1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Rockchip DesignWare based PCIe host controller driver 4 * 5 * Copyright (c) 2021 Rockchip, Inc. 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <dm.h> 11 #include <generic-phy.h> 12 #include <pci.h> 13 #include <power-domain.h> 14 #include <power/regulator.h> 15 #include <reset.h> 16 #include <syscon.h> 17 #include <asm/io.h> 18 #include <asm-generic/gpio.h> 19 #include <asm/arch-rockchip/clock.h> 20 #include <linux/iopoll.h> 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 #define RK_PCIE_DBG 0 25 26 #define __pcie_dev_print_emit(fmt, ...) \ 27 ({ \ 28 printf(fmt, ##__VA_ARGS__); \ 29 }) 30 31 #ifdef dev_err 32 #undef dev_err 33 #define dev_err(dev, fmt, ...) \ 34 ({ \ 35 if (dev) \ 36 __pcie_dev_print_emit("%s: " fmt, dev->name, \ 37 ##__VA_ARGS__); \ 38 }) 39 #endif 40 41 #ifdef dev_info 42 #undef dev_info 43 #define dev_info dev_err 44 #endif 45 46 #ifdef DEBUG 47 #define dev_dbg dev_err 48 #else 49 #define dev_dbg(dev, fmt, ...) \ 50 ({ \ 51 if (0) \ 52 __dev_printk(7, dev, fmt, ##__VA_ARGS__); \ 53 }) 54 #endif 55 56 struct rk_pcie { 57 struct udevice *dev; 58 struct udevice *vpcie3v3; 59 void *dbi_base; 60 void *apb_base; 61 void *cfg_base; 62 fdt_size_t cfg_size; 63 struct phy phy; 64 struct clk_bulk clks; 65 int first_busno; 66 struct reset_ctl_bulk rsts; 67 struct gpio_desc rst_gpio; 68 struct pci_region io; 69 struct pci_region mem; 70 bool is_bifurcation; 71 u32 gen; 72 }; 73 74 enum { 75 PCIBIOS_SUCCESSFUL = 0x0000, 76 PCIBIOS_UNSUPPORTED = -ENODEV, 77 PCIBIOS_NODEV = -ENODEV, 78 }; 79 80 #define msleep(a) udelay((a) * 1000) 81 82 /* Parameters for the waiting for iATU enabled routine */ 83 #define PCIE_CLIENT_GENERAL_DEBUG 0x104 84 #define PCIE_CLIENT_HOT_RESET_CTRL 0x180 85 #define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) 86 #define PCIE_CLIENT_LTSSM_STATUS 0x300 87 #define SMLH_LINKUP BIT(16) 88 #define RDLH_LINKUP BIT(17) 89 #define PCIE_CLIENT_DBG_FIFO_MODE_CON 0x310 90 #define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0 0x320 91 #define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1 0x324 92 #define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0 0x328 93 #define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1 0x32c 94 #define PCIE_CLIENT_DBG_FIFO_STATUS 0x350 95 #define PCIE_CLIENT_DBG_TRANSITION_DATA 0xffff0000 96 #define PCIE_CLIENT_DBF_EN 0xffff0003 97 98 /* PCI DBICS registers */ 99 #define PCIE_LINK_STATUS_REG 0x80 100 #define PCIE_LINK_STATUS_SPEED_OFF 16 101 #define PCIE_LINK_STATUS_SPEED_MASK (0xf << PCIE_LINK_STATUS_SPEED_OFF) 102 #define PCIE_LINK_STATUS_WIDTH_OFF 20 103 #define PCIE_LINK_STATUS_WIDTH_MASK (0xf << PCIE_LINK_STATUS_WIDTH_OFF) 104 105 #define PCIE_LINK_CAPABILITY 0x7c 106 #define PCIE_LINK_CTL_2 0xa0 107 #define TARGET_LINK_SPEED_MASK 0xf 108 #define LINK_SPEED_GEN_1 0x1 109 #define LINK_SPEED_GEN_2 0x2 110 #define LINK_SPEED_GEN_3 0x3 111 112 #define PCIE_MISC_CONTROL_1_OFF 0x8bc 113 #define PCIE_DBI_RO_WR_EN BIT(0) 114 115 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80c 116 #define PORT_LOGIC_SPEED_CHANGE BIT(17) 117 118 /* 119 * iATU Unroll-specific register definitions 120 * From 4.80 core version the address translation will be made by unroll. 121 * The registers are offset from atu_base 122 */ 123 #define PCIE_ATU_UNR_REGION_CTRL1 0x00 124 #define PCIE_ATU_UNR_REGION_CTRL2 0x04 125 #define PCIE_ATU_UNR_LOWER_BASE 0x08 126 #define PCIE_ATU_UNR_UPPER_BASE 0x0c 127 #define PCIE_ATU_UNR_LIMIT 0x10 128 #define PCIE_ATU_UNR_LOWER_TARGET 0x14 129 #define PCIE_ATU_UNR_UPPER_TARGET 0x18 130 131 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0) 132 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0) 133 #define PCIE_ATU_TYPE_MEM (0x0 << 0) 134 #define PCIE_ATU_TYPE_IO (0x2 << 0) 135 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0) 136 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0) 137 #define PCIE_ATU_ENABLE (0x1 << 31) 138 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) 139 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) 140 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) 141 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) 142 143 /* Register address builder */ 144 #define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) \ 145 ((0x3 << 20) | ((region) << 9)) 146 #define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region) \ 147 ((0x3 << 20) | ((region) << 9) | (0x1 << 8)) 148 149 /* Parameters for the waiting for iATU enabled routine */ 150 #define LINK_WAIT_MAX_IATU_RETRIES 5 151 #define LINK_WAIT_IATU 10000 152 153 static int rk_pcie_read(void __iomem *addr, int size, u32 *val) 154 { 155 if ((uintptr_t)addr & (size - 1)) { 156 *val = 0; 157 return PCIBIOS_UNSUPPORTED; 158 } 159 160 if (size == 4) { 161 *val = readl(addr); 162 } else if (size == 2) { 163 *val = readw(addr); 164 } else if (size == 1) { 165 *val = readb(addr); 166 } else { 167 *val = 0; 168 return PCIBIOS_NODEV; 169 } 170 171 return PCIBIOS_SUCCESSFUL; 172 } 173 174 static int rk_pcie_write(void __iomem *addr, int size, u32 val) 175 { 176 if ((uintptr_t)addr & (size - 1)) 177 return PCIBIOS_UNSUPPORTED; 178 179 if (size == 4) 180 writel(val, addr); 181 else if (size == 2) 182 writew(val, addr); 183 else if (size == 1) 184 writeb(val, addr); 185 else 186 return PCIBIOS_NODEV; 187 188 return PCIBIOS_SUCCESSFUL; 189 } 190 191 static u32 __rk_pcie_read_apb(struct rk_pcie *rk_pcie, void __iomem *base, 192 u32 reg, size_t size) 193 { 194 int ret; 195 u32 val; 196 197 ret = rk_pcie_read(base + reg, size, &val); 198 if (ret) 199 dev_err(rk_pcie->dev, "Read APB address failed\n"); 200 201 return val; 202 } 203 204 static void __rk_pcie_write_apb(struct rk_pcie *rk_pcie, void __iomem *base, 205 u32 reg, size_t size, u32 val) 206 { 207 int ret; 208 209 ret = rk_pcie_write(base + reg, size, val); 210 if (ret) 211 dev_err(rk_pcie->dev, "Write APB address failed\n"); 212 } 213 214 static inline u32 rk_pcie_readl_apb(struct rk_pcie *rk_pcie, u32 reg) 215 { 216 return __rk_pcie_read_apb(rk_pcie, rk_pcie->apb_base, reg, 0x4); 217 } 218 219 static inline void rk_pcie_writel_apb(struct rk_pcie *rk_pcie, u32 reg, 220 u32 val) 221 { 222 __rk_pcie_write_apb(rk_pcie, rk_pcie->apb_base, reg, 0x4, val); 223 } 224 225 static int rk_pcie_get_link_speed(struct rk_pcie *rk_pcie) 226 { 227 return (readl(rk_pcie->dbi_base + PCIE_LINK_STATUS_REG) & 228 PCIE_LINK_STATUS_SPEED_MASK) >> PCIE_LINK_STATUS_SPEED_OFF; 229 } 230 231 static int rk_pcie_get_link_width(struct rk_pcie *rk_pcie) 232 { 233 return (readl(rk_pcie->dbi_base + PCIE_LINK_STATUS_REG) & 234 PCIE_LINK_STATUS_WIDTH_MASK) >> PCIE_LINK_STATUS_WIDTH_OFF; 235 } 236 237 static void rk_pcie_writel_ob_unroll(struct rk_pcie *rk_pcie, u32 index, 238 u32 reg, u32 val) 239 { 240 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); 241 void __iomem *base = rk_pcie->dbi_base; 242 243 writel(val, base + offset + reg); 244 } 245 246 static u32 rk_pcie_readl_ob_unroll(struct rk_pcie *rk_pcie, u32 index, u32 reg) 247 { 248 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); 249 void __iomem *base = rk_pcie->dbi_base; 250 251 return readl(base + offset + reg); 252 } 253 254 static inline void rk_pcie_dbi_write_enable(struct rk_pcie *rk_pcie, bool en) 255 { 256 u32 val; 257 258 val = readl(rk_pcie->dbi_base + PCIE_MISC_CONTROL_1_OFF); 259 260 if (en) 261 val |= PCIE_DBI_RO_WR_EN; 262 else 263 val &= ~PCIE_DBI_RO_WR_EN; 264 writel(val, rk_pcie->dbi_base + PCIE_MISC_CONTROL_1_OFF); 265 } 266 267 static void rk_pcie_setup_host(struct rk_pcie *rk_pcie) 268 { 269 u32 val; 270 271 rk_pcie_dbi_write_enable(rk_pcie, true); 272 273 /* setup RC BARs */ 274 writel(PCI_BASE_ADDRESS_MEM_TYPE_64, 275 rk_pcie->dbi_base + PCI_BASE_ADDRESS_0); 276 writel(0x0, rk_pcie->dbi_base + PCI_BASE_ADDRESS_1); 277 278 /* setup interrupt pins */ 279 val = readl(rk_pcie->dbi_base + PCI_INTERRUPT_LINE); 280 val &= 0xffff00ff; 281 val |= 0x00000100; 282 writel(val, rk_pcie->dbi_base + PCI_INTERRUPT_LINE); 283 284 /* setup bus numbers */ 285 val = readl(rk_pcie->dbi_base + PCI_PRIMARY_BUS); 286 val &= 0xff000000; 287 val |= 0x00ff0100; 288 writel(val, rk_pcie->dbi_base + PCI_PRIMARY_BUS); 289 290 val = readl(rk_pcie->dbi_base + PCI_PRIMARY_BUS); 291 292 /* setup command register */ 293 val = readl(rk_pcie->dbi_base + PCI_COMMAND); 294 val &= 0xffff0000; 295 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 296 PCI_COMMAND_MASTER | PCI_COMMAND_SERR; 297 writel(val, rk_pcie->dbi_base + PCI_COMMAND); 298 299 /* program correct class for RC */ 300 writew(PCI_CLASS_BRIDGE_PCI, rk_pcie->dbi_base + PCI_CLASS_DEVICE); 301 /* Better disable write permission right after the update */ 302 303 val = readl(rk_pcie->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); 304 val |= PORT_LOGIC_SPEED_CHANGE; 305 writel(val, rk_pcie->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); 306 307 rk_pcie_dbi_write_enable(rk_pcie, false); 308 } 309 310 static void rk_pcie_configure(struct rk_pcie *pci, u32 cap_speed) 311 { 312 u32 val; 313 314 rk_pcie_dbi_write_enable(pci, true); 315 316 val = readl(pci->dbi_base + PCIE_LINK_CAPABILITY); 317 val &= ~TARGET_LINK_SPEED_MASK; 318 val |= cap_speed; 319 writel(val, pci->dbi_base + PCIE_LINK_CAPABILITY); 320 321 val = readl(pci->dbi_base + PCIE_LINK_CTL_2); 322 val &= ~TARGET_LINK_SPEED_MASK; 323 val |= cap_speed; 324 writel(val, pci->dbi_base + PCIE_LINK_CTL_2); 325 326 rk_pcie_dbi_write_enable(pci, false); 327 } 328 329 static void rk_pcie_prog_outbound_atu_unroll(struct rk_pcie *pci, int index, 330 int type, u64 cpu_addr, 331 u64 pci_addr, u32 size) 332 { 333 u32 retries, val; 334 335 dev_dbg(pci->dev, "ATU programmed with: index: %d, type: %d, cpu addr: %8llx, pci addr: %8llx, size: %8x\n", 336 index, type, cpu_addr, pci_addr, size); 337 338 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE, 339 lower_32_bits(cpu_addr)); 340 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE, 341 upper_32_bits(cpu_addr)); 342 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LIMIT, 343 lower_32_bits(cpu_addr + size - 1)); 344 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET, 345 lower_32_bits(pci_addr)); 346 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET, 347 upper_32_bits(pci_addr)); 348 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, 349 type); 350 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2, 351 PCIE_ATU_ENABLE); 352 353 /* 354 * Make sure ATU enable takes effect before any subsequent config 355 * and I/O accesses. 356 */ 357 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { 358 val = rk_pcie_readl_ob_unroll(pci, index, 359 PCIE_ATU_UNR_REGION_CTRL2); 360 if (val & PCIE_ATU_ENABLE) 361 return; 362 363 udelay(LINK_WAIT_IATU); 364 } 365 dev_err(pci->dev, "outbound iATU is not being enabled\n"); 366 } 367 368 static int rk_pcie_addr_valid(pci_dev_t d, int first_busno) 369 { 370 if ((PCI_BUS(d) == first_busno) && (PCI_DEV(d) > 0)) 371 return 0; 372 if ((PCI_BUS(d) == first_busno + 1) && (PCI_DEV(d) > 0)) 373 return 0; 374 375 return 1; 376 } 377 378 static uintptr_t set_cfg_address(struct rk_pcie *pcie, 379 pci_dev_t d, uint where) 380 { 381 int bus = PCI_BUS(d) - pcie->first_busno; 382 uintptr_t va_address; 383 u32 atu_type; 384 385 /* Use dbi_base for own configuration read and write */ 386 if (!bus) { 387 va_address = (uintptr_t)pcie->dbi_base; 388 goto out; 389 } 390 391 if (bus == 1) 392 /* 393 * For local bus whose primary bus number is root bridge, 394 * change TLP Type field to 4. 395 */ 396 atu_type = PCIE_ATU_TYPE_CFG0; 397 else 398 /* Otherwise, change TLP Type field to 5. */ 399 atu_type = PCIE_ATU_TYPE_CFG1; 400 401 /* 402 * Not accessing root port configuration space? 403 * Region #0 is used for Outbound CFG space access. 404 * Direction = Outbound 405 * Region Index = 0 406 */ 407 d = PCI_MASK_BUS(d); 408 d = PCI_ADD_BUS(bus, d); 409 rk_pcie_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1, 410 atu_type, (u64)pcie->cfg_base, 411 d << 8, pcie->cfg_size); 412 413 va_address = (uintptr_t)pcie->cfg_base; 414 415 out: 416 va_address += where & ~0x3; 417 418 return va_address; 419 } 420 421 static int rockchip_pcie_rd_conf(struct udevice *bus, pci_dev_t bdf, 422 uint offset, ulong *valuep, 423 enum pci_size_t size) 424 { 425 struct rk_pcie *pcie = dev_get_priv(bus); 426 uintptr_t va_address; 427 ulong value; 428 429 debug("PCIE CFG read: bdf=%2x:%2x:%2x\n", 430 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); 431 432 if (!rk_pcie_addr_valid(bdf, pcie->first_busno)) { 433 debug("- out of range\n"); 434 *valuep = pci_get_ff(size); 435 return 0; 436 } 437 438 va_address = set_cfg_address(pcie, bdf, offset); 439 440 value = readl(va_address); 441 442 debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value); 443 *valuep = pci_conv_32_to_size(value, offset, size); 444 445 rk_pcie_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1, 446 PCIE_ATU_TYPE_IO, pcie->io.phys_start, 447 pcie->io.bus_start, pcie->io.size); 448 449 return 0; 450 } 451 452 static int rockchip_pcie_wr_conf(struct udevice *bus, pci_dev_t bdf, 453 uint offset, ulong value, 454 enum pci_size_t size) 455 { 456 struct rk_pcie *pcie = dev_get_priv(bus); 457 uintptr_t va_address; 458 ulong old; 459 460 debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d)\n", 461 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); 462 debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value); 463 464 if (!rk_pcie_addr_valid(bdf, pcie->first_busno)) { 465 debug("- out of range\n"); 466 return 0; 467 } 468 469 va_address = set_cfg_address(pcie, bdf, offset); 470 471 old = readl(va_address); 472 value = pci_conv_size_to_32(old, value, offset, size); 473 writel(value, va_address); 474 475 rk_pcie_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1, 476 PCIE_ATU_TYPE_IO, pcie->io.phys_start, 477 pcie->io.bus_start, pcie->io.size); 478 479 return 0; 480 } 481 482 static void rk_pcie_enable_debug(struct rk_pcie *rk_pcie) 483 { 484 #if RK_PCIE_DBG 485 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0, 486 PCIE_CLIENT_DBG_TRANSITION_DATA); 487 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1, 488 PCIE_CLIENT_DBG_TRANSITION_DATA); 489 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0, 490 PCIE_CLIENT_DBG_TRANSITION_DATA); 491 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1, 492 PCIE_CLIENT_DBG_TRANSITION_DATA); 493 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_MODE_CON, 494 PCIE_CLIENT_DBF_EN); 495 #endif 496 } 497 498 static void rk_pcie_debug_dump(struct rk_pcie *rk_pcie) 499 { 500 #if RK_PCIE_DBG 501 u32 loop; 502 503 dev_err(rk_pcie->dev, "ltssm = 0x%x\n", 504 rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_LTSSM_STATUS)); 505 for (loop = 0; loop < 64; loop++) 506 dev_err(rk_pcie->dev, "fifo_status = 0x%x\n", 507 rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_STATUS)); 508 #endif 509 } 510 511 static inline void rk_pcie_link_status_clear(struct rk_pcie *rk_pcie) 512 { 513 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_GENERAL_DEBUG, 0x0); 514 } 515 516 static inline void rk_pcie_disable_ltssm(struct rk_pcie *rk_pcie) 517 { 518 rk_pcie_writel_apb(rk_pcie, 0x0, 0xc0008); 519 } 520 521 static inline void rk_pcie_enable_ltssm(struct rk_pcie *rk_pcie) 522 { 523 rk_pcie_writel_apb(rk_pcie, 0x0, 0xc000c); 524 } 525 526 static int is_link_up(struct rk_pcie *priv) 527 { 528 u32 val; 529 530 val = rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS); 531 if ((val & (RDLH_LINKUP | SMLH_LINKUP)) == 0x30000 && 532 (val & GENMASK(5, 0)) == 0x11) 533 return 1; 534 535 return 0; 536 } 537 538 static int rk_pcie_link_up(struct rk_pcie *priv, u32 cap_speed) 539 { 540 int retries; 541 542 if (is_link_up(priv)) { 543 printf("PCI Link already up before configuration!\n"); 544 return 1; 545 } 546 547 /* DW pre link configurations */ 548 rk_pcie_configure(priv, cap_speed); 549 550 /* Release the device */ 551 if (dm_gpio_is_valid(&priv->rst_gpio)) { 552 /* 553 * T_PVPERL (Power stable to PERST# inactive) should be a minimum of 100ms. 554 * We add a 200ms by default for sake of hoping everthings 555 * work fine. 556 */ 557 msleep(200); 558 dm_gpio_set_value(&priv->rst_gpio, 1); 559 /* 560 * Add this 20ms delay because we observe link is always up stably after it and 561 * could help us save 20ms for scanning devices. 562 */ 563 msleep(20); 564 } 565 566 rk_pcie_disable_ltssm(priv); 567 rk_pcie_link_status_clear(priv); 568 rk_pcie_enable_debug(priv); 569 570 /* Enable LTSSM */ 571 rk_pcie_enable_ltssm(priv); 572 573 for (retries = 0; retries < 50; retries++) { 574 if (is_link_up(priv)) { 575 dev_info(priv->dev, "PCIe Link up, LTSSM is 0x%x\n", 576 rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS)); 577 rk_pcie_debug_dump(priv); 578 /* Link maybe in Gen switch recovery but we need to wait more 1s */ 579 msleep(1000); 580 return 0; 581 } 582 583 dev_info(priv->dev, "PCIe Linking... LTSSM is 0x%x\n", 584 rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS)); 585 rk_pcie_debug_dump(priv); 586 msleep(10); 587 } 588 589 dev_err(priv->dev, "PCIe-%d Link Fail\n", priv->dev->seq); 590 return -EINVAL; 591 } 592 593 static int rockchip_pcie_init_port(struct udevice *dev) 594 { 595 int ret; 596 u32 val; 597 struct rk_pcie *priv = dev_get_priv(dev); 598 union phy_configure_opts phy_cfg; 599 600 /* Rest the device */ 601 if (dm_gpio_is_valid(&priv->rst_gpio)) 602 dm_gpio_set_value(&priv->rst_gpio, 0); 603 604 /* Set power and maybe external ref clk input */ 605 if (priv->vpcie3v3) { 606 ret = regulator_set_enable(priv->vpcie3v3, true); 607 if (ret) { 608 dev_err(priv->dev, "failed to enable vpcie3v3 (ret=%d)\n", 609 ret); 610 return ret; 611 } 612 } 613 614 if (priv->is_bifurcation) { 615 phy_cfg.pcie.is_bifurcation = true; 616 ret = generic_phy_configure(&priv->phy, &phy_cfg); 617 if (ret) 618 dev_err(dev, "failed to set bifurcation for phy (ret=%d)\n", ret); 619 } 620 621 ret = generic_phy_init(&priv->phy); 622 if (ret) { 623 dev_err(dev, "failed to init phy (ret=%d)\n", ret); 624 return ret; 625 } 626 627 ret = generic_phy_power_on(&priv->phy); 628 if (ret) { 629 dev_err(dev, "failed to power on phy (ret=%d)\n", ret); 630 goto err_exit_phy; 631 } 632 633 ret = reset_deassert_bulk(&priv->rsts); 634 if (ret) { 635 dev_err(dev, "failed to deassert resets (ret=%d)\n", ret); 636 goto err_power_off_phy; 637 } 638 639 ret = clk_enable_bulk(&priv->clks); 640 if (ret) { 641 dev_err(dev, "failed to enable clks (ret=%d)\n", ret); 642 goto err_deassert_bulk; 643 } 644 645 /* LTSSM EN ctrl mode */ 646 val = rk_pcie_readl_apb(priv, PCIE_CLIENT_HOT_RESET_CTRL); 647 val |= PCIE_LTSSM_ENABLE_ENHANCE | (PCIE_LTSSM_ENABLE_ENHANCE << 16); 648 rk_pcie_writel_apb(priv, PCIE_CLIENT_HOT_RESET_CTRL, val); 649 650 /* Set RC mode */ 651 rk_pcie_writel_apb(priv, 0x0, 0xf00040); 652 rk_pcie_setup_host(priv); 653 654 ret = rk_pcie_link_up(priv, priv->gen); 655 if (ret < 0) 656 goto err_link_up; 657 658 return 0; 659 err_link_up: 660 clk_disable_bulk(&priv->clks); 661 err_deassert_bulk: 662 reset_assert_bulk(&priv->rsts); 663 err_power_off_phy: 664 generic_phy_power_off(&priv->phy); 665 err_exit_phy: 666 generic_phy_exit(&priv->phy); 667 return ret; 668 } 669 670 static int rockchip_pcie_parse_dt(struct udevice *dev) 671 { 672 struct rk_pcie *priv = dev_get_priv(dev); 673 u32 max_link_speed; 674 int ret; 675 676 priv->dbi_base = (void *)dev_read_addr_index(dev, 0); 677 if (!priv->dbi_base) 678 return -ENODEV; 679 680 dev_dbg(dev, "DBI address is 0x%p\n", priv->dbi_base); 681 682 priv->apb_base = (void *)dev_read_addr_index(dev, 1); 683 if (!priv->apb_base) 684 return -ENODEV; 685 686 dev_dbg(dev, "APB address is 0x%p\n", priv->apb_base); 687 688 ret = gpio_request_by_name(dev, "reset-gpios", 0, 689 &priv->rst_gpio, GPIOD_IS_OUT); 690 if (ret) { 691 dev_err(dev, "failed to find reset-gpios property\n"); 692 return ret; 693 } 694 695 ret = reset_get_bulk(dev, &priv->rsts); 696 if (ret) { 697 dev_err(dev, "Can't get reset: %d\n", ret); 698 return ret; 699 } 700 701 ret = clk_get_bulk(dev, &priv->clks); 702 if (ret) { 703 dev_err(dev, "Can't get clock: %d\n", ret); 704 return ret; 705 } 706 707 ret = device_get_supply_regulator(dev, "vpcie3v3-supply", 708 &priv->vpcie3v3); 709 if (ret && ret != -ENOENT) { 710 dev_err(dev, "failed to get vpcie3v3 supply (ret=%d)\n", ret); 711 return ret; 712 } 713 714 ret = generic_phy_get_by_index(dev, 0, &priv->phy); 715 if (ret) { 716 dev_err(dev, "failed to get pcie phy (ret=%d)\n", ret); 717 return ret; 718 } 719 720 if (dev_read_bool(dev, "rockchip,bifurcation")) 721 priv->is_bifurcation = true; 722 723 ret = ofnode_read_u32(dev->node, "max-link-speed", &max_link_speed); 724 if (ret < 0 || max_link_speed > 4) 725 priv->gen = 0; 726 else 727 priv->gen = max_link_speed; 728 729 return 0; 730 } 731 732 static int rockchip_pcie_probe(struct udevice *dev) 733 { 734 struct rk_pcie *priv = dev_get_priv(dev); 735 struct udevice *ctlr = pci_get_controller(dev); 736 struct pci_controller *hose = dev_get_uclass_priv(ctlr); 737 int ret; 738 739 priv->first_busno = dev->seq; 740 priv->dev = dev; 741 742 ret = rockchip_pcie_parse_dt(dev); 743 if (ret) 744 return ret; 745 746 ret = rockchip_pcie_init_port(dev); 747 if (ret) 748 return ret; 749 750 dev_info(dev, "PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", 751 dev->seq, rk_pcie_get_link_speed(priv), 752 rk_pcie_get_link_width(priv), 753 hose->first_busno); 754 755 for (ret = 0; ret < hose->region_count; ret++) { 756 if (hose->regions[ret].flags == PCI_REGION_IO) { 757 priv->io.phys_start = hose->regions[ret].phys_start; /* IO base */ 758 priv->io.bus_start = hose->regions[ret].bus_start; /* IO_bus_addr */ 759 priv->io.size = hose->regions[ret].size; /* IO size */ 760 } else if (hose->regions[ret].flags == PCI_REGION_MEM) { 761 priv->mem.phys_start = hose->regions[ret].phys_start; /* MEM base */ 762 priv->mem.bus_start = hose->regions[ret].bus_start; /* MEM_bus_addr */ 763 priv->mem.size = hose->regions[ret].size; /* MEM size */ 764 } else if (hose->regions[ret].flags == PCI_REGION_SYS_MEMORY) { 765 priv->cfg_base = (void *)(priv->io.phys_start - priv->io.size); 766 priv->cfg_size = priv->io.size; 767 } else { 768 dev_err(dev, "invalid flags type!\n"); 769 } 770 } 771 772 dev_dbg(dev, "Config space: [0x%p - 0x%p, size 0x%llx]\n", 773 priv->cfg_base, priv->cfg_base + priv->cfg_size, 774 priv->cfg_size); 775 776 dev_dbg(dev, "IO space: [0x%llx - 0x%llx, size 0x%x]\n", 777 priv->io.phys_start, priv->io.phys_start + priv->io.size, 778 priv->io.size); 779 780 dev_dbg(dev, "IO bus: [0x%x - 0x%x, size 0x%x]\n", 781 priv->io.bus_start, priv->io.bus_start + priv->io.size, 782 priv->io.size); 783 784 dev_dbg(dev, "MEM space: [0x%llx - 0x%llx, size 0x%x]\n", 785 priv->mem.phys_start, priv->mem.phys_start + priv->mem.size, 786 priv->mem.size); 787 788 dev_dbg(dev, "MEM bus: [0x%x - 0x%x, size 0x%x]\n", 789 priv->mem.bus_start, priv->mem.bus_start + priv->mem.size, 790 priv->mem.size); 791 792 rk_pcie_prog_outbound_atu_unroll(priv, PCIE_ATU_REGION_INDEX0, 793 PCIE_ATU_TYPE_MEM, 794 priv->mem.phys_start, 795 priv->mem.bus_start, priv->mem.size); 796 return 0; 797 } 798 799 static const struct dm_pci_ops rockchip_pcie_ops = { 800 .read_config = rockchip_pcie_rd_conf, 801 .write_config = rockchip_pcie_wr_conf, 802 }; 803 804 static const struct udevice_id rockchip_pcie_ids[] = { 805 { .compatible = "rockchip,rk3528-pcie" }, 806 { .compatible = "rockchip,rk3568-pcie" }, 807 { .compatible = "rockchip,rk3588-pcie" }, 808 { } 809 }; 810 811 U_BOOT_DRIVER(rockchip_pcie) = { 812 .name = "pcie_dw_rockchip", 813 .id = UCLASS_PCI, 814 .of_match = rockchip_pcie_ids, 815 .ops = &rockchip_pcie_ops, 816 .probe = rockchip_pcie_probe, 817 .priv_auto_alloc_size = sizeof(struct rk_pcie), 818 }; 819