1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Rockchip DesignWare based PCIe host controller driver 4 * 5 * Copyright (c) 2021 Rockchip, Inc. 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <dm.h> 11 #include <generic-phy.h> 12 #include <pci.h> 13 #include <power-domain.h> 14 #include <power/regulator.h> 15 #include <reset.h> 16 #include <syscon.h> 17 #include <asm/io.h> 18 #include <asm-generic/gpio.h> 19 #include <asm/arch-rockchip/clock.h> 20 #include <linux/iopoll.h> 21 #include <linux/ioport.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #define RK_PCIE_DBG 0 26 27 #define __pcie_dev_print_emit(fmt, ...) \ 28 ({ \ 29 printf(fmt, ##__VA_ARGS__); \ 30 }) 31 32 #ifdef dev_err 33 #undef dev_err 34 #define dev_err(dev, fmt, ...) \ 35 ({ \ 36 if (dev) \ 37 __pcie_dev_print_emit("%s: " fmt, dev->name, \ 38 ##__VA_ARGS__); \ 39 }) 40 #endif 41 42 #ifdef dev_info 43 #undef dev_info 44 #define dev_info dev_err 45 #endif 46 47 #ifdef DEBUG 48 #define dev_dbg dev_err 49 #else 50 #define dev_dbg(dev, fmt, ...) \ 51 ({ \ 52 if (0) \ 53 __dev_printk(7, dev, fmt, ##__VA_ARGS__); \ 54 }) 55 #endif 56 57 struct rk_pcie { 58 struct udevice *dev; 59 struct udevice *vpcie3v3; 60 void *dbi_base; 61 void *apb_base; 62 void *cfg_base; 63 fdt_size_t cfg_size; 64 struct phy phy; 65 struct clk_bulk clks; 66 int first_busno; 67 struct reset_ctl_bulk rsts; 68 struct gpio_desc rst_gpio; 69 struct pci_region io; 70 struct pci_region mem; 71 bool is_bifurcation; 72 u32 gen; 73 }; 74 75 enum { 76 PCIBIOS_SUCCESSFUL = 0x0000, 77 PCIBIOS_UNSUPPORTED = -ENODEV, 78 PCIBIOS_NODEV = -ENODEV, 79 }; 80 81 #define msleep(a) udelay((a) * 1000) 82 83 /* Parameters for the waiting for iATU enabled routine */ 84 #define PCIE_CLIENT_GENERAL_DEBUG 0x104 85 #define PCIE_CLIENT_HOT_RESET_CTRL 0x180 86 #define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) 87 #define PCIE_CLIENT_LTSSM_STATUS 0x300 88 #define SMLH_LINKUP BIT(16) 89 #define RDLH_LINKUP BIT(17) 90 #define PCIE_CLIENT_DBG_FIFO_MODE_CON 0x310 91 #define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0 0x320 92 #define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1 0x324 93 #define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0 0x328 94 #define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1 0x32c 95 #define PCIE_CLIENT_DBG_FIFO_STATUS 0x350 96 #define PCIE_CLIENT_DBG_TRANSITION_DATA 0xffff0000 97 #define PCIE_CLIENT_DBF_EN 0xffff0003 98 99 /* PCI DBICS registers */ 100 #define PCIE_LINK_STATUS_REG 0x80 101 #define PCIE_LINK_STATUS_SPEED_OFF 16 102 #define PCIE_LINK_STATUS_SPEED_MASK (0xf << PCIE_LINK_STATUS_SPEED_OFF) 103 #define PCIE_LINK_STATUS_WIDTH_OFF 20 104 #define PCIE_LINK_STATUS_WIDTH_MASK (0xf << PCIE_LINK_STATUS_WIDTH_OFF) 105 106 #define PCIE_LINK_CAPABILITY 0x7c 107 #define PCIE_LINK_CTL_2 0xa0 108 #define TARGET_LINK_SPEED_MASK 0xf 109 #define LINK_SPEED_GEN_1 0x1 110 #define LINK_SPEED_GEN_2 0x2 111 #define LINK_SPEED_GEN_3 0x3 112 113 #define PCIE_MISC_CONTROL_1_OFF 0x8bc 114 #define PCIE_DBI_RO_WR_EN BIT(0) 115 116 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80c 117 #define PORT_LOGIC_SPEED_CHANGE BIT(17) 118 119 /* 120 * iATU Unroll-specific register definitions 121 * From 4.80 core version the address translation will be made by unroll. 122 * The registers are offset from atu_base 123 */ 124 #define PCIE_ATU_UNR_REGION_CTRL1 0x00 125 #define PCIE_ATU_UNR_REGION_CTRL2 0x04 126 #define PCIE_ATU_UNR_LOWER_BASE 0x08 127 #define PCIE_ATU_UNR_UPPER_BASE 0x0c 128 #define PCIE_ATU_UNR_LIMIT 0x10 129 #define PCIE_ATU_UNR_LOWER_TARGET 0x14 130 #define PCIE_ATU_UNR_UPPER_TARGET 0x18 131 132 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0) 133 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0) 134 #define PCIE_ATU_TYPE_MEM (0x0 << 0) 135 #define PCIE_ATU_TYPE_IO (0x2 << 0) 136 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0) 137 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0) 138 #define PCIE_ATU_ENABLE (0x1 << 31) 139 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) 140 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) 141 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) 142 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) 143 144 /* Register address builder */ 145 #define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) \ 146 ((0x3 << 20) | ((region) << 9)) 147 #define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region) \ 148 ((0x3 << 20) | ((region) << 9) | (0x1 << 8)) 149 150 /* Parameters for the waiting for iATU enabled routine */ 151 #define LINK_WAIT_MAX_IATU_RETRIES 5 152 #define LINK_WAIT_IATU 10000 153 154 static int rk_pcie_read(void __iomem *addr, int size, u32 *val) 155 { 156 if ((uintptr_t)addr & (size - 1)) { 157 *val = 0; 158 return PCIBIOS_UNSUPPORTED; 159 } 160 161 if (size == 4) { 162 *val = readl(addr); 163 } else if (size == 2) { 164 *val = readw(addr); 165 } else if (size == 1) { 166 *val = readb(addr); 167 } else { 168 *val = 0; 169 return PCIBIOS_NODEV; 170 } 171 172 return PCIBIOS_SUCCESSFUL; 173 } 174 175 static int rk_pcie_write(void __iomem *addr, int size, u32 val) 176 { 177 if ((uintptr_t)addr & (size - 1)) 178 return PCIBIOS_UNSUPPORTED; 179 180 if (size == 4) 181 writel(val, addr); 182 else if (size == 2) 183 writew(val, addr); 184 else if (size == 1) 185 writeb(val, addr); 186 else 187 return PCIBIOS_NODEV; 188 189 return PCIBIOS_SUCCESSFUL; 190 } 191 192 static u32 __rk_pcie_read_apb(struct rk_pcie *rk_pcie, void __iomem *base, 193 u32 reg, size_t size) 194 { 195 int ret; 196 u32 val; 197 198 ret = rk_pcie_read(base + reg, size, &val); 199 if (ret) 200 dev_err(rk_pcie->dev, "Read APB address failed\n"); 201 202 return val; 203 } 204 205 static void __rk_pcie_write_apb(struct rk_pcie *rk_pcie, void __iomem *base, 206 u32 reg, size_t size, u32 val) 207 { 208 int ret; 209 210 ret = rk_pcie_write(base + reg, size, val); 211 if (ret) 212 dev_err(rk_pcie->dev, "Write APB address failed\n"); 213 } 214 215 static inline u32 rk_pcie_readl_apb(struct rk_pcie *rk_pcie, u32 reg) 216 { 217 return __rk_pcie_read_apb(rk_pcie, rk_pcie->apb_base, reg, 0x4); 218 } 219 220 static inline void rk_pcie_writel_apb(struct rk_pcie *rk_pcie, u32 reg, 221 u32 val) 222 { 223 __rk_pcie_write_apb(rk_pcie, rk_pcie->apb_base, reg, 0x4, val); 224 } 225 226 static int rk_pcie_get_link_speed(struct rk_pcie *rk_pcie) 227 { 228 return (readl(rk_pcie->dbi_base + PCIE_LINK_STATUS_REG) & 229 PCIE_LINK_STATUS_SPEED_MASK) >> PCIE_LINK_STATUS_SPEED_OFF; 230 } 231 232 static int rk_pcie_get_link_width(struct rk_pcie *rk_pcie) 233 { 234 return (readl(rk_pcie->dbi_base + PCIE_LINK_STATUS_REG) & 235 PCIE_LINK_STATUS_WIDTH_MASK) >> PCIE_LINK_STATUS_WIDTH_OFF; 236 } 237 238 static void rk_pcie_writel_ob_unroll(struct rk_pcie *rk_pcie, u32 index, 239 u32 reg, u32 val) 240 { 241 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); 242 void __iomem *base = rk_pcie->dbi_base; 243 244 writel(val, base + offset + reg); 245 } 246 247 static u32 rk_pcie_readl_ob_unroll(struct rk_pcie *rk_pcie, u32 index, u32 reg) 248 { 249 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); 250 void __iomem *base = rk_pcie->dbi_base; 251 252 return readl(base + offset + reg); 253 } 254 255 static inline void rk_pcie_dbi_write_enable(struct rk_pcie *rk_pcie, bool en) 256 { 257 u32 val; 258 259 val = readl(rk_pcie->dbi_base + PCIE_MISC_CONTROL_1_OFF); 260 261 if (en) 262 val |= PCIE_DBI_RO_WR_EN; 263 else 264 val &= ~PCIE_DBI_RO_WR_EN; 265 writel(val, rk_pcie->dbi_base + PCIE_MISC_CONTROL_1_OFF); 266 } 267 268 static void rk_pcie_setup_host(struct rk_pcie *rk_pcie) 269 { 270 u32 val; 271 272 rk_pcie_dbi_write_enable(rk_pcie, true); 273 274 /* setup RC BARs */ 275 writel(PCI_BASE_ADDRESS_MEM_TYPE_64, 276 rk_pcie->dbi_base + PCI_BASE_ADDRESS_0); 277 writel(0x0, rk_pcie->dbi_base + PCI_BASE_ADDRESS_1); 278 279 /* setup interrupt pins */ 280 val = readl(rk_pcie->dbi_base + PCI_INTERRUPT_LINE); 281 val &= 0xffff00ff; 282 val |= 0x00000100; 283 writel(val, rk_pcie->dbi_base + PCI_INTERRUPT_LINE); 284 285 /* setup bus numbers */ 286 val = readl(rk_pcie->dbi_base + PCI_PRIMARY_BUS); 287 val &= 0xff000000; 288 val |= 0x00ff0100; 289 writel(val, rk_pcie->dbi_base + PCI_PRIMARY_BUS); 290 291 val = readl(rk_pcie->dbi_base + PCI_PRIMARY_BUS); 292 293 /* setup command register */ 294 val = readl(rk_pcie->dbi_base + PCI_COMMAND); 295 val &= 0xffff0000; 296 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 297 PCI_COMMAND_MASTER | PCI_COMMAND_SERR; 298 writel(val, rk_pcie->dbi_base + PCI_COMMAND); 299 300 /* program correct class for RC */ 301 writew(PCI_CLASS_BRIDGE_PCI, rk_pcie->dbi_base + PCI_CLASS_DEVICE); 302 /* Better disable write permission right after the update */ 303 304 val = readl(rk_pcie->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); 305 val |= PORT_LOGIC_SPEED_CHANGE; 306 writel(val, rk_pcie->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); 307 308 rk_pcie_dbi_write_enable(rk_pcie, false); 309 } 310 311 static void rk_pcie_configure(struct rk_pcie *pci, u32 cap_speed) 312 { 313 u32 val; 314 315 rk_pcie_dbi_write_enable(pci, true); 316 317 val = readl(pci->dbi_base + PCIE_LINK_CAPABILITY); 318 val &= ~TARGET_LINK_SPEED_MASK; 319 val |= cap_speed; 320 writel(val, pci->dbi_base + PCIE_LINK_CAPABILITY); 321 322 val = readl(pci->dbi_base + PCIE_LINK_CTL_2); 323 val &= ~TARGET_LINK_SPEED_MASK; 324 val |= cap_speed; 325 writel(val, pci->dbi_base + PCIE_LINK_CTL_2); 326 327 rk_pcie_dbi_write_enable(pci, false); 328 } 329 330 static void rk_pcie_prog_outbound_atu_unroll(struct rk_pcie *pci, int index, 331 int type, u64 cpu_addr, 332 u64 pci_addr, u32 size) 333 { 334 u32 retries, val; 335 336 dev_dbg(pci->dev, "ATU programmed with: index: %d, type: %d, cpu addr: %8llx, pci addr: %8llx, size: %8x\n", 337 index, type, cpu_addr, pci_addr, size); 338 339 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE, 340 lower_32_bits(cpu_addr)); 341 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE, 342 upper_32_bits(cpu_addr)); 343 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LIMIT, 344 lower_32_bits(cpu_addr + size - 1)); 345 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET, 346 lower_32_bits(pci_addr)); 347 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET, 348 upper_32_bits(pci_addr)); 349 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, 350 type); 351 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2, 352 PCIE_ATU_ENABLE); 353 354 /* 355 * Make sure ATU enable takes effect before any subsequent config 356 * and I/O accesses. 357 */ 358 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { 359 val = rk_pcie_readl_ob_unroll(pci, index, 360 PCIE_ATU_UNR_REGION_CTRL2); 361 if (val & PCIE_ATU_ENABLE) 362 return; 363 364 udelay(LINK_WAIT_IATU); 365 } 366 dev_err(pci->dev, "outbound iATU is not being enabled\n"); 367 } 368 369 static int rk_pcie_addr_valid(pci_dev_t d, int first_busno) 370 { 371 if ((PCI_BUS(d) == first_busno) && (PCI_DEV(d) > 0)) 372 return 0; 373 if ((PCI_BUS(d) == first_busno + 1) && (PCI_DEV(d) > 0)) 374 return 0; 375 376 return 1; 377 } 378 379 static uintptr_t set_cfg_address(struct rk_pcie *pcie, 380 pci_dev_t d, uint where) 381 { 382 int bus = PCI_BUS(d) - pcie->first_busno; 383 uintptr_t va_address; 384 u32 atu_type; 385 386 /* Use dbi_base for own configuration read and write */ 387 if (!bus) { 388 va_address = (uintptr_t)pcie->dbi_base; 389 goto out; 390 } 391 392 if (bus == 1) 393 /* 394 * For local bus whose primary bus number is root bridge, 395 * change TLP Type field to 4. 396 */ 397 atu_type = PCIE_ATU_TYPE_CFG0; 398 else 399 /* Otherwise, change TLP Type field to 5. */ 400 atu_type = PCIE_ATU_TYPE_CFG1; 401 402 /* 403 * Not accessing root port configuration space? 404 * Region #0 is used for Outbound CFG space access. 405 * Direction = Outbound 406 * Region Index = 0 407 */ 408 d = PCI_MASK_BUS(d); 409 d = PCI_ADD_BUS(bus, d); 410 rk_pcie_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1, 411 atu_type, (u64)pcie->cfg_base, 412 d << 8, pcie->cfg_size); 413 414 va_address = (uintptr_t)pcie->cfg_base; 415 416 out: 417 va_address += where & ~0x3; 418 419 return va_address; 420 } 421 422 static int rockchip_pcie_rd_conf(struct udevice *bus, pci_dev_t bdf, 423 uint offset, ulong *valuep, 424 enum pci_size_t size) 425 { 426 struct rk_pcie *pcie = dev_get_priv(bus); 427 uintptr_t va_address; 428 ulong value; 429 430 debug("PCIE CFG read: bdf=%2x:%2x:%2x\n", 431 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); 432 433 if (!rk_pcie_addr_valid(bdf, pcie->first_busno)) { 434 debug("- out of range\n"); 435 *valuep = pci_get_ff(size); 436 return 0; 437 } 438 439 va_address = set_cfg_address(pcie, bdf, offset); 440 441 value = readl(va_address); 442 443 debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value); 444 *valuep = pci_conv_32_to_size(value, offset, size); 445 446 rk_pcie_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1, 447 PCIE_ATU_TYPE_IO, pcie->io.phys_start, 448 pcie->io.bus_start, pcie->io.size); 449 450 return 0; 451 } 452 453 static int rockchip_pcie_wr_conf(struct udevice *bus, pci_dev_t bdf, 454 uint offset, ulong value, 455 enum pci_size_t size) 456 { 457 struct rk_pcie *pcie = dev_get_priv(bus); 458 uintptr_t va_address; 459 ulong old; 460 461 debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d)\n", 462 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); 463 debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value); 464 465 if (!rk_pcie_addr_valid(bdf, pcie->first_busno)) { 466 debug("- out of range\n"); 467 return 0; 468 } 469 470 va_address = set_cfg_address(pcie, bdf, offset); 471 472 old = readl(va_address); 473 value = pci_conv_size_to_32(old, value, offset, size); 474 writel(value, va_address); 475 476 rk_pcie_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1, 477 PCIE_ATU_TYPE_IO, pcie->io.phys_start, 478 pcie->io.bus_start, pcie->io.size); 479 480 return 0; 481 } 482 483 static void rk_pcie_enable_debug(struct rk_pcie *rk_pcie) 484 { 485 #if RK_PCIE_DBG 486 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0, 487 PCIE_CLIENT_DBG_TRANSITION_DATA); 488 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1, 489 PCIE_CLIENT_DBG_TRANSITION_DATA); 490 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0, 491 PCIE_CLIENT_DBG_TRANSITION_DATA); 492 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1, 493 PCIE_CLIENT_DBG_TRANSITION_DATA); 494 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_MODE_CON, 495 PCIE_CLIENT_DBF_EN); 496 #endif 497 } 498 499 static void rk_pcie_debug_dump(struct rk_pcie *rk_pcie) 500 { 501 #if RK_PCIE_DBG 502 u32 loop; 503 504 dev_err(rk_pcie->dev, "ltssm = 0x%x\n", 505 rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_LTSSM_STATUS)); 506 for (loop = 0; loop < 64; loop++) 507 dev_err(rk_pcie->dev, "fifo_status = 0x%x\n", 508 rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_STATUS)); 509 #endif 510 } 511 512 static inline void rk_pcie_link_status_clear(struct rk_pcie *rk_pcie) 513 { 514 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_GENERAL_DEBUG, 0x0); 515 } 516 517 static inline void rk_pcie_disable_ltssm(struct rk_pcie *rk_pcie) 518 { 519 rk_pcie_writel_apb(rk_pcie, 0x0, 0xc0008); 520 } 521 522 static inline void rk_pcie_enable_ltssm(struct rk_pcie *rk_pcie) 523 { 524 rk_pcie_writel_apb(rk_pcie, 0x0, 0xc000c); 525 } 526 527 static int is_link_up(struct rk_pcie *priv) 528 { 529 u32 val; 530 531 val = rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS); 532 if ((val & (RDLH_LINKUP | SMLH_LINKUP)) == 0x30000 && 533 (val & GENMASK(5, 0)) == 0x11) 534 return 1; 535 536 return 0; 537 } 538 539 static int rk_pcie_link_up(struct rk_pcie *priv, u32 cap_speed) 540 { 541 int retries; 542 543 if (is_link_up(priv)) { 544 printf("PCI Link already up before configuration!\n"); 545 return 1; 546 } 547 548 /* DW pre link configurations */ 549 rk_pcie_configure(priv, cap_speed); 550 551 /* Release the device */ 552 if (dm_gpio_is_valid(&priv->rst_gpio)) { 553 /* 554 * T_PVPERL (Power stable to PERST# inactive) should be a minimum of 100ms. 555 * We add a 200ms by default for sake of hoping everthings 556 * work fine. 557 */ 558 msleep(200); 559 dm_gpio_set_value(&priv->rst_gpio, 1); 560 /* 561 * Add this 20ms delay because we observe link is always up stably after it and 562 * could help us save 20ms for scanning devices. 563 */ 564 msleep(20); 565 } 566 567 rk_pcie_disable_ltssm(priv); 568 rk_pcie_link_status_clear(priv); 569 rk_pcie_enable_debug(priv); 570 571 /* Enable LTSSM */ 572 rk_pcie_enable_ltssm(priv); 573 574 for (retries = 0; retries < 50; retries++) { 575 if (is_link_up(priv)) { 576 dev_info(priv->dev, "PCIe Link up, LTSSM is 0x%x\n", 577 rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS)); 578 rk_pcie_debug_dump(priv); 579 /* Link maybe in Gen switch recovery but we need to wait more 1s */ 580 msleep(1000); 581 return 0; 582 } 583 584 dev_info(priv->dev, "PCIe Linking... LTSSM is 0x%x\n", 585 rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS)); 586 rk_pcie_debug_dump(priv); 587 msleep(10); 588 } 589 590 dev_err(priv->dev, "PCIe-%d Link Fail\n", priv->dev->seq); 591 return -EINVAL; 592 } 593 594 static int rockchip_pcie_init_port(struct udevice *dev) 595 { 596 int ret; 597 u32 val; 598 struct rk_pcie *priv = dev_get_priv(dev); 599 union phy_configure_opts phy_cfg; 600 601 /* Rest the device */ 602 if (dm_gpio_is_valid(&priv->rst_gpio)) 603 dm_gpio_set_value(&priv->rst_gpio, 0); 604 605 /* Set power and maybe external ref clk input */ 606 if (priv->vpcie3v3) { 607 ret = regulator_set_enable(priv->vpcie3v3, true); 608 if (ret) { 609 dev_err(priv->dev, "failed to enable vpcie3v3 (ret=%d)\n", 610 ret); 611 return ret; 612 } 613 } 614 615 if (priv->is_bifurcation) { 616 phy_cfg.pcie.is_bifurcation = true; 617 ret = generic_phy_configure(&priv->phy, &phy_cfg); 618 if (ret) 619 dev_err(dev, "failed to set bifurcation for phy (ret=%d)\n", ret); 620 } 621 622 ret = generic_phy_init(&priv->phy); 623 if (ret) { 624 dev_err(dev, "failed to init phy (ret=%d)\n", ret); 625 return ret; 626 } 627 628 ret = generic_phy_power_on(&priv->phy); 629 if (ret) { 630 dev_err(dev, "failed to power on phy (ret=%d)\n", ret); 631 goto err_exit_phy; 632 } 633 634 ret = reset_deassert_bulk(&priv->rsts); 635 if (ret) { 636 dev_err(dev, "failed to deassert resets (ret=%d)\n", ret); 637 goto err_power_off_phy; 638 } 639 640 ret = clk_enable_bulk(&priv->clks); 641 if (ret) { 642 dev_err(dev, "failed to enable clks (ret=%d)\n", ret); 643 goto err_deassert_bulk; 644 } 645 646 /* LTSSM EN ctrl mode */ 647 val = rk_pcie_readl_apb(priv, PCIE_CLIENT_HOT_RESET_CTRL); 648 val |= PCIE_LTSSM_ENABLE_ENHANCE | (PCIE_LTSSM_ENABLE_ENHANCE << 16); 649 rk_pcie_writel_apb(priv, PCIE_CLIENT_HOT_RESET_CTRL, val); 650 651 /* Set RC mode */ 652 rk_pcie_writel_apb(priv, 0x0, 0xf00040); 653 rk_pcie_setup_host(priv); 654 655 ret = rk_pcie_link_up(priv, priv->gen); 656 if (ret < 0) 657 goto err_link_up; 658 659 return 0; 660 err_link_up: 661 clk_disable_bulk(&priv->clks); 662 err_deassert_bulk: 663 reset_assert_bulk(&priv->rsts); 664 err_power_off_phy: 665 generic_phy_power_off(&priv->phy); 666 err_exit_phy: 667 generic_phy_exit(&priv->phy); 668 return ret; 669 } 670 671 static int rockchip_pcie_parse_dt(struct udevice *dev) 672 { 673 struct rk_pcie *priv = dev_get_priv(dev); 674 u32 max_link_speed; 675 int ret; 676 struct resource res; 677 678 ret = dev_read_resource_byname(dev, "pcie-dbi", &res); 679 if (ret) 680 return -ENODEV; 681 priv->dbi_base = (void *)(res.start); 682 dev_dbg(dev, "DBI address is 0x%p\n", priv->dbi_base); 683 684 ret = dev_read_resource_byname(dev, "pcie-apb", &res); 685 if (ret) 686 return -ENODEV; 687 priv->apb_base = (void *)(res.start); 688 dev_dbg(dev, "APB address is 0x%p\n", priv->apb_base); 689 690 ret = gpio_request_by_name(dev, "reset-gpios", 0, 691 &priv->rst_gpio, GPIOD_IS_OUT); 692 if (ret) { 693 dev_err(dev, "failed to find reset-gpios property\n"); 694 return ret; 695 } 696 697 ret = reset_get_bulk(dev, &priv->rsts); 698 if (ret) { 699 dev_err(dev, "Can't get reset: %d\n", ret); 700 return ret; 701 } 702 703 ret = clk_get_bulk(dev, &priv->clks); 704 if (ret) { 705 dev_err(dev, "Can't get clock: %d\n", ret); 706 return ret; 707 } 708 709 ret = device_get_supply_regulator(dev, "vpcie3v3-supply", 710 &priv->vpcie3v3); 711 if (ret && ret != -ENOENT) { 712 dev_err(dev, "failed to get vpcie3v3 supply (ret=%d)\n", ret); 713 return ret; 714 } 715 716 ret = generic_phy_get_by_index(dev, 0, &priv->phy); 717 if (ret) { 718 dev_err(dev, "failed to get pcie phy (ret=%d)\n", ret); 719 return ret; 720 } 721 722 if (dev_read_bool(dev, "rockchip,bifurcation")) 723 priv->is_bifurcation = true; 724 725 ret = ofnode_read_u32(dev->node, "max-link-speed", &max_link_speed); 726 if (ret < 0 || max_link_speed > 4) 727 priv->gen = 0; 728 else 729 priv->gen = max_link_speed; 730 731 return 0; 732 } 733 734 static int rockchip_pcie_probe(struct udevice *dev) 735 { 736 struct rk_pcie *priv = dev_get_priv(dev); 737 struct udevice *ctlr = pci_get_controller(dev); 738 struct pci_controller *hose = dev_get_uclass_priv(ctlr); 739 int ret; 740 741 priv->first_busno = dev->seq; 742 priv->dev = dev; 743 744 ret = rockchip_pcie_parse_dt(dev); 745 if (ret) 746 return ret; 747 748 ret = rockchip_pcie_init_port(dev); 749 if (ret) 750 return ret; 751 752 dev_info(dev, "PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", 753 dev->seq, rk_pcie_get_link_speed(priv), 754 rk_pcie_get_link_width(priv), 755 hose->first_busno); 756 757 for (ret = 0; ret < hose->region_count; ret++) { 758 if (hose->regions[ret].flags == PCI_REGION_IO) { 759 priv->io.phys_start = hose->regions[ret].phys_start; /* IO base */ 760 priv->io.bus_start = hose->regions[ret].bus_start; /* IO_bus_addr */ 761 priv->io.size = hose->regions[ret].size; /* IO size */ 762 } else if (hose->regions[ret].flags == PCI_REGION_MEM) { 763 priv->mem.phys_start = hose->regions[ret].phys_start; /* MEM base */ 764 priv->mem.bus_start = hose->regions[ret].bus_start; /* MEM_bus_addr */ 765 priv->mem.size = hose->regions[ret].size; /* MEM size */ 766 } else if (hose->regions[ret].flags == PCI_REGION_SYS_MEMORY) { 767 priv->cfg_base = (void *)(priv->io.phys_start - priv->io.size); 768 priv->cfg_size = priv->io.size; 769 } else { 770 dev_err(dev, "invalid flags type!\n"); 771 } 772 } 773 774 dev_dbg(dev, "Config space: [0x%p - 0x%p, size 0x%llx]\n", 775 priv->cfg_base, priv->cfg_base + priv->cfg_size, 776 priv->cfg_size); 777 778 dev_dbg(dev, "IO space: [0x%llx - 0x%llx, size 0x%x]\n", 779 priv->io.phys_start, priv->io.phys_start + priv->io.size, 780 priv->io.size); 781 782 dev_dbg(dev, "IO bus: [0x%x - 0x%x, size 0x%x]\n", 783 priv->io.bus_start, priv->io.bus_start + priv->io.size, 784 priv->io.size); 785 786 dev_dbg(dev, "MEM space: [0x%llx - 0x%llx, size 0x%x]\n", 787 priv->mem.phys_start, priv->mem.phys_start + priv->mem.size, 788 priv->mem.size); 789 790 dev_dbg(dev, "MEM bus: [0x%x - 0x%x, size 0x%x]\n", 791 priv->mem.bus_start, priv->mem.bus_start + priv->mem.size, 792 priv->mem.size); 793 794 rk_pcie_prog_outbound_atu_unroll(priv, PCIE_ATU_REGION_INDEX0, 795 PCIE_ATU_TYPE_MEM, 796 priv->mem.phys_start, 797 priv->mem.bus_start, priv->mem.size); 798 return 0; 799 } 800 801 static const struct dm_pci_ops rockchip_pcie_ops = { 802 .read_config = rockchip_pcie_rd_conf, 803 .write_config = rockchip_pcie_wr_conf, 804 }; 805 806 static const struct udevice_id rockchip_pcie_ids[] = { 807 { .compatible = "rockchip,rk3528-pcie" }, 808 { .compatible = "rockchip,rk3562-pcie" }, 809 { .compatible = "rockchip,rk3568-pcie" }, 810 { .compatible = "rockchip,rk3588-pcie" }, 811 { } 812 }; 813 814 U_BOOT_DRIVER(rockchip_pcie) = { 815 .name = "pcie_dw_rockchip", 816 .id = UCLASS_PCI, 817 .of_match = rockchip_pcie_ids, 818 .ops = &rockchip_pcie_ops, 819 .probe = rockchip_pcie_probe, 820 .priv_auto_alloc_size = sizeof(struct rk_pcie), 821 }; 822