1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Rockchip DesignWare based PCIe host controller driver 4 * 5 * Copyright (c) 2021 Rockchip, Inc. 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <dm.h> 11 #include <generic-phy.h> 12 #include <pci.h> 13 #include <power-domain.h> 14 #include <power/regulator.h> 15 #include <reset.h> 16 #include <syscon.h> 17 #include <asm/io.h> 18 #include <asm-generic/gpio.h> 19 #include <asm/arch-rockchip/clock.h> 20 #include <linux/bitfield.h> 21 #include <linux/iopoll.h> 22 #include <linux/ioport.h> 23 #include <linux/log2.h> 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 #define RK_PCIE_DBG 0 28 29 #define __pcie_dev_print_emit(fmt, ...) \ 30 ({ \ 31 printf(fmt, ##__VA_ARGS__); \ 32 }) 33 34 #ifdef dev_err 35 #undef dev_err 36 #define dev_err(dev, fmt, ...) \ 37 ({ \ 38 if (dev) \ 39 __pcie_dev_print_emit("%s: " fmt, dev->name, \ 40 ##__VA_ARGS__); \ 41 }) 42 #endif 43 44 #ifdef dev_info 45 #undef dev_info 46 #define dev_info dev_err 47 #endif 48 49 #ifdef DEBUG 50 #define dev_dbg dev_err 51 #else 52 #define dev_dbg(dev, fmt, ...) \ 53 ({ \ 54 if (0) \ 55 __dev_printk(7, dev, fmt, ##__VA_ARGS__); \ 56 }) 57 #endif 58 59 struct rk_pcie { 60 struct udevice *dev; 61 struct udevice *vpcie3v3; 62 void *dbi_base; 63 void *apb_base; 64 void *cfg_base; 65 fdt_size_t cfg_size; 66 struct phy phy; 67 struct clk_bulk clks; 68 int first_busno; 69 struct reset_ctl_bulk rsts; 70 struct gpio_desc rst_gpio; 71 struct pci_region io; 72 struct pci_region mem; 73 struct pci_region mem64; 74 bool is_bifurcation; 75 u32 gen; 76 u32 lanes; 77 }; 78 79 enum { 80 PCIBIOS_SUCCESSFUL = 0x0000, 81 PCIBIOS_UNSUPPORTED = -ENODEV, 82 PCIBIOS_NODEV = -ENODEV, 83 }; 84 85 #define msleep(a) udelay((a) * 1000) 86 #define MAX_LINKUP_RETRIES 2 87 88 /* Parameters for the waiting for iATU enabled routine */ 89 #define PCIE_CLIENT_GENERAL_DEBUG 0x104 90 #define PCIE_CLIENT_HOT_RESET_CTRL 0x180 91 #define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) 92 #define PCIE_CLIENT_LTSSM_STATUS 0x300 93 #define SMLH_LINKUP BIT(16) 94 #define RDLH_LINKUP BIT(17) 95 #define PCIE_CLIENT_DBG_FIFO_MODE_CON 0x310 96 #define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0 0x320 97 #define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1 0x324 98 #define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0 0x328 99 #define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1 0x32c 100 #define PCIE_CLIENT_DBG_FIFO_STATUS 0x350 101 #define PCIE_CLIENT_DBG_TRANSITION_DATA 0xffff0000 102 #define PCIE_CLIENT_DBF_EN 0xffff0003 103 104 /* PCI DBICS registers */ 105 #define PCIE_LINK_STATUS_REG 0x80 106 #define PCIE_LINK_STATUS_SPEED_OFF 16 107 #define PCIE_LINK_STATUS_SPEED_MASK (0xf << PCIE_LINK_STATUS_SPEED_OFF) 108 #define PCIE_LINK_STATUS_WIDTH_OFF 20 109 #define PCIE_LINK_STATUS_WIDTH_MASK (0xf << PCIE_LINK_STATUS_WIDTH_OFF) 110 111 #define PCIE_LINK_CAPABILITY 0x7c 112 #define PCIE_LINK_CTL_2 0xa0 113 #define TARGET_LINK_SPEED_MASK 0xf 114 #define LINK_SPEED_GEN_1 0x1 115 #define LINK_SPEED_GEN_2 0x2 116 #define LINK_SPEED_GEN_3 0x3 117 118 #define PCIE_PORT_LINK_CONTROL 0x710 119 #define PORT_LINK_FAST_LINK_MODE BIT(7) 120 #define PCIE_MISC_CONTROL_1_OFF 0x8bc 121 #define PCIE_DBI_RO_WR_EN BIT(0) 122 123 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80c 124 #define PORT_LOGIC_SPEED_CHANGE BIT(17) 125 #define PORT_LINK_MODE_MASK GENMASK(21, 16) 126 #define PORT_LINK_MODE(n) FIELD_PREP(PORT_LINK_MODE_MASK, n) 127 #define PORT_LINK_MODE_1_LANES PORT_LINK_MODE(0x1) 128 #define PORT_LINK_MODE_2_LANES PORT_LINK_MODE(0x3) 129 #define PORT_LINK_MODE_4_LANES PORT_LINK_MODE(0x7) 130 #define PORT_LINK_MODE_8_LANES PORT_LINK_MODE(0xf) 131 #define PORT_LOGIC_LINK_WIDTH_MASK GENMASK(12, 8) 132 #define PORT_LOGIC_LINK_WIDTH(n) FIELD_PREP(PORT_LOGIC_LINK_WIDTH_MASK, n) 133 #define PORT_LOGIC_LINK_WIDTH_1_LANES PORT_LOGIC_LINK_WIDTH(0x1) 134 #define PORT_LOGIC_LINK_WIDTH_2_LANES PORT_LOGIC_LINK_WIDTH(0x2) 135 #define PORT_LOGIC_LINK_WIDTH_4_LANES PORT_LOGIC_LINK_WIDTH(0x4) 136 #define PORT_LOGIC_LINK_WIDTH_8_LANES PORT_LOGIC_LINK_WIDTH(0x8) 137 138 139 /* 140 * iATU Unroll-specific register definitions 141 * From 4.80 core version the address translation will be made by unroll. 142 * The registers are offset from atu_base 143 */ 144 #define PCIE_ATU_UNR_REGION_CTRL1 0x00 145 #define PCIE_ATU_UNR_REGION_CTRL2 0x04 146 #define PCIE_ATU_UNR_LOWER_BASE 0x08 147 #define PCIE_ATU_UNR_UPPER_BASE 0x0c 148 #define PCIE_ATU_UNR_LIMIT 0x10 149 #define PCIE_ATU_UNR_LOWER_TARGET 0x14 150 #define PCIE_ATU_UNR_UPPER_TARGET 0x18 151 152 #define PCIE_ATU_REGION_INDEX2 (0x2 << 0) 153 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0) 154 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0) 155 #define PCIE_ATU_TYPE_MEM (0x0 << 0) 156 #define PCIE_ATU_TYPE_IO (0x2 << 0) 157 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0) 158 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0) 159 #define PCIE_ATU_ENABLE (0x1 << 31) 160 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) 161 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) 162 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) 163 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) 164 165 /* Register address builder */ 166 #define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) \ 167 ((0x3 << 20) | ((region) << 9)) 168 #define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region) \ 169 ((0x3 << 20) | ((region) << 9) | (0x1 << 8)) 170 171 /* Parameters for the waiting for iATU enabled routine */ 172 #define LINK_WAIT_MAX_IATU_RETRIES 5 173 #define LINK_WAIT_IATU 10000 174 175 #define PCIE_TYPE0_HDR_DBI2_OFFSET 0x100000 176 177 static int rk_pcie_read(void __iomem *addr, int size, u32 *val) 178 { 179 if ((uintptr_t)addr & (size - 1)) { 180 *val = 0; 181 return PCIBIOS_UNSUPPORTED; 182 } 183 184 if (size == 4) { 185 *val = readl(addr); 186 } else if (size == 2) { 187 *val = readw(addr); 188 } else if (size == 1) { 189 *val = readb(addr); 190 } else { 191 *val = 0; 192 return PCIBIOS_NODEV; 193 } 194 195 return PCIBIOS_SUCCESSFUL; 196 } 197 198 static int rk_pcie_write(void __iomem *addr, int size, u32 val) 199 { 200 if ((uintptr_t)addr & (size - 1)) 201 return PCIBIOS_UNSUPPORTED; 202 203 if (size == 4) 204 writel(val, addr); 205 else if (size == 2) 206 writew(val, addr); 207 else if (size == 1) 208 writeb(val, addr); 209 else 210 return PCIBIOS_NODEV; 211 212 return PCIBIOS_SUCCESSFUL; 213 } 214 215 static u32 __rk_pcie_read_apb(struct rk_pcie *rk_pcie, void __iomem *base, 216 u32 reg, size_t size) 217 { 218 int ret; 219 u32 val; 220 221 ret = rk_pcie_read(base + reg, size, &val); 222 if (ret) 223 dev_err(rk_pcie->dev, "Read APB address failed\n"); 224 225 return val; 226 } 227 228 static void __rk_pcie_write_apb(struct rk_pcie *rk_pcie, void __iomem *base, 229 u32 reg, size_t size, u32 val) 230 { 231 int ret; 232 233 ret = rk_pcie_write(base + reg, size, val); 234 if (ret) 235 dev_err(rk_pcie->dev, "Write APB address failed\n"); 236 } 237 238 static inline u32 rk_pcie_readl_apb(struct rk_pcie *rk_pcie, u32 reg) 239 { 240 return __rk_pcie_read_apb(rk_pcie, rk_pcie->apb_base, reg, 0x4); 241 } 242 243 static inline void rk_pcie_writel_apb(struct rk_pcie *rk_pcie, u32 reg, 244 u32 val) 245 { 246 __rk_pcie_write_apb(rk_pcie, rk_pcie->apb_base, reg, 0x4, val); 247 } 248 249 static int rk_pcie_get_link_speed(struct rk_pcie *rk_pcie) 250 { 251 return (readl(rk_pcie->dbi_base + PCIE_LINK_STATUS_REG) & 252 PCIE_LINK_STATUS_SPEED_MASK) >> PCIE_LINK_STATUS_SPEED_OFF; 253 } 254 255 static int rk_pcie_get_link_width(struct rk_pcie *rk_pcie) 256 { 257 return (readl(rk_pcie->dbi_base + PCIE_LINK_STATUS_REG) & 258 PCIE_LINK_STATUS_WIDTH_MASK) >> PCIE_LINK_STATUS_WIDTH_OFF; 259 } 260 261 static void rk_pcie_writel_ob_unroll(struct rk_pcie *rk_pcie, u32 index, 262 u32 reg, u32 val) 263 { 264 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); 265 void __iomem *base = rk_pcie->dbi_base; 266 267 writel(val, base + offset + reg); 268 } 269 270 static u32 rk_pcie_readl_ob_unroll(struct rk_pcie *rk_pcie, u32 index, u32 reg) 271 { 272 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); 273 void __iomem *base = rk_pcie->dbi_base; 274 275 return readl(base + offset + reg); 276 } 277 278 static inline void rk_pcie_dbi_write_enable(struct rk_pcie *rk_pcie, bool en) 279 { 280 u32 val; 281 282 val = readl(rk_pcie->dbi_base + PCIE_MISC_CONTROL_1_OFF); 283 284 if (en) 285 val |= PCIE_DBI_RO_WR_EN; 286 else 287 val &= ~PCIE_DBI_RO_WR_EN; 288 writel(val, rk_pcie->dbi_base + PCIE_MISC_CONTROL_1_OFF); 289 } 290 291 static void rk_pcie_setup_host(struct rk_pcie *rk_pcie) 292 { 293 u32 val; 294 295 rk_pcie_dbi_write_enable(rk_pcie, true); 296 297 /* setup RC BARs */ 298 writel(PCI_BASE_ADDRESS_MEM_TYPE_64, 299 rk_pcie->dbi_base + PCI_BASE_ADDRESS_0); 300 writel(0x0, rk_pcie->dbi_base + PCI_BASE_ADDRESS_1); 301 302 /* setup interrupt pins */ 303 val = readl(rk_pcie->dbi_base + PCI_INTERRUPT_LINE); 304 val &= 0xffff00ff; 305 val |= 0x00000100; 306 writel(val, rk_pcie->dbi_base + PCI_INTERRUPT_LINE); 307 308 /* setup bus numbers */ 309 val = readl(rk_pcie->dbi_base + PCI_PRIMARY_BUS); 310 val &= 0xff000000; 311 val |= 0x00ff0100; 312 writel(val, rk_pcie->dbi_base + PCI_PRIMARY_BUS); 313 314 val = readl(rk_pcie->dbi_base + PCI_PRIMARY_BUS); 315 316 /* setup command register */ 317 val = readl(rk_pcie->dbi_base + PCI_COMMAND); 318 val &= 0xffff0000; 319 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 320 PCI_COMMAND_MASTER | PCI_COMMAND_SERR; 321 writel(val, rk_pcie->dbi_base + PCI_COMMAND); 322 323 /* program correct class for RC */ 324 writew(PCI_CLASS_BRIDGE_PCI, rk_pcie->dbi_base + PCI_CLASS_DEVICE); 325 /* Better disable write permission right after the update */ 326 327 val = readl(rk_pcie->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); 328 val |= PORT_LOGIC_SPEED_CHANGE; 329 writel(val, rk_pcie->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); 330 331 /* Disable BAR0 BAR1 */ 332 writel(0, rk_pcie->dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + 0 * 4); 333 writel(0, rk_pcie->dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + 1 * 4); 334 335 rk_pcie_dbi_write_enable(rk_pcie, false); 336 } 337 338 static void rk_pcie_configure(struct rk_pcie *pci, u32 cap_speed, u32 cap_lanes) 339 { 340 u32 val; 341 342 rk_pcie_dbi_write_enable(pci, true); 343 344 val = readl(pci->dbi_base + PCIE_LINK_CAPABILITY); 345 val &= ~TARGET_LINK_SPEED_MASK; 346 val |= cap_speed; 347 writel(val, pci->dbi_base + PCIE_LINK_CAPABILITY); 348 349 val = readl(pci->dbi_base + PCIE_LINK_CTL_2); 350 val &= ~TARGET_LINK_SPEED_MASK; 351 val |= cap_speed; 352 writel(val, pci->dbi_base + PCIE_LINK_CTL_2); 353 354 val = readl(pci->dbi_base + PCIE_PORT_LINK_CONTROL); 355 356 /* Set the number of lanes */ 357 val &= ~PORT_LINK_FAST_LINK_MODE; 358 val &= ~PORT_LINK_MODE_MASK; 359 switch (cap_lanes) { 360 case 1: 361 val |= PORT_LINK_MODE_1_LANES; 362 break; 363 case 2: 364 val |= PORT_LINK_MODE_2_LANES; 365 break; 366 case 4: 367 val |= PORT_LINK_MODE_4_LANES; 368 break; 369 case 8: 370 val |= PORT_LINK_MODE_8_LANES; 371 break; 372 default: 373 dev_err(pci->dev, "cap_lanes %u: invalid value\n", cap_lanes); 374 return; 375 } 376 writel(val, pci->dbi_base + PCIE_PORT_LINK_CONTROL); 377 378 /* Set link width speed control register */ 379 val = readl(pci->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); 380 val &= ~PORT_LOGIC_LINK_WIDTH_MASK; 381 switch (cap_lanes) { 382 case 1: 383 val |= PORT_LOGIC_LINK_WIDTH_1_LANES; 384 break; 385 case 2: 386 val |= PORT_LOGIC_LINK_WIDTH_2_LANES; 387 break; 388 case 4: 389 val |= PORT_LOGIC_LINK_WIDTH_4_LANES; 390 break; 391 case 8: 392 val |= PORT_LOGIC_LINK_WIDTH_8_LANES; 393 break; 394 } 395 writel(val, pci->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); 396 397 rk_pcie_dbi_write_enable(pci, false); 398 } 399 400 static void rk_pcie_prog_outbound_atu_unroll(struct rk_pcie *pci, int index, 401 int type, u64 cpu_addr, 402 u64 pci_addr, u32 size) 403 { 404 u32 retries, val; 405 406 dev_dbg(pci->dev, "ATU programmed with: index: %d, type: %d, cpu addr: %8llx, pci addr: %8llx, size: %8x\n", 407 index, type, cpu_addr, pci_addr, size); 408 409 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE, 410 lower_32_bits(cpu_addr)); 411 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE, 412 upper_32_bits(cpu_addr)); 413 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LIMIT, 414 lower_32_bits(cpu_addr + size - 1)); 415 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET, 416 lower_32_bits(pci_addr)); 417 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET, 418 upper_32_bits(pci_addr)); 419 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, 420 type); 421 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2, 422 PCIE_ATU_ENABLE); 423 424 /* 425 * Make sure ATU enable takes effect before any subsequent config 426 * and I/O accesses. 427 */ 428 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { 429 val = rk_pcie_readl_ob_unroll(pci, index, 430 PCIE_ATU_UNR_REGION_CTRL2); 431 if (val & PCIE_ATU_ENABLE) 432 return; 433 434 udelay(LINK_WAIT_IATU); 435 } 436 dev_err(pci->dev, "outbound iATU is not being enabled\n"); 437 } 438 439 static int rk_pcie_addr_valid(pci_dev_t d, int first_busno) 440 { 441 if ((PCI_BUS(d) == first_busno) && (PCI_DEV(d) > 0)) 442 return 0; 443 if ((PCI_BUS(d) == first_busno + 1) && (PCI_DEV(d) > 0)) 444 return 0; 445 446 return 1; 447 } 448 449 static uintptr_t set_cfg_address(struct rk_pcie *pcie, 450 pci_dev_t d, uint where) 451 { 452 int bus = PCI_BUS(d) - pcie->first_busno; 453 uintptr_t va_address; 454 u32 atu_type; 455 456 /* Use dbi_base for own configuration read and write */ 457 if (!bus) { 458 va_address = (uintptr_t)pcie->dbi_base; 459 goto out; 460 } 461 462 if (bus == 1) 463 /* 464 * For local bus whose primary bus number is root bridge, 465 * change TLP Type field to 4. 466 */ 467 atu_type = PCIE_ATU_TYPE_CFG0; 468 else 469 /* Otherwise, change TLP Type field to 5. */ 470 atu_type = PCIE_ATU_TYPE_CFG1; 471 472 /* 473 * Not accessing root port configuration space? 474 * Region #0 is used for Outbound CFG space access. 475 * Direction = Outbound 476 * Region Index = 0 477 */ 478 d = PCI_MASK_BUS(d); 479 d = PCI_ADD_BUS(bus, d); 480 rk_pcie_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1, 481 atu_type, (u64)pcie->cfg_base, 482 d << 8, pcie->cfg_size); 483 484 va_address = (uintptr_t)pcie->cfg_base; 485 486 out: 487 va_address += where & ~0x3; 488 489 return va_address; 490 } 491 492 static int rockchip_pcie_rd_conf(struct udevice *bus, pci_dev_t bdf, 493 uint offset, ulong *valuep, 494 enum pci_size_t size) 495 { 496 struct rk_pcie *pcie = dev_get_priv(bus); 497 uintptr_t va_address; 498 ulong value; 499 500 debug("PCIE CFG read: bdf=%2x:%2x:%2x\n", 501 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); 502 503 if (!rk_pcie_addr_valid(bdf, pcie->first_busno)) { 504 debug("- out of range\n"); 505 *valuep = pci_get_ff(size); 506 return 0; 507 } 508 509 va_address = set_cfg_address(pcie, bdf, offset); 510 511 value = readl(va_address); 512 513 debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value); 514 *valuep = pci_conv_32_to_size(value, offset, size); 515 516 rk_pcie_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1, 517 PCIE_ATU_TYPE_IO, pcie->io.phys_start, 518 pcie->io.bus_start, pcie->io.size); 519 520 return 0; 521 } 522 523 static int rockchip_pcie_wr_conf(struct udevice *bus, pci_dev_t bdf, 524 uint offset, ulong value, 525 enum pci_size_t size) 526 { 527 struct rk_pcie *pcie = dev_get_priv(bus); 528 uintptr_t va_address; 529 ulong old; 530 531 debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d)\n", 532 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); 533 debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value); 534 if (!rk_pcie_addr_valid(bdf, pcie->first_busno)) { 535 debug("- out of range\n"); 536 return 0; 537 } 538 539 va_address = set_cfg_address(pcie, bdf, offset); 540 541 old = readl(va_address); 542 value = pci_conv_size_to_32(old, value, offset, size); 543 writel(value, va_address); 544 545 rk_pcie_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1, 546 PCIE_ATU_TYPE_IO, pcie->io.phys_start, 547 pcie->io.bus_start, pcie->io.size); 548 549 return 0; 550 } 551 552 static void rk_pcie_enable_debug(struct rk_pcie *rk_pcie) 553 { 554 #if RK_PCIE_DBG 555 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0, 556 PCIE_CLIENT_DBG_TRANSITION_DATA); 557 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1, 558 PCIE_CLIENT_DBG_TRANSITION_DATA); 559 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0, 560 PCIE_CLIENT_DBG_TRANSITION_DATA); 561 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1, 562 PCIE_CLIENT_DBG_TRANSITION_DATA); 563 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_MODE_CON, 564 PCIE_CLIENT_DBF_EN); 565 #endif 566 } 567 568 static void rk_pcie_debug_dump(struct rk_pcie *rk_pcie) 569 { 570 #if RK_PCIE_DBG 571 u32 loop; 572 573 dev_err(rk_pcie->dev, "ltssm = 0x%x\n", 574 rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_LTSSM_STATUS)); 575 for (loop = 0; loop < 64; loop++) 576 dev_err(rk_pcie->dev, "fifo_status = 0x%x\n", 577 rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_STATUS)); 578 #endif 579 } 580 581 static inline void rk_pcie_link_status_clear(struct rk_pcie *rk_pcie) 582 { 583 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_GENERAL_DEBUG, 0x0); 584 } 585 586 static inline void rk_pcie_disable_ltssm(struct rk_pcie *rk_pcie) 587 { 588 rk_pcie_writel_apb(rk_pcie, 0x0, 0xc0008); 589 } 590 591 static inline void rk_pcie_enable_ltssm(struct rk_pcie *rk_pcie) 592 { 593 rk_pcie_writel_apb(rk_pcie, 0x0, 0xc000c); 594 } 595 596 static int is_link_up(struct rk_pcie *priv) 597 { 598 u32 val; 599 600 val = rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS); 601 if ((val & (RDLH_LINKUP | SMLH_LINKUP)) == 0x30000 && 602 (val & GENMASK(5, 0)) == 0x11) 603 return 1; 604 605 return 0; 606 } 607 608 static int rk_pcie_link_up(struct rk_pcie *priv, u32 cap_speed, u32 cap_lanes) 609 { 610 int retries; 611 612 if (is_link_up(priv)) { 613 printf("PCI Link already up before configuration!\n"); 614 return 1; 615 } 616 617 /* DW pre link configurations */ 618 rk_pcie_configure(priv, cap_speed, cap_lanes); 619 620 /* Release the device */ 621 if (dm_gpio_is_valid(&priv->rst_gpio)) { 622 /* 623 * T_PVPERL (Power stable to PERST# inactive) should be a minimum of 100ms. 624 * We add a 200ms by default for sake of hoping everthings 625 * work fine. 626 */ 627 msleep(200); 628 dm_gpio_set_value(&priv->rst_gpio, 1); 629 /* 630 * Add this 20ms delay because we observe link is always up stably after it and 631 * could help us save 20ms for scanning devices. 632 */ 633 msleep(20); 634 } 635 636 rk_pcie_disable_ltssm(priv); 637 rk_pcie_link_status_clear(priv); 638 rk_pcie_enable_debug(priv); 639 640 /* Enable LTSSM */ 641 rk_pcie_enable_ltssm(priv); 642 643 for (retries = 0; retries < 50; retries++) { 644 if (is_link_up(priv)) { 645 dev_info(priv->dev, "PCIe Link up, LTSSM is 0x%x\n", 646 rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS)); 647 rk_pcie_debug_dump(priv); 648 /* Link maybe in Gen switch recovery but we need to wait more 1s */ 649 msleep(1000); 650 return 0; 651 } 652 653 dev_info(priv->dev, "PCIe Linking... LTSSM is 0x%x\n", 654 rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS)); 655 rk_pcie_debug_dump(priv); 656 msleep(10); 657 } 658 659 dev_err(priv->dev, "PCIe-%d Link Fail\n", priv->dev->seq); 660 rk_pcie_disable_ltssm(priv); 661 if (dm_gpio_is_valid(&priv->rst_gpio)) 662 dm_gpio_set_value(&priv->rst_gpio, 0); 663 664 return -EINVAL; 665 } 666 667 static int rockchip_pcie_init_port(struct udevice *dev) 668 { 669 int ret, retries; 670 u32 val; 671 struct rk_pcie *priv = dev_get_priv(dev); 672 union phy_configure_opts phy_cfg; 673 674 /* Rest the device */ 675 if (dm_gpio_is_valid(&priv->rst_gpio)) 676 dm_gpio_set_value(&priv->rst_gpio, 0); 677 678 /* Set power and maybe external ref clk input */ 679 if (priv->vpcie3v3) { 680 ret = regulator_set_enable(priv->vpcie3v3, true); 681 if (ret) { 682 dev_err(priv->dev, "failed to enable vpcie3v3 (ret=%d)\n", 683 ret); 684 return ret; 685 } 686 } 687 688 if (priv->is_bifurcation) { 689 phy_cfg.pcie.is_bifurcation = true; 690 ret = generic_phy_configure(&priv->phy, &phy_cfg); 691 if (ret) 692 dev_err(dev, "failed to set bifurcation for phy (ret=%d)\n", ret); 693 } 694 695 ret = generic_phy_init(&priv->phy); 696 if (ret) { 697 dev_err(dev, "failed to init phy (ret=%d)\n", ret); 698 goto err_disable_3v3; 699 } 700 701 ret = generic_phy_power_on(&priv->phy); 702 if (ret) { 703 dev_err(dev, "failed to power on phy (ret=%d)\n", ret); 704 goto err_exit_phy; 705 } 706 707 ret = reset_deassert_bulk(&priv->rsts); 708 if (ret) { 709 dev_err(dev, "failed to deassert resets (ret=%d)\n", ret); 710 goto err_power_off_phy; 711 } 712 713 ret = clk_enable_bulk(&priv->clks); 714 if (ret) { 715 dev_err(dev, "failed to enable clks (ret=%d)\n", ret); 716 goto err_deassert_bulk; 717 } 718 719 /* LTSSM EN ctrl mode */ 720 val = rk_pcie_readl_apb(priv, PCIE_CLIENT_HOT_RESET_CTRL); 721 val |= PCIE_LTSSM_ENABLE_ENHANCE | (PCIE_LTSSM_ENABLE_ENHANCE << 16); 722 rk_pcie_writel_apb(priv, PCIE_CLIENT_HOT_RESET_CTRL, val); 723 724 /* Set RC mode */ 725 rk_pcie_writel_apb(priv, 0x0, 0xf00040); 726 rk_pcie_setup_host(priv); 727 728 for (retries = MAX_LINKUP_RETRIES; retries > 0; retries--) { 729 ret = rk_pcie_link_up(priv, priv->gen, priv->lanes); 730 if (ret >= 0) 731 return 0; 732 if(priv->vpcie3v3) { 733 regulator_set_enable(priv->vpcie3v3, false); 734 msleep(200); 735 regulator_set_enable(priv->vpcie3v3, true); 736 } 737 } 738 739 if (retries <= 0) 740 goto err_link_up; 741 742 return 0; 743 err_link_up: 744 clk_disable_bulk(&priv->clks); 745 err_deassert_bulk: 746 reset_assert_bulk(&priv->rsts); 747 err_power_off_phy: 748 if (!priv->is_bifurcation) 749 generic_phy_power_off(&priv->phy); 750 err_exit_phy: 751 if (!priv->is_bifurcation) 752 generic_phy_exit(&priv->phy); 753 err_disable_3v3: 754 if(priv->vpcie3v3 && !priv->is_bifurcation) 755 regulator_set_enable(priv->vpcie3v3, false); 756 return ret; 757 } 758 759 static int rockchip_pcie_parse_dt(struct udevice *dev) 760 { 761 struct rk_pcie *priv = dev_get_priv(dev); 762 u32 max_link_speed, num_lanes; 763 int ret; 764 struct resource res; 765 766 ret = dev_read_resource_byname(dev, "pcie-dbi", &res); 767 if (ret) 768 return -ENODEV; 769 priv->dbi_base = (void *)(res.start); 770 dev_dbg(dev, "DBI address is 0x%p\n", priv->dbi_base); 771 772 ret = dev_read_resource_byname(dev, "pcie-apb", &res); 773 if (ret) 774 return -ENODEV; 775 priv->apb_base = (void *)(res.start); 776 dev_dbg(dev, "APB address is 0x%p\n", priv->apb_base); 777 778 ret = gpio_request_by_name(dev, "reset-gpios", 0, 779 &priv->rst_gpio, GPIOD_IS_OUT); 780 if (ret) { 781 dev_err(dev, "failed to find reset-gpios property\n"); 782 return ret; 783 } 784 785 ret = reset_get_bulk(dev, &priv->rsts); 786 if (ret) { 787 dev_err(dev, "Can't get reset: %d\n", ret); 788 return ret; 789 } 790 791 ret = clk_get_bulk(dev, &priv->clks); 792 if (ret) { 793 dev_err(dev, "Can't get clock: %d\n", ret); 794 return ret; 795 } 796 797 ret = device_get_supply_regulator(dev, "vpcie3v3-supply", 798 &priv->vpcie3v3); 799 if (ret && ret != -ENOENT) { 800 dev_err(dev, "failed to get vpcie3v3 supply (ret=%d)\n", ret); 801 return ret; 802 } 803 804 ret = generic_phy_get_by_index(dev, 0, &priv->phy); 805 if (ret) { 806 dev_err(dev, "failed to get pcie phy (ret=%d)\n", ret); 807 return ret; 808 } 809 810 if (dev_read_bool(dev, "rockchip,bifurcation")) 811 priv->is_bifurcation = true; 812 813 ret = ofnode_read_u32(dev->node, "max-link-speed", &max_link_speed); 814 if (ret < 0 || max_link_speed > 4) 815 priv->gen = 0; 816 else 817 priv->gen = max_link_speed; 818 819 ret = ofnode_read_u32(dev->node, "num-lanes", &num_lanes); 820 if (ret >= 0 && ilog2(num_lanes) >= 0 && ilog2(num_lanes) <= 3) 821 priv->lanes = num_lanes; 822 823 return 0; 824 } 825 826 static int rockchip_pcie_probe(struct udevice *dev) 827 { 828 struct rk_pcie *priv = dev_get_priv(dev); 829 struct udevice *ctlr = pci_get_controller(dev); 830 struct pci_controller *hose = dev_get_uclass_priv(ctlr); 831 int ret; 832 833 priv->first_busno = dev->seq; 834 priv->dev = dev; 835 836 ret = rockchip_pcie_parse_dt(dev); 837 if (ret) 838 return ret; 839 840 ret = rockchip_pcie_init_port(dev); 841 if (ret) 842 goto free_rst; 843 844 dev_info(dev, "PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", 845 dev->seq, rk_pcie_get_link_speed(priv), 846 rk_pcie_get_link_width(priv), 847 hose->first_busno); 848 849 for (ret = 0; ret < hose->region_count; ret++) { 850 if (hose->regions[ret].flags == PCI_REGION_IO) { 851 priv->io.phys_start = hose->regions[ret].phys_start; /* IO base */ 852 priv->io.bus_start = hose->regions[ret].bus_start; /* IO_bus_addr */ 853 priv->io.size = hose->regions[ret].size; /* IO size */ 854 } else if (hose->regions[ret].flags == PCI_REGION_MEM) { 855 if (upper_32_bits(hose->regions[ret].bus_start)) {/* MEM64 base */ 856 priv->mem64.phys_start = hose->regions[ret].phys_start; 857 priv->mem64.bus_start = hose->regions[ret].bus_start; 858 priv->mem64.size = hose->regions[ret].size; 859 } else { /* MEM32 base */ 860 priv->mem.phys_start = hose->regions[ret].phys_start; 861 priv->mem.bus_start = hose->regions[ret].bus_start; 862 priv->mem.size = hose->regions[ret].size; 863 } 864 } else if (hose->regions[ret].flags == PCI_REGION_SYS_MEMORY) { 865 priv->cfg_base = (void *)(priv->io.phys_start - priv->io.size); 866 priv->cfg_size = priv->io.size; 867 } else if (hose->regions[ret].flags == PCI_REGION_PREFETCH) { 868 dev_err(dev, "don't support prefetchable memory, please fix your dtb.\n"); 869 } else { 870 dev_err(dev, "invalid flags type\n"); 871 } 872 } 873 874 #ifdef CONFIG_SYS_PCI_64BIT 875 dev_dbg(dev, "Config space: [0x%p - 0x%p, size 0x%llx]\n", 876 priv->cfg_base, priv->cfg_base + priv->cfg_size, 877 priv->cfg_size); 878 879 dev_dbg(dev, "IO space: [0x%llx - 0x%llx, size 0x%llx]\n", 880 priv->io.phys_start, priv->io.phys_start + priv->io.size, 881 priv->io.size); 882 883 dev_dbg(dev, "IO bus: [0x%llx - 0x%llx, size 0x%llx]\n", 884 priv->io.bus_start, priv->io.bus_start + priv->io.size, 885 priv->io.size); 886 887 dev_dbg(dev, "MEM32 space: [0x%llx - 0x%llx, size 0x%llx]\n", 888 priv->mem.phys_start, priv->mem.phys_start + priv->mem.size, 889 priv->mem.size); 890 891 dev_dbg(dev, "MEM32 bus: [0x%llx - 0x%llx, size 0x%llx]\n", 892 priv->mem.bus_start, priv->mem.bus_start + priv->mem.size, 893 priv->mem.size); 894 895 dev_dbg(dev, "MEM64 space: [0x%llx - 0x%llx, size 0x%llx]\n", 896 priv->mem64.phys_start, priv->mem64.phys_start + priv->mem64.size, 897 priv->mem64.size); 898 899 dev_dbg(dev, "MEM64 bus: [0x%llx - 0x%llx, size 0x%llx]\n", 900 priv->mem64.bus_start, priv->mem64.bus_start + priv->mem64.size, 901 priv->mem64.size); 902 903 rk_pcie_prog_outbound_atu_unroll(priv, PCIE_ATU_REGION_INDEX2, 904 PCIE_ATU_TYPE_MEM, 905 priv->mem64.phys_start, 906 priv->mem64.bus_start, priv->mem64.size); 907 #else 908 dev_dbg(dev, "Config space: [0x%p - 0x%p, size 0x%llx]\n", 909 priv->cfg_base, priv->cfg_base + priv->cfg_size, 910 priv->cfg_size); 911 912 dev_dbg(dev, "IO space: [0x%llx - 0x%llx, size 0x%x]\n", 913 priv->io.phys_start, priv->io.phys_start + priv->io.size, 914 priv->io.size); 915 916 dev_dbg(dev, "IO bus: [0x%x - 0x%x, size 0x%x]\n", 917 priv->io.bus_start, priv->io.bus_start + priv->io.size, 918 priv->io.size); 919 920 dev_dbg(dev, "MEM32 space: [0x%llx - 0x%llx, size 0x%x]\n", 921 priv->mem.phys_start, priv->mem.phys_start + priv->mem.size, 922 priv->mem.size); 923 924 dev_dbg(dev, "MEM32 bus: [0x%x - 0x%x, size 0x%x]\n", 925 priv->mem.bus_start, priv->mem.bus_start + priv->mem.size, 926 priv->mem.size); 927 928 #endif 929 rk_pcie_prog_outbound_atu_unroll(priv, PCIE_ATU_REGION_INDEX0, 930 PCIE_ATU_TYPE_MEM, 931 priv->mem.phys_start, 932 priv->mem.bus_start, priv->mem.size); 933 934 return 0; 935 free_rst: 936 dm_gpio_free(dev, &priv->rst_gpio); 937 return ret; 938 } 939 940 static const struct dm_pci_ops rockchip_pcie_ops = { 941 .read_config = rockchip_pcie_rd_conf, 942 .write_config = rockchip_pcie_wr_conf, 943 }; 944 945 static const struct udevice_id rockchip_pcie_ids[] = { 946 { .compatible = "rockchip,rk3528-pcie" }, 947 { .compatible = "rockchip,rk3562-pcie" }, 948 { .compatible = "rockchip,rk3568-pcie" }, 949 { .compatible = "rockchip,rk3588-pcie" }, 950 { .compatible = "rockchip,rk3576-pcie" }, 951 { } 952 }; 953 954 U_BOOT_DRIVER(rockchip_pcie) = { 955 .name = "pcie_dw_rockchip", 956 .id = UCLASS_PCI, 957 .of_match = rockchip_pcie_ids, 958 .ops = &rockchip_pcie_ops, 959 .probe = rockchip_pcie_probe, 960 .priv_auto_alloc_size = sizeof(struct rk_pcie), 961 }; 962