1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Rockchip DesignWare based PCIe host controller driver 4 * 5 * Copyright (c) 2021 Rockchip, Inc. 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <dm.h> 11 #include <generic-phy.h> 12 #include <pci.h> 13 #include <power-domain.h> 14 #include <power/regulator.h> 15 #include <reset.h> 16 #include <syscon.h> 17 #include <asm/io.h> 18 #include <asm-generic/gpio.h> 19 #include <asm/arch-rockchip/clock.h> 20 #include <linux/iopoll.h> 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 struct rk_pcie { 25 struct udevice *dev; 26 struct udevice *vpcie3v3; 27 void *dbi_base; 28 void *apb_base; 29 void *cfg_base; 30 fdt_size_t cfg_size; 31 struct phy phy; 32 struct clk_bulk clks; 33 int first_busno; 34 struct reset_ctl_bulk rsts; 35 struct gpio_desc rst_gpio; 36 struct pci_region io; 37 struct pci_region mem; 38 bool is_bifurcation; 39 }; 40 41 enum { 42 PCIBIOS_SUCCESSFUL = 0x0000, 43 PCIBIOS_UNSUPPORTED = -ENODEV, 44 PCIBIOS_NODEV = -ENODEV, 45 }; 46 47 #define msleep(a) udelay((a) * 1000) 48 49 /* Parameters for the waiting for iATU enabled routine */ 50 #define PCIE_CLIENT_GENERAL_DEBUG 0x104 51 #define PCIE_CLIENT_HOT_RESET_CTRL 0x180 52 #define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) 53 #define PCIE_CLIENT_LTSSM_STATUS 0x300 54 #define SMLH_LINKUP BIT(16) 55 #define RDLH_LINKUP BIT(17) 56 #define PCIE_CLIENT_DBG_FIFO_MODE_CON 0x310 57 #define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0 0x320 58 #define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1 0x324 59 #define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0 0x328 60 #define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1 0x32c 61 #define PCIE_CLIENT_DBG_FIFO_STATUS 0x350 62 #define PCIE_CLIENT_DBG_TRANSITION_DATA 0xffff0000 63 #define PCIE_CLIENT_DBF_EN 0xffff0003 64 #define RK_PCIE_DBG 0 65 66 /* PCI DBICS registers */ 67 #define PCIE_LINK_STATUS_REG 0x80 68 #define PCIE_LINK_STATUS_SPEED_OFF 16 69 #define PCIE_LINK_STATUS_SPEED_MASK (0xf << PCIE_LINK_STATUS_SPEED_OFF) 70 #define PCIE_LINK_STATUS_WIDTH_OFF 20 71 #define PCIE_LINK_STATUS_WIDTH_MASK (0xf << PCIE_LINK_STATUS_WIDTH_OFF) 72 73 #define PCIE_LINK_CAPABILITY 0x7c 74 #define PCIE_LINK_CTL_2 0xa0 75 #define TARGET_LINK_SPEED_MASK 0xf 76 #define LINK_SPEED_GEN_1 0x1 77 #define LINK_SPEED_GEN_2 0x2 78 #define LINK_SPEED_GEN_3 0x3 79 80 #define PCIE_MISC_CONTROL_1_OFF 0x8bc 81 #define PCIE_DBI_RO_WR_EN BIT(0) 82 83 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80c 84 #define PORT_LOGIC_SPEED_CHANGE BIT(17) 85 86 /* 87 * iATU Unroll-specific register definitions 88 * From 4.80 core version the address translation will be made by unroll. 89 * The registers are offset from atu_base 90 */ 91 #define PCIE_ATU_UNR_REGION_CTRL1 0x00 92 #define PCIE_ATU_UNR_REGION_CTRL2 0x04 93 #define PCIE_ATU_UNR_LOWER_BASE 0x08 94 #define PCIE_ATU_UNR_UPPER_BASE 0x0c 95 #define PCIE_ATU_UNR_LIMIT 0x10 96 #define PCIE_ATU_UNR_LOWER_TARGET 0x14 97 #define PCIE_ATU_UNR_UPPER_TARGET 0x18 98 99 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0) 100 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0) 101 #define PCIE_ATU_TYPE_MEM (0x0 << 0) 102 #define PCIE_ATU_TYPE_IO (0x2 << 0) 103 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0) 104 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0) 105 #define PCIE_ATU_ENABLE (0x1 << 31) 106 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) 107 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) 108 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) 109 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) 110 111 /* Register address builder */ 112 #define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) \ 113 ((0x3 << 20) | ((region) << 9)) 114 #define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region) \ 115 ((0x3 << 20) | ((region) << 9) | (0x1 << 8)) 116 117 /* Parameters for the waiting for iATU enabled routine */ 118 #define LINK_WAIT_MAX_IATU_RETRIES 5 119 #define LINK_WAIT_IATU 10000 120 121 static int rk_pcie_read(void __iomem *addr, int size, u32 *val) 122 { 123 if ((uintptr_t)addr & (size - 1)) { 124 *val = 0; 125 return PCIBIOS_UNSUPPORTED; 126 } 127 128 if (size == 4) { 129 *val = readl(addr); 130 } else if (size == 2) { 131 *val = readw(addr); 132 } else if (size == 1) { 133 *val = readb(addr); 134 } else { 135 *val = 0; 136 return PCIBIOS_NODEV; 137 } 138 139 return PCIBIOS_SUCCESSFUL; 140 } 141 142 static int rk_pcie_write(void __iomem *addr, int size, u32 val) 143 { 144 if ((uintptr_t)addr & (size - 1)) 145 return PCIBIOS_UNSUPPORTED; 146 147 if (size == 4) 148 writel(val, addr); 149 else if (size == 2) 150 writew(val, addr); 151 else if (size == 1) 152 writeb(val, addr); 153 else 154 return PCIBIOS_NODEV; 155 156 return PCIBIOS_SUCCESSFUL; 157 } 158 159 static u32 __rk_pcie_read_apb(struct rk_pcie *rk_pcie, void __iomem *base, 160 u32 reg, size_t size) 161 { 162 int ret; 163 u32 val; 164 165 ret = rk_pcie_read(base + reg, size, &val); 166 if (ret) 167 dev_err(rk_pcie->pci->dev, "Read APB address failed\n"); 168 169 return val; 170 } 171 172 static void __rk_pcie_write_apb(struct rk_pcie *rk_pcie, void __iomem *base, 173 u32 reg, size_t size, u32 val) 174 { 175 int ret; 176 177 ret = rk_pcie_write(base + reg, size, val); 178 if (ret) 179 dev_err(rk_pcie->pci->dev, "Write APB address failed\n"); 180 } 181 182 static inline u32 rk_pcie_readl_apb(struct rk_pcie *rk_pcie, u32 reg) 183 { 184 return __rk_pcie_read_apb(rk_pcie, rk_pcie->apb_base, reg, 0x4); 185 } 186 187 static inline void rk_pcie_writel_apb(struct rk_pcie *rk_pcie, u32 reg, 188 u32 val) 189 { 190 __rk_pcie_write_apb(rk_pcie, rk_pcie->apb_base, reg, 0x4, val); 191 } 192 193 static int rk_pcie_get_link_speed(struct rk_pcie *rk_pcie) 194 { 195 return (readl(rk_pcie->dbi_base + PCIE_LINK_STATUS_REG) & 196 PCIE_LINK_STATUS_SPEED_MASK) >> PCIE_LINK_STATUS_SPEED_OFF; 197 } 198 199 static int rk_pcie_get_link_width(struct rk_pcie *rk_pcie) 200 { 201 return (readl(rk_pcie->dbi_base + PCIE_LINK_STATUS_REG) & 202 PCIE_LINK_STATUS_WIDTH_MASK) >> PCIE_LINK_STATUS_WIDTH_OFF; 203 } 204 205 static void rk_pcie_writel_ob_unroll(struct rk_pcie *rk_pcie, u32 index, 206 u32 reg, u32 val) 207 { 208 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); 209 void __iomem *base = rk_pcie->dbi_base; 210 211 writel(val, base + offset + reg); 212 } 213 214 static u32 rk_pcie_readl_ob_unroll(struct rk_pcie *rk_pcie, u32 index, u32 reg) 215 { 216 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); 217 void __iomem *base = rk_pcie->dbi_base; 218 219 return readl(base + offset + reg); 220 } 221 222 static inline void rk_pcie_dbi_write_enable(struct rk_pcie *rk_pcie, bool en) 223 { 224 u32 val; 225 226 val = readl(rk_pcie->dbi_base + PCIE_MISC_CONTROL_1_OFF); 227 228 if (en) 229 val |= PCIE_DBI_RO_WR_EN; 230 else 231 val &= ~PCIE_DBI_RO_WR_EN; 232 writel(val, rk_pcie->dbi_base + PCIE_MISC_CONTROL_1_OFF); 233 } 234 235 static void rk_pcie_setup_host(struct rk_pcie *rk_pcie) 236 { 237 u32 val; 238 239 rk_pcie_dbi_write_enable(rk_pcie, true); 240 241 /* setup RC BARs */ 242 writel(PCI_BASE_ADDRESS_MEM_TYPE_64, 243 rk_pcie->dbi_base + PCI_BASE_ADDRESS_0); 244 writel(0x0, rk_pcie->dbi_base + PCI_BASE_ADDRESS_1); 245 246 /* setup interrupt pins */ 247 val = readl(rk_pcie->dbi_base + PCI_INTERRUPT_LINE); 248 val &= 0xffff00ff; 249 val |= 0x00000100; 250 writel(val, rk_pcie->dbi_base + PCI_INTERRUPT_LINE); 251 252 /* setup bus numbers */ 253 val = readl(rk_pcie->dbi_base + PCI_PRIMARY_BUS); 254 val &= 0xff000000; 255 val |= 0x00ff0100; 256 writel(val, rk_pcie->dbi_base + PCI_PRIMARY_BUS); 257 258 val = readl(rk_pcie->dbi_base + PCI_PRIMARY_BUS); 259 260 /* setup command register */ 261 val = readl(rk_pcie->dbi_base + PCI_COMMAND); 262 val &= 0xffff0000; 263 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 264 PCI_COMMAND_MASTER | PCI_COMMAND_SERR; 265 writel(val, rk_pcie->dbi_base + PCI_COMMAND); 266 267 /* program correct class for RC */ 268 writew(PCI_CLASS_BRIDGE_PCI, rk_pcie->dbi_base + PCI_CLASS_DEVICE); 269 /* Better disable write permission right after the update */ 270 271 val = readl(rk_pcie->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); 272 val |= PORT_LOGIC_SPEED_CHANGE; 273 writel(val, rk_pcie->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); 274 275 rk_pcie_dbi_write_enable(rk_pcie, false); 276 } 277 278 static void rk_pcie_configure(struct rk_pcie *pci, u32 cap_speed) 279 { 280 u32 val; 281 282 rk_pcie_dbi_write_enable(pci, true); 283 284 val = readl(pci->dbi_base + PCIE_LINK_CAPABILITY); 285 val &= ~TARGET_LINK_SPEED_MASK; 286 val |= cap_speed; 287 writel(val, pci->dbi_base + PCIE_LINK_CAPABILITY); 288 289 val = readl(pci->dbi_base + PCIE_LINK_CTL_2); 290 val &= ~TARGET_LINK_SPEED_MASK; 291 val |= cap_speed; 292 writel(val, pci->dbi_base + PCIE_LINK_CTL_2); 293 294 rk_pcie_dbi_write_enable(pci, false); 295 } 296 297 static void rk_pcie_prog_outbound_atu_unroll(struct rk_pcie *pci, int index, 298 int type, u64 cpu_addr, 299 u64 pci_addr, u32 size) 300 { 301 u32 retries, val; 302 303 dev_dbg(pci->dev, "ATU programmed with: index: %d, type: %d, cpu addr: %8llx, pci addr: %8llx, size: %8x\n", 304 index, type, cpu_addr, pci_addr, size); 305 306 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE, 307 lower_32_bits(cpu_addr)); 308 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE, 309 upper_32_bits(cpu_addr)); 310 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LIMIT, 311 lower_32_bits(cpu_addr + size - 1)); 312 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET, 313 lower_32_bits(pci_addr)); 314 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET, 315 upper_32_bits(pci_addr)); 316 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, 317 type); 318 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2, 319 PCIE_ATU_ENABLE); 320 321 /* 322 * Make sure ATU enable takes effect before any subsequent config 323 * and I/O accesses. 324 */ 325 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { 326 val = rk_pcie_readl_ob_unroll(pci, index, 327 PCIE_ATU_UNR_REGION_CTRL2); 328 if (val & PCIE_ATU_ENABLE) 329 return; 330 331 udelay(LINK_WAIT_IATU); 332 } 333 dev_err(pci->dev, "outbound iATU is not being enabled\n"); 334 } 335 336 static int rk_pcie_addr_valid(pci_dev_t d, int first_busno) 337 { 338 if ((PCI_BUS(d) == first_busno) && (PCI_DEV(d) > 0)) 339 return 0; 340 if ((PCI_BUS(d) == first_busno + 1) && (PCI_DEV(d) > 0)) 341 return 0; 342 343 return 1; 344 } 345 346 static uintptr_t set_cfg_address(struct rk_pcie *pcie, 347 pci_dev_t d, uint where) 348 { 349 int bus = PCI_BUS(d) - pcie->first_busno; 350 uintptr_t va_address; 351 u32 atu_type; 352 353 /* Use dbi_base for own configuration read and write */ 354 if (!bus) { 355 va_address = (uintptr_t)pcie->dbi_base; 356 goto out; 357 } 358 359 if (bus == 1) 360 /* 361 * For local bus whose primary bus number is root bridge, 362 * change TLP Type field to 4. 363 */ 364 atu_type = PCIE_ATU_TYPE_CFG0; 365 else 366 /* Otherwise, change TLP Type field to 5. */ 367 atu_type = PCIE_ATU_TYPE_CFG1; 368 369 /* 370 * Not accessing root port configuration space? 371 * Region #0 is used for Outbound CFG space access. 372 * Direction = Outbound 373 * Region Index = 0 374 */ 375 d = PCI_MASK_BUS(d); 376 d = PCI_ADD_BUS(bus, d); 377 rk_pcie_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1, 378 atu_type, (u64)pcie->cfg_base, 379 d << 8, pcie->cfg_size); 380 381 va_address = (uintptr_t)pcie->cfg_base; 382 383 out: 384 va_address += where & ~0x3; 385 386 return va_address; 387 } 388 389 static int rockchip_pcie_rd_conf(struct udevice *bus, pci_dev_t bdf, 390 uint offset, ulong *valuep, 391 enum pci_size_t size) 392 { 393 struct rk_pcie *pcie = dev_get_priv(bus); 394 uintptr_t va_address; 395 ulong value; 396 397 debug("PCIE CFG read: bdf=%2x:%2x:%2x\n", 398 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); 399 400 if (!rk_pcie_addr_valid(bdf, pcie->first_busno)) { 401 debug("- out of range\n"); 402 *valuep = pci_get_ff(size); 403 return 0; 404 } 405 406 va_address = set_cfg_address(pcie, bdf, offset); 407 408 value = readl(va_address); 409 410 debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value); 411 *valuep = pci_conv_32_to_size(value, offset, size); 412 413 rk_pcie_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1, 414 PCIE_ATU_TYPE_IO, pcie->io.phys_start, 415 pcie->io.bus_start, pcie->io.size); 416 417 return 0; 418 } 419 420 static int rockchip_pcie_wr_conf(struct udevice *bus, pci_dev_t bdf, 421 uint offset, ulong value, 422 enum pci_size_t size) 423 { 424 struct rk_pcie *pcie = dev_get_priv(bus); 425 uintptr_t va_address; 426 ulong old; 427 428 debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d)\n", 429 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); 430 debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value); 431 432 if (!rk_pcie_addr_valid(bdf, pcie->first_busno)) { 433 debug("- out of range\n"); 434 return 0; 435 } 436 437 va_address = set_cfg_address(pcie, bdf, offset); 438 439 old = readl(va_address); 440 value = pci_conv_size_to_32(old, value, offset, size); 441 writel(value, va_address); 442 443 rk_pcie_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1, 444 PCIE_ATU_TYPE_IO, pcie->io.phys_start, 445 pcie->io.bus_start, pcie->io.size); 446 447 return 0; 448 } 449 450 static void rk_pcie_enable_debug(struct rk_pcie *rk_pcie) 451 { 452 #if RK_PCIE_DBG 453 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0, 454 PCIE_CLIENT_DBG_TRANSITION_DATA); 455 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1, 456 PCIE_CLIENT_DBG_TRANSITION_DATA); 457 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0, 458 PCIE_CLIENT_DBG_TRANSITION_DATA); 459 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1, 460 PCIE_CLIENT_DBG_TRANSITION_DATA); 461 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_MODE_CON, 462 PCIE_CLIENT_DBF_EN); 463 #endif 464 } 465 466 static void rk_pcie_debug_dump(struct rk_pcie *rk_pcie) 467 { 468 #if RK_PCIE_DBG 469 u32 loop; 470 471 dev_info(rk_pcie->dev, "ltssm = 0x%x\n", 472 rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_LTSSM_STATUS)); 473 for (loop = 0; loop < 64; loop++) 474 dev_info(rk_pcie->dev, "fifo_status = 0x%x\n", 475 rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_STATUS)); 476 #endif 477 } 478 479 static inline void rk_pcie_link_status_clear(struct rk_pcie *rk_pcie) 480 { 481 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_GENERAL_DEBUG, 0x0); 482 } 483 484 static inline void rk_pcie_disable_ltssm(struct rk_pcie *rk_pcie) 485 { 486 rk_pcie_writel_apb(rk_pcie, 0x0, 0xc0008); 487 } 488 489 static inline void rk_pcie_enable_ltssm(struct rk_pcie *rk_pcie) 490 { 491 rk_pcie_writel_apb(rk_pcie, 0x0, 0xc000c); 492 } 493 494 static int is_link_up(struct rk_pcie *priv) 495 { 496 u32 val; 497 498 val = rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS); 499 if ((val & (RDLH_LINKUP | SMLH_LINKUP)) == 0x30000 && 500 (val & GENMASK(5, 0)) == 0x11) 501 return 1; 502 503 return 0; 504 } 505 506 static int rk_pcie_link_up(struct rk_pcie *priv, u32 cap_speed) 507 { 508 int retries; 509 510 if (is_link_up(priv)) { 511 printf("PCI Link already up before configuration!\n"); 512 return 1; 513 } 514 515 /* DW pre link configurations */ 516 rk_pcie_configure(priv, cap_speed); 517 518 /* Release the device */ 519 if (dm_gpio_is_valid(&priv->rst_gpio)) 520 dm_gpio_set_value(&priv->rst_gpio, 1); 521 522 rk_pcie_disable_ltssm(priv); 523 rk_pcie_link_status_clear(priv); 524 rk_pcie_enable_debug(priv); 525 526 /* Enable LTSSM */ 527 rk_pcie_enable_ltssm(priv); 528 529 for (retries = 0; retries < 50; retries++) { 530 if (is_link_up(priv)) { 531 dev_info(priv->dev, "PCIe Link up, LTSSM is 0x%x\n", 532 rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS)); 533 rk_pcie_debug_dump(priv); 534 /* Link maybe in Gen switch recovery but we need to wait more 1s */ 535 msleep(1000); 536 return 0; 537 } 538 539 dev_info(priv->dev, "PCIe Linking... LTSSM is 0x%x\n", 540 rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS)); 541 rk_pcie_debug_dump(priv); 542 msleep(10); 543 } 544 545 dev_err(priv->dev, "PCIe-%d Link Fail\n", priv->dev->seq); 546 return -EINVAL; 547 } 548 549 static int rockchip_pcie_init_port(struct udevice *dev) 550 { 551 int ret; 552 u32 val; 553 struct rk_pcie *priv = dev_get_priv(dev); 554 union phy_configure_opts phy_cfg; 555 556 /* Rest the device */ 557 if (dm_gpio_is_valid(&priv->rst_gpio)) 558 dm_gpio_set_value(&priv->rst_gpio, 0); 559 560 /* Set power and maybe external ref clk input */ 561 if (priv->vpcie3v3) { 562 ret = regulator_set_enable(priv->vpcie3v3, true); 563 if (ret) { 564 dev_err(priv->dev, "failed to enable vpcie3v3 (ret=%d)\n", 565 ret); 566 return ret; 567 } 568 } 569 570 if (priv->is_bifurcation) { 571 phy_cfg.pcie.is_bifurcation = true; 572 ret = generic_phy_configure(&priv->phy, &phy_cfg); 573 if (ret) 574 dev_err(dev, "failed to set bifurcation for phy (ret=%d)\n", ret); 575 } 576 577 ret = generic_phy_init(&priv->phy); 578 if (ret) { 579 dev_err(dev, "failed to init phy (ret=%d)\n", ret); 580 return ret; 581 } 582 583 ret = generic_phy_power_on(&priv->phy); 584 if (ret) { 585 dev_err(dev, "failed to power on phy (ret=%d)\n", ret); 586 goto err_exit_phy; 587 } 588 589 ret = reset_deassert_bulk(&priv->rsts); 590 if (ret) { 591 dev_err(dev, "failed to deassert resets (ret=%d)\n", ret); 592 goto err_power_off_phy; 593 } 594 595 ret = clk_enable_bulk(&priv->clks); 596 if (ret) { 597 dev_err(dev, "failed to enable clks (ret=%d)\n", ret); 598 goto err_deassert_bulk; 599 } 600 601 /* LTSSM EN ctrl mode */ 602 val = rk_pcie_readl_apb(priv, PCIE_CLIENT_HOT_RESET_CTRL); 603 val |= PCIE_LTSSM_ENABLE_ENHANCE | (PCIE_LTSSM_ENABLE_ENHANCE << 16); 604 rk_pcie_writel_apb(priv, PCIE_CLIENT_HOT_RESET_CTRL, val); 605 606 /* Set RC mode */ 607 rk_pcie_writel_apb(priv, 0x0, 0xf00040); 608 rk_pcie_setup_host(priv); 609 610 ret = rk_pcie_link_up(priv, LINK_SPEED_GEN_3); 611 if (ret < 0) 612 goto err_link_up; 613 614 return 0; 615 err_link_up: 616 clk_disable_bulk(&priv->clks); 617 err_deassert_bulk: 618 reset_assert_bulk(&priv->rsts); 619 err_power_off_phy: 620 generic_phy_power_off(&priv->phy); 621 err_exit_phy: 622 generic_phy_exit(&priv->phy); 623 return ret; 624 } 625 626 static int rockchip_pcie_parse_dt(struct udevice *dev) 627 { 628 struct rk_pcie *priv = dev_get_priv(dev); 629 int ret; 630 631 priv->dbi_base = (void *)dev_read_addr_index(dev, 0); 632 if (!priv->dbi_base) 633 return -ENODEV; 634 635 dev_dbg(dev, "DBI address is 0x%p\n", priv->dbi_base); 636 637 priv->apb_base = (void *)dev_read_addr_index(dev, 1); 638 if (!priv->apb_base) 639 return -ENODEV; 640 641 dev_dbg(dev, "APB address is 0x%p\n", priv->apb_base); 642 643 ret = gpio_request_by_name(dev, "reset-gpios", 0, 644 &priv->rst_gpio, GPIOD_IS_OUT); 645 if (ret) { 646 dev_err(dev, "failed to find reset-gpios property\n"); 647 return ret; 648 } 649 650 ret = reset_get_bulk(dev, &priv->rsts); 651 if (ret) { 652 dev_err(dev, "Can't get reset: %d\n", ret); 653 return ret; 654 } 655 656 ret = clk_get_bulk(dev, &priv->clks); 657 if (ret) { 658 dev_err(dev, "Can't get clock: %d\n", ret); 659 return ret; 660 } 661 662 ret = device_get_supply_regulator(dev, "vpcie3v3-supply", 663 &priv->vpcie3v3); 664 if (ret && ret != -ENOENT) { 665 dev_err(dev, "failed to get vpcie3v3 supply (ret=%d)\n", ret); 666 return ret; 667 } 668 669 ret = generic_phy_get_by_index(dev, 0, &priv->phy); 670 if (ret) { 671 dev_err(dev, "failed to get pcie phy (ret=%d)\n", ret); 672 return ret; 673 } 674 675 if (dev_read_bool(dev, "rockchip,bifurcation")) 676 priv->is_bifurcation = true; 677 678 return 0; 679 } 680 681 static int rockchip_pcie_probe(struct udevice *dev) 682 { 683 struct rk_pcie *priv = dev_get_priv(dev); 684 struct udevice *ctlr = pci_get_controller(dev); 685 struct pci_controller *hose = dev_get_uclass_priv(ctlr); 686 int ret; 687 688 priv->first_busno = dev->seq; 689 priv->dev = dev; 690 691 ret = rockchip_pcie_parse_dt(dev); 692 if (ret) 693 return ret; 694 695 ret = rockchip_pcie_init_port(dev); 696 if (ret) 697 return ret; 698 699 dev_info(dev, "PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", 700 dev->seq, rk_pcie_get_link_speed(priv), 701 rk_pcie_get_link_width(priv), 702 hose->first_busno); 703 704 for (ret = 0; ret < hose->region_count; ret++) { 705 if (hose->regions[ret].flags == PCI_REGION_IO) { 706 priv->io.phys_start = hose->regions[ret].phys_start; /* IO base */ 707 priv->io.bus_start = hose->regions[ret].bus_start; /* IO_bus_addr */ 708 priv->io.size = hose->regions[ret].size; /* IO size */ 709 } else if (hose->regions[ret].flags == PCI_REGION_MEM) { 710 priv->mem.phys_start = hose->regions[ret].phys_start; /* MEM base */ 711 priv->mem.bus_start = hose->regions[ret].bus_start; /* MEM_bus_addr */ 712 priv->mem.size = hose->regions[ret].size; /* MEM size */ 713 } else if (hose->regions[ret].flags == PCI_REGION_SYS_MEMORY) { 714 priv->cfg_base = (void *)(priv->io.phys_start - priv->io.size); 715 priv->cfg_size = priv->io.size; 716 } else { 717 dev_err(dev, "invalid flags type!\n"); 718 } 719 } 720 721 dev_dbg(dev, "Config space: [0x%p - 0x%p, size 0x%llx]\n", 722 priv->cfg_base, priv->cfg_base + priv->cfg_size, 723 priv->cfg_size); 724 725 dev_dbg(dev, "IO space: [0x%llx - 0x%llx, size 0x%x]\n", 726 priv->io.phys_start, priv->io.phys_start + priv->io.size, 727 priv->io.size); 728 729 dev_dbg(dev, "IO bus: [0x%x - 0x%x, size 0x%x]\n", 730 priv->io.bus_start, priv->io.bus_start + priv->io.size, 731 priv->io.size); 732 733 dev_dbg(dev, "MEM space: [0x%llx - 0x%llx, size 0x%x]\n", 734 priv->mem.phys_start, priv->mem.phys_start + priv->mem.size, 735 priv->mem.size); 736 737 dev_dbg(dev, "MEM bus: [0x%x - 0x%x, size 0x%x]\n", 738 priv->mem.bus_start, priv->mem.bus_start + priv->mem.size, 739 priv->mem.size); 740 741 rk_pcie_prog_outbound_atu_unroll(priv, PCIE_ATU_REGION_INDEX0, 742 PCIE_ATU_TYPE_MEM, 743 priv->mem.phys_start, 744 priv->mem.bus_start, priv->mem.size); 745 return 0; 746 } 747 748 static const struct dm_pci_ops rockchip_pcie_ops = { 749 .read_config = rockchip_pcie_rd_conf, 750 .write_config = rockchip_pcie_wr_conf, 751 }; 752 753 static const struct udevice_id rockchip_pcie_ids[] = { 754 { .compatible = "rockchip,rk3568-pcie" }, 755 { } 756 }; 757 758 U_BOOT_DRIVER(rockchip_pcie) = { 759 .name = "pcie_dw_rockchip", 760 .id = UCLASS_PCI, 761 .of_match = rockchip_pcie_ids, 762 .ops = &rockchip_pcie_ops, 763 .probe = rockchip_pcie_probe, 764 .priv_auto_alloc_size = sizeof(struct rk_pcie), 765 }; 766