1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Rockchip DesignWare based PCIe host controller driver 4 * 5 * Copyright (c) 2021 Rockchip, Inc. 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <dm.h> 11 #include <generic-phy.h> 12 #include <pci.h> 13 #include <power-domain.h> 14 #include <power/regulator.h> 15 #include <reset.h> 16 #include <syscon.h> 17 #include <asm/io.h> 18 #include <asm-generic/gpio.h> 19 #include <asm/arch-rockchip/clock.h> 20 #include <linux/bitfield.h> 21 #include <linux/iopoll.h> 22 #include <linux/ioport.h> 23 #include <linux/log2.h> 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 #define RK_PCIE_DBG 0 28 29 #define __pcie_dev_print_emit(fmt, ...) \ 30 ({ \ 31 printf(fmt, ##__VA_ARGS__); \ 32 }) 33 34 #ifdef dev_err 35 #undef dev_err 36 #define dev_err(dev, fmt, ...) \ 37 ({ \ 38 if (dev) \ 39 __pcie_dev_print_emit("%s: " fmt, dev->name, \ 40 ##__VA_ARGS__); \ 41 }) 42 #endif 43 44 #ifdef dev_info 45 #undef dev_info 46 #define dev_info dev_err 47 #endif 48 49 #ifdef DEBUG 50 #define dev_dbg dev_err 51 #else 52 #define dev_dbg(dev, fmt, ...) \ 53 ({ \ 54 if (0) \ 55 __dev_printk(7, dev, fmt, ##__VA_ARGS__); \ 56 }) 57 #endif 58 59 struct rk_pcie { 60 struct udevice *dev; 61 struct udevice *vpcie3v3; 62 void *dbi_base; 63 void *apb_base; 64 void *cfg_base; 65 fdt_size_t cfg_size; 66 struct phy phy; 67 struct clk_bulk clks; 68 int first_busno; 69 struct reset_ctl_bulk rsts; 70 struct gpio_desc rst_gpio; 71 struct pci_region io; 72 struct pci_region mem; 73 struct pci_region mem64; 74 bool is_bifurcation; 75 u32 rasdes_off; 76 u32 gen; 77 u32 lanes; 78 }; 79 80 enum { 81 PCIBIOS_SUCCESSFUL = 0x0000, 82 PCIBIOS_UNSUPPORTED = -ENODEV, 83 PCIBIOS_NODEV = -ENODEV, 84 }; 85 86 #define msleep(a) udelay((a) * 1000) 87 #define MAX_LINKUP_RETRIES 2 88 89 /* Parameters for the waiting for iATU enabled routine */ 90 #define PCIE_CLIENT_GENERAL_DEBUG 0x104 91 #define PCIE_CLIENT_CDM_RASDES_TBA_INFO_CMN 0x154 92 #define PCIE_CLIENT_HOT_RESET_CTRL 0x180 93 #define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) 94 #define PCIE_CLIENT_LTSSM_STATUS 0x300 95 #define SMLH_LINKUP BIT(16) 96 #define RDLH_LINKUP BIT(17) 97 #define PCIE_CLIENT_DBG_FIFO_MODE_CON 0x310 98 #define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0 0x320 99 #define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1 0x324 100 #define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0 0x328 101 #define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1 0x32c 102 #define PCIE_CLIENT_DBG_FIFO_STATUS 0x350 103 #define PCIE_CLIENT_DBG_TRANSITION_DATA 0xffff0000 104 #define PCIE_CLIENT_DBF_EN 0xffff0003 105 106 /* PCI DBICS registers */ 107 #define PCIE_LINK_STATUS_REG 0x80 108 #define PCIE_LINK_STATUS_SPEED_OFF 16 109 #define PCIE_LINK_STATUS_SPEED_MASK (0xf << PCIE_LINK_STATUS_SPEED_OFF) 110 #define PCIE_LINK_STATUS_WIDTH_OFF 20 111 #define PCIE_LINK_STATUS_WIDTH_MASK (0xf << PCIE_LINK_STATUS_WIDTH_OFF) 112 113 #define PCIE_LINK_CAPABILITY 0x7c 114 #define PCIE_LINK_CTL_2 0xa0 115 #define TARGET_LINK_SPEED_MASK 0xf 116 #define LINK_SPEED_GEN_1 0x1 117 #define LINK_SPEED_GEN_2 0x2 118 #define LINK_SPEED_GEN_3 0x3 119 120 #define PCIE_PORT_LINK_CONTROL 0x710 121 #define PORT_LINK_FAST_LINK_MODE BIT(7) 122 #define PCIE_MISC_CONTROL_1_OFF 0x8bc 123 #define PCIE_DBI_RO_WR_EN BIT(0) 124 125 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80c 126 #define PORT_LOGIC_SPEED_CHANGE BIT(17) 127 #define PORT_LINK_MODE_MASK GENMASK(21, 16) 128 #define PORT_LINK_MODE(n) FIELD_PREP(PORT_LINK_MODE_MASK, n) 129 #define PORT_LINK_MODE_1_LANES PORT_LINK_MODE(0x1) 130 #define PORT_LINK_MODE_2_LANES PORT_LINK_MODE(0x3) 131 #define PORT_LINK_MODE_4_LANES PORT_LINK_MODE(0x7) 132 #define PORT_LINK_MODE_8_LANES PORT_LINK_MODE(0xf) 133 #define PORT_LOGIC_LINK_WIDTH_MASK GENMASK(12, 8) 134 #define PORT_LOGIC_LINK_WIDTH(n) FIELD_PREP(PORT_LOGIC_LINK_WIDTH_MASK, n) 135 #define PORT_LOGIC_LINK_WIDTH_1_LANES PORT_LOGIC_LINK_WIDTH(0x1) 136 #define PORT_LOGIC_LINK_WIDTH_2_LANES PORT_LOGIC_LINK_WIDTH(0x2) 137 #define PORT_LOGIC_LINK_WIDTH_4_LANES PORT_LOGIC_LINK_WIDTH(0x4) 138 #define PORT_LOGIC_LINK_WIDTH_8_LANES PORT_LOGIC_LINK_WIDTH(0x8) 139 140 141 /* 142 * iATU Unroll-specific register definitions 143 * From 4.80 core version the address translation will be made by unroll. 144 * The registers are offset from atu_base 145 */ 146 #define PCIE_ATU_UNR_REGION_CTRL1 0x00 147 #define PCIE_ATU_UNR_REGION_CTRL2 0x04 148 #define PCIE_ATU_UNR_LOWER_BASE 0x08 149 #define PCIE_ATU_UNR_UPPER_BASE 0x0c 150 #define PCIE_ATU_UNR_LIMIT 0x10 151 #define PCIE_ATU_UNR_LOWER_TARGET 0x14 152 #define PCIE_ATU_UNR_UPPER_TARGET 0x18 153 154 #define PCIE_ATU_REGION_INDEX2 (0x2 << 0) 155 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0) 156 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0) 157 #define PCIE_ATU_TYPE_MEM (0x0 << 0) 158 #define PCIE_ATU_TYPE_IO (0x2 << 0) 159 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0) 160 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0) 161 #define PCIE_ATU_ENABLE (0x1 << 31) 162 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) 163 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) 164 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) 165 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) 166 167 /* Register address builder */ 168 #define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) \ 169 ((0x3 << 20) | ((region) << 9)) 170 #define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region) \ 171 ((0x3 << 20) | ((region) << 9) | (0x1 << 8)) 172 173 /* Parameters for the waiting for iATU enabled routine */ 174 #define LINK_WAIT_MAX_IATU_RETRIES 5 175 #define LINK_WAIT_IATU 10000 176 177 #define PCIE_TYPE0_HDR_DBI2_OFFSET 0x100000 178 179 static int rk_pcie_read(void __iomem *addr, int size, u32 *val) 180 { 181 if ((uintptr_t)addr & (size - 1)) { 182 *val = 0; 183 return PCIBIOS_UNSUPPORTED; 184 } 185 186 if (size == 4) { 187 *val = readl(addr); 188 } else if (size == 2) { 189 *val = readw(addr); 190 } else if (size == 1) { 191 *val = readb(addr); 192 } else { 193 *val = 0; 194 return PCIBIOS_NODEV; 195 } 196 197 return PCIBIOS_SUCCESSFUL; 198 } 199 200 static int rk_pcie_write(void __iomem *addr, int size, u32 val) 201 { 202 if ((uintptr_t)addr & (size - 1)) 203 return PCIBIOS_UNSUPPORTED; 204 205 if (size == 4) 206 writel(val, addr); 207 else if (size == 2) 208 writew(val, addr); 209 else if (size == 1) 210 writeb(val, addr); 211 else 212 return PCIBIOS_NODEV; 213 214 return PCIBIOS_SUCCESSFUL; 215 } 216 217 static u32 __rk_pcie_read_apb(struct rk_pcie *rk_pcie, void __iomem *base, 218 u32 reg, size_t size) 219 { 220 int ret; 221 u32 val; 222 223 ret = rk_pcie_read(base + reg, size, &val); 224 if (ret) 225 dev_err(rk_pcie->dev, "Read APB address failed\n"); 226 227 return val; 228 } 229 230 static void __rk_pcie_write_apb(struct rk_pcie *rk_pcie, void __iomem *base, 231 u32 reg, size_t size, u32 val) 232 { 233 int ret; 234 235 ret = rk_pcie_write(base + reg, size, val); 236 if (ret) 237 dev_err(rk_pcie->dev, "Write APB address failed\n"); 238 } 239 240 static inline u32 rk_pcie_readl_apb(struct rk_pcie *rk_pcie, u32 reg) 241 { 242 return __rk_pcie_read_apb(rk_pcie, rk_pcie->apb_base, reg, 0x4); 243 } 244 245 static inline void rk_pcie_writel_apb(struct rk_pcie *rk_pcie, u32 reg, 246 u32 val) 247 { 248 __rk_pcie_write_apb(rk_pcie, rk_pcie->apb_base, reg, 0x4, val); 249 } 250 251 static int rk_pcie_get_link_speed(struct rk_pcie *rk_pcie) 252 { 253 return (readl(rk_pcie->dbi_base + PCIE_LINK_STATUS_REG) & 254 PCIE_LINK_STATUS_SPEED_MASK) >> PCIE_LINK_STATUS_SPEED_OFF; 255 } 256 257 static int rk_pcie_get_link_width(struct rk_pcie *rk_pcie) 258 { 259 return (readl(rk_pcie->dbi_base + PCIE_LINK_STATUS_REG) & 260 PCIE_LINK_STATUS_WIDTH_MASK) >> PCIE_LINK_STATUS_WIDTH_OFF; 261 } 262 263 static void rk_pcie_writel_ob_unroll(struct rk_pcie *rk_pcie, u32 index, 264 u32 reg, u32 val) 265 { 266 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); 267 void __iomem *base = rk_pcie->dbi_base; 268 269 writel(val, base + offset + reg); 270 } 271 272 static u32 rk_pcie_readl_ob_unroll(struct rk_pcie *rk_pcie, u32 index, u32 reg) 273 { 274 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); 275 void __iomem *base = rk_pcie->dbi_base; 276 277 return readl(base + offset + reg); 278 } 279 280 static inline void rk_pcie_dbi_write_enable(struct rk_pcie *rk_pcie, bool en) 281 { 282 u32 val; 283 284 val = readl(rk_pcie->dbi_base + PCIE_MISC_CONTROL_1_OFF); 285 286 if (en) 287 val |= PCIE_DBI_RO_WR_EN; 288 else 289 val &= ~PCIE_DBI_RO_WR_EN; 290 writel(val, rk_pcie->dbi_base + PCIE_MISC_CONTROL_1_OFF); 291 } 292 293 static void rk_pcie_setup_host(struct rk_pcie *rk_pcie) 294 { 295 u32 val; 296 297 rk_pcie_dbi_write_enable(rk_pcie, true); 298 299 /* setup RC BARs */ 300 writel(PCI_BASE_ADDRESS_MEM_TYPE_64, 301 rk_pcie->dbi_base + PCI_BASE_ADDRESS_0); 302 writel(0x0, rk_pcie->dbi_base + PCI_BASE_ADDRESS_1); 303 304 /* setup interrupt pins */ 305 val = readl(rk_pcie->dbi_base + PCI_INTERRUPT_LINE); 306 val &= 0xffff00ff; 307 val |= 0x00000100; 308 writel(val, rk_pcie->dbi_base + PCI_INTERRUPT_LINE); 309 310 /* setup bus numbers */ 311 val = readl(rk_pcie->dbi_base + PCI_PRIMARY_BUS); 312 val &= 0xff000000; 313 val |= 0x00ff0100; 314 writel(val, rk_pcie->dbi_base + PCI_PRIMARY_BUS); 315 316 val = readl(rk_pcie->dbi_base + PCI_PRIMARY_BUS); 317 318 /* setup command register */ 319 val = readl(rk_pcie->dbi_base + PCI_COMMAND); 320 val &= 0xffff0000; 321 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 322 PCI_COMMAND_MASTER | PCI_COMMAND_SERR; 323 writel(val, rk_pcie->dbi_base + PCI_COMMAND); 324 325 /* program correct class for RC */ 326 writew(PCI_CLASS_BRIDGE_PCI, rk_pcie->dbi_base + PCI_CLASS_DEVICE); 327 /* Better disable write permission right after the update */ 328 329 val = readl(rk_pcie->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); 330 val |= PORT_LOGIC_SPEED_CHANGE; 331 writel(val, rk_pcie->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); 332 333 /* Disable BAR0 BAR1 */ 334 writel(0, rk_pcie->dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + 0 * 4); 335 writel(0, rk_pcie->dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + 1 * 4); 336 337 rk_pcie_dbi_write_enable(rk_pcie, false); 338 } 339 340 static void rk_pcie_configure(struct rk_pcie *pci, u32 cap_speed, u32 cap_lanes) 341 { 342 u32 val; 343 344 rk_pcie_dbi_write_enable(pci, true); 345 346 val = readl(pci->dbi_base + PCIE_LINK_CAPABILITY); 347 val &= ~TARGET_LINK_SPEED_MASK; 348 val |= cap_speed; 349 writel(val, pci->dbi_base + PCIE_LINK_CAPABILITY); 350 351 val = readl(pci->dbi_base + PCIE_LINK_CTL_2); 352 val &= ~TARGET_LINK_SPEED_MASK; 353 val |= cap_speed; 354 writel(val, pci->dbi_base + PCIE_LINK_CTL_2); 355 356 val = readl(pci->dbi_base + PCIE_PORT_LINK_CONTROL); 357 358 /* Set the number of lanes */ 359 val &= ~PORT_LINK_FAST_LINK_MODE; 360 val &= ~PORT_LINK_MODE_MASK; 361 switch (cap_lanes) { 362 case 1: 363 val |= PORT_LINK_MODE_1_LANES; 364 break; 365 case 2: 366 val |= PORT_LINK_MODE_2_LANES; 367 break; 368 case 4: 369 val |= PORT_LINK_MODE_4_LANES; 370 break; 371 case 8: 372 val |= PORT_LINK_MODE_8_LANES; 373 break; 374 default: 375 dev_err(pci->dev, "cap_lanes %u: invalid value\n", cap_lanes); 376 return; 377 } 378 writel(val, pci->dbi_base + PCIE_PORT_LINK_CONTROL); 379 380 /* Set link width speed control register */ 381 val = readl(pci->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); 382 val &= ~PORT_LOGIC_LINK_WIDTH_MASK; 383 switch (cap_lanes) { 384 case 1: 385 val |= PORT_LOGIC_LINK_WIDTH_1_LANES; 386 break; 387 case 2: 388 val |= PORT_LOGIC_LINK_WIDTH_2_LANES; 389 break; 390 case 4: 391 val |= PORT_LOGIC_LINK_WIDTH_4_LANES; 392 break; 393 case 8: 394 val |= PORT_LOGIC_LINK_WIDTH_8_LANES; 395 break; 396 } 397 writel(val, pci->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); 398 399 rk_pcie_dbi_write_enable(pci, false); 400 } 401 402 static void rk_pcie_prog_outbound_atu_unroll(struct rk_pcie *pci, int index, 403 int type, u64 cpu_addr, 404 u64 pci_addr, u32 size) 405 { 406 u32 retries, val; 407 408 dev_dbg(pci->dev, "ATU programmed with: index: %d, type: %d, cpu addr: %8llx, pci addr: %8llx, size: %8x\n", 409 index, type, cpu_addr, pci_addr, size); 410 411 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE, 412 lower_32_bits(cpu_addr)); 413 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE, 414 upper_32_bits(cpu_addr)); 415 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LIMIT, 416 lower_32_bits(cpu_addr + size - 1)); 417 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET, 418 lower_32_bits(pci_addr)); 419 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET, 420 upper_32_bits(pci_addr)); 421 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, 422 type); 423 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2, 424 PCIE_ATU_ENABLE); 425 426 /* 427 * Make sure ATU enable takes effect before any subsequent config 428 * and I/O accesses. 429 */ 430 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { 431 val = rk_pcie_readl_ob_unroll(pci, index, 432 PCIE_ATU_UNR_REGION_CTRL2); 433 if (val & PCIE_ATU_ENABLE) 434 return; 435 436 udelay(LINK_WAIT_IATU); 437 } 438 dev_err(pci->dev, "outbound iATU is not being enabled\n"); 439 } 440 441 static int rk_pcie_addr_valid(pci_dev_t d, int first_busno) 442 { 443 if ((PCI_BUS(d) == first_busno) && (PCI_DEV(d) > 0)) 444 return 0; 445 if ((PCI_BUS(d) == first_busno + 1) && (PCI_DEV(d) > 0)) 446 return 0; 447 448 return 1; 449 } 450 451 static uintptr_t set_cfg_address(struct rk_pcie *pcie, 452 pci_dev_t d, uint where) 453 { 454 int bus = PCI_BUS(d) - pcie->first_busno; 455 uintptr_t va_address; 456 u32 atu_type; 457 458 /* Use dbi_base for own configuration read and write */ 459 if (!bus) { 460 va_address = (uintptr_t)pcie->dbi_base; 461 goto out; 462 } 463 464 if (bus == 1) 465 /* 466 * For local bus whose primary bus number is root bridge, 467 * change TLP Type field to 4. 468 */ 469 atu_type = PCIE_ATU_TYPE_CFG0; 470 else 471 /* Otherwise, change TLP Type field to 5. */ 472 atu_type = PCIE_ATU_TYPE_CFG1; 473 474 /* 475 * Not accessing root port configuration space? 476 * Region #0 is used for Outbound CFG space access. 477 * Direction = Outbound 478 * Region Index = 0 479 */ 480 d = PCI_MASK_BUS(d); 481 d = PCI_ADD_BUS(bus, d); 482 rk_pcie_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1, 483 atu_type, (u64)pcie->cfg_base, 484 d << 8, pcie->cfg_size); 485 486 va_address = (uintptr_t)pcie->cfg_base; 487 488 out: 489 va_address += where & ~0x3; 490 491 return va_address; 492 } 493 494 static int rockchip_pcie_rd_conf(struct udevice *bus, pci_dev_t bdf, 495 uint offset, ulong *valuep, 496 enum pci_size_t size) 497 { 498 struct rk_pcie *pcie = dev_get_priv(bus); 499 uintptr_t va_address; 500 ulong value; 501 502 debug("PCIE CFG read: bdf=%2x:%2x:%2x\n", 503 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); 504 505 if (!rk_pcie_addr_valid(bdf, pcie->first_busno)) { 506 debug("- out of range\n"); 507 *valuep = pci_get_ff(size); 508 return 0; 509 } 510 511 va_address = set_cfg_address(pcie, bdf, offset); 512 513 value = readl(va_address); 514 515 debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value); 516 *valuep = pci_conv_32_to_size(value, offset, size); 517 518 rk_pcie_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1, 519 PCIE_ATU_TYPE_IO, pcie->io.phys_start, 520 pcie->io.bus_start, pcie->io.size); 521 522 return 0; 523 } 524 525 static int rockchip_pcie_wr_conf(struct udevice *bus, pci_dev_t bdf, 526 uint offset, ulong value, 527 enum pci_size_t size) 528 { 529 struct rk_pcie *pcie = dev_get_priv(bus); 530 uintptr_t va_address; 531 ulong old; 532 533 debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d)\n", 534 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); 535 debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value); 536 if (!rk_pcie_addr_valid(bdf, pcie->first_busno)) { 537 debug("- out of range\n"); 538 return 0; 539 } 540 541 va_address = set_cfg_address(pcie, bdf, offset); 542 543 old = readl(va_address); 544 value = pci_conv_size_to_32(old, value, offset, size); 545 writel(value, va_address); 546 547 rk_pcie_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1, 548 PCIE_ATU_TYPE_IO, pcie->io.phys_start, 549 pcie->io.bus_start, pcie->io.size); 550 551 return 0; 552 } 553 554 static void rk_pcie_enable_debug(struct rk_pcie *rk_pcie) 555 { 556 #if RK_PCIE_DBG 557 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0, 558 PCIE_CLIENT_DBG_TRANSITION_DATA); 559 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1, 560 PCIE_CLIENT_DBG_TRANSITION_DATA); 561 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0, 562 PCIE_CLIENT_DBG_TRANSITION_DATA); 563 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1, 564 PCIE_CLIENT_DBG_TRANSITION_DATA); 565 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_MODE_CON, 566 PCIE_CLIENT_DBF_EN); 567 #endif 568 } 569 570 static void rk_pcie_debug_dump(struct rk_pcie *rk_pcie) 571 { 572 #if RK_PCIE_DBG 573 u32 loop; 574 575 dev_err(rk_pcie->dev, "ltssm = 0x%x\n", 576 rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_LTSSM_STATUS)); 577 for (loop = 0; loop < 64; loop++) 578 dev_err(rk_pcie->dev, "fifo_status = 0x%x\n", 579 rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_STATUS)); 580 #endif 581 } 582 583 static inline void rk_pcie_link_status_clear(struct rk_pcie *rk_pcie) 584 { 585 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_GENERAL_DEBUG, 0x0); 586 } 587 588 static inline void rk_pcie_disable_ltssm(struct rk_pcie *rk_pcie) 589 { 590 rk_pcie_writel_apb(rk_pcie, 0x0, 0xc0008); 591 } 592 593 static inline void rk_pcie_enable_ltssm(struct rk_pcie *rk_pcie) 594 { 595 rk_pcie_writel_apb(rk_pcie, 0x0, 0xc000c); 596 } 597 598 static int is_link_up(struct rk_pcie *priv) 599 { 600 u32 val; 601 602 val = rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS); 603 if ((val & (RDLH_LINKUP | SMLH_LINKUP)) == 0x30000 && 604 (val & GENMASK(5, 0)) == 0x11) 605 return 1; 606 607 return 0; 608 } 609 610 static int rk_pcie_link_up(struct rk_pcie *priv, u32 cap_speed, u32 cap_lanes) 611 { 612 int retries; 613 614 if (is_link_up(priv)) { 615 printf("PCI Link already up before configuration!\n"); 616 return 1; 617 } 618 619 /* DW pre link configurations */ 620 rk_pcie_configure(priv, cap_speed, cap_lanes); 621 622 /* Release the device */ 623 if (dm_gpio_is_valid(&priv->rst_gpio)) { 624 /* 625 * T_PVPERL (Power stable to PERST# inactive) should be a minimum of 100ms. 626 * We add a 200ms by default for sake of hoping everthings 627 * work fine. 628 */ 629 msleep(200); 630 dm_gpio_set_value(&priv->rst_gpio, 1); 631 /* 632 * Add this 20ms delay because we observe link is always up stably after it and 633 * could help us save 20ms for scanning devices. 634 */ 635 msleep(20); 636 } 637 638 rk_pcie_disable_ltssm(priv); 639 rk_pcie_link_status_clear(priv); 640 rk_pcie_enable_debug(priv); 641 642 /* Enable LTSSM */ 643 rk_pcie_enable_ltssm(priv); 644 645 for (retries = 0; retries < 50; retries++) { 646 if (is_link_up(priv)) { 647 dev_info(priv->dev, "PCIe Link up, LTSSM is 0x%x\n", 648 rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS)); 649 rk_pcie_debug_dump(priv); 650 /* Link maybe in Gen switch recovery but we need to wait more 1s */ 651 msleep(1000); 652 return 0; 653 } 654 655 dev_info(priv->dev, "PCIe Linking... LTSSM is 0x%x\n", 656 rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS)); 657 rk_pcie_debug_dump(priv); 658 msleep(10); 659 } 660 661 dev_err(priv->dev, "PCIe-%d Link Fail\n", priv->dev->seq); 662 rk_pcie_disable_ltssm(priv); 663 if (dm_gpio_is_valid(&priv->rst_gpio)) 664 dm_gpio_set_value(&priv->rst_gpio, 0); 665 666 return -EINVAL; 667 } 668 669 static int rockchip_pcie_init_port(struct udevice *dev) 670 { 671 int ret, retries; 672 u32 val; 673 struct rk_pcie *priv = dev_get_priv(dev); 674 union phy_configure_opts phy_cfg; 675 676 /* Rest the device */ 677 if (dm_gpio_is_valid(&priv->rst_gpio)) 678 dm_gpio_set_value(&priv->rst_gpio, 0); 679 680 /* Set power and maybe external ref clk input */ 681 if (priv->vpcie3v3) { 682 ret = regulator_set_enable(priv->vpcie3v3, true); 683 if (ret) { 684 dev_err(priv->dev, "failed to enable vpcie3v3 (ret=%d)\n", 685 ret); 686 return ret; 687 } 688 } 689 690 if (priv->is_bifurcation) { 691 phy_cfg.pcie.is_bifurcation = true; 692 ret = generic_phy_configure(&priv->phy, &phy_cfg); 693 if (ret) 694 dev_err(dev, "failed to set bifurcation for phy (ret=%d)\n", ret); 695 } 696 697 ret = generic_phy_init(&priv->phy); 698 if (ret) { 699 dev_err(dev, "failed to init phy (ret=%d)\n", ret); 700 goto err_disable_3v3; 701 } 702 703 ret = generic_phy_power_on(&priv->phy); 704 if (ret) { 705 dev_err(dev, "failed to power on phy (ret=%d)\n", ret); 706 goto err_exit_phy; 707 } 708 709 ret = reset_deassert_bulk(&priv->rsts); 710 if (ret) { 711 dev_err(dev, "failed to deassert resets (ret=%d)\n", ret); 712 goto err_power_off_phy; 713 } 714 715 ret = clk_enable_bulk(&priv->clks); 716 if (ret) { 717 dev_err(dev, "failed to enable clks (ret=%d)\n", ret); 718 goto err_deassert_bulk; 719 } 720 721 /* LTSSM EN ctrl mode */ 722 val = rk_pcie_readl_apb(priv, PCIE_CLIENT_HOT_RESET_CTRL); 723 val |= PCIE_LTSSM_ENABLE_ENHANCE | (PCIE_LTSSM_ENABLE_ENHANCE << 16); 724 rk_pcie_writel_apb(priv, PCIE_CLIENT_HOT_RESET_CTRL, val); 725 726 /* Set RC mode */ 727 rk_pcie_writel_apb(priv, 0x0, 0xf00040); 728 rk_pcie_setup_host(priv); 729 730 for (retries = MAX_LINKUP_RETRIES; retries > 0; retries--) { 731 ret = rk_pcie_link_up(priv, priv->gen, priv->lanes); 732 if (ret >= 0) 733 return 0; 734 if(priv->vpcie3v3) { 735 regulator_set_enable(priv->vpcie3v3, false); 736 msleep(200); 737 regulator_set_enable(priv->vpcie3v3, true); 738 } 739 } 740 741 if (retries <= 0) 742 goto err_link_up; 743 744 return 0; 745 err_link_up: 746 clk_disable_bulk(&priv->clks); 747 err_deassert_bulk: 748 reset_assert_bulk(&priv->rsts); 749 err_power_off_phy: 750 if (!priv->is_bifurcation) 751 generic_phy_power_off(&priv->phy); 752 err_exit_phy: 753 if (!priv->is_bifurcation) 754 generic_phy_exit(&priv->phy); 755 err_disable_3v3: 756 if(priv->vpcie3v3 && !priv->is_bifurcation) 757 regulator_set_enable(priv->vpcie3v3, false); 758 return ret; 759 } 760 761 static int rockchip_pcie_parse_dt(struct udevice *dev) 762 { 763 struct rk_pcie *priv = dev_get_priv(dev); 764 u32 max_link_speed, num_lanes; 765 int ret; 766 struct resource res; 767 768 ret = dev_read_resource_byname(dev, "pcie-dbi", &res); 769 if (ret) 770 return -ENODEV; 771 priv->dbi_base = (void *)(res.start); 772 dev_dbg(dev, "DBI address is 0x%p\n", priv->dbi_base); 773 774 ret = dev_read_resource_byname(dev, "pcie-apb", &res); 775 if (ret) 776 return -ENODEV; 777 priv->apb_base = (void *)(res.start); 778 dev_dbg(dev, "APB address is 0x%p\n", priv->apb_base); 779 780 ret = gpio_request_by_name(dev, "reset-gpios", 0, 781 &priv->rst_gpio, GPIOD_IS_OUT); 782 if (ret) { 783 dev_err(dev, "failed to find reset-gpios property\n"); 784 return ret; 785 } 786 787 ret = reset_get_bulk(dev, &priv->rsts); 788 if (ret) { 789 dev_err(dev, "Can't get reset: %d\n", ret); 790 return ret; 791 } 792 793 ret = clk_get_bulk(dev, &priv->clks); 794 if (ret) { 795 dev_err(dev, "Can't get clock: %d\n", ret); 796 return ret; 797 } 798 799 ret = device_get_supply_regulator(dev, "vpcie3v3-supply", 800 &priv->vpcie3v3); 801 if (ret && ret != -ENOENT) { 802 dev_err(dev, "failed to get vpcie3v3 supply (ret=%d)\n", ret); 803 return ret; 804 } 805 806 ret = generic_phy_get_by_index(dev, 0, &priv->phy); 807 if (ret) { 808 dev_err(dev, "failed to get pcie phy (ret=%d)\n", ret); 809 return ret; 810 } 811 812 if (dev_read_bool(dev, "rockchip,bifurcation")) 813 priv->is_bifurcation = true; 814 815 ret = ofnode_read_u32(dev->node, "max-link-speed", &max_link_speed); 816 if (ret < 0 || max_link_speed > 4) 817 priv->gen = 0; 818 else 819 priv->gen = max_link_speed; 820 821 ret = ofnode_read_u32(dev->node, "num-lanes", &num_lanes); 822 if (ret >= 0 && ilog2(num_lanes) >= 0 && ilog2(num_lanes) <= 3) 823 priv->lanes = num_lanes; 824 825 return 0; 826 } 827 828 static int rockchip_pcie_probe(struct udevice *dev) 829 { 830 struct rk_pcie *priv = dev_get_priv(dev); 831 struct udevice *ctlr = pci_get_controller(dev); 832 struct pci_controller *hose = dev_get_uclass_priv(ctlr); 833 int ret; 834 835 priv->first_busno = dev->seq; 836 priv->dev = dev; 837 838 ret = rockchip_pcie_parse_dt(dev); 839 if (ret) 840 return ret; 841 842 ret = rockchip_pcie_init_port(dev); 843 if (ret) 844 goto free_rst; 845 846 dev_info(dev, "PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", 847 dev->seq, rk_pcie_get_link_speed(priv), 848 rk_pcie_get_link_width(priv), 849 hose->first_busno); 850 851 for (ret = 0; ret < hose->region_count; ret++) { 852 if (hose->regions[ret].flags == PCI_REGION_IO) { 853 priv->io.phys_start = hose->regions[ret].phys_start; /* IO base */ 854 priv->io.bus_start = hose->regions[ret].bus_start; /* IO_bus_addr */ 855 priv->io.size = hose->regions[ret].size; /* IO size */ 856 } else if (hose->regions[ret].flags == PCI_REGION_MEM) { 857 if (upper_32_bits(hose->regions[ret].bus_start)) {/* MEM64 base */ 858 priv->mem64.phys_start = hose->regions[ret].phys_start; 859 priv->mem64.bus_start = hose->regions[ret].bus_start; 860 priv->mem64.size = hose->regions[ret].size; 861 } else { /* MEM32 base */ 862 priv->mem.phys_start = hose->regions[ret].phys_start; 863 priv->mem.bus_start = hose->regions[ret].bus_start; 864 priv->mem.size = hose->regions[ret].size; 865 } 866 } else if (hose->regions[ret].flags == PCI_REGION_SYS_MEMORY) { 867 priv->cfg_base = (void *)(priv->io.phys_start - priv->io.size); 868 priv->cfg_size = priv->io.size; 869 } else if (hose->regions[ret].flags == PCI_REGION_PREFETCH) { 870 dev_err(dev, "don't support prefetchable memory, please fix your dtb.\n"); 871 } else { 872 dev_err(dev, "invalid flags type\n"); 873 } 874 } 875 876 #ifdef CONFIG_SYS_PCI_64BIT 877 dev_dbg(dev, "Config space: [0x%p - 0x%p, size 0x%llx]\n", 878 priv->cfg_base, priv->cfg_base + priv->cfg_size, 879 priv->cfg_size); 880 881 dev_dbg(dev, "IO space: [0x%llx - 0x%llx, size 0x%llx]\n", 882 priv->io.phys_start, priv->io.phys_start + priv->io.size, 883 priv->io.size); 884 885 dev_dbg(dev, "IO bus: [0x%llx - 0x%llx, size 0x%llx]\n", 886 priv->io.bus_start, priv->io.bus_start + priv->io.size, 887 priv->io.size); 888 889 dev_dbg(dev, "MEM32 space: [0x%llx - 0x%llx, size 0x%llx]\n", 890 priv->mem.phys_start, priv->mem.phys_start + priv->mem.size, 891 priv->mem.size); 892 893 dev_dbg(dev, "MEM32 bus: [0x%llx - 0x%llx, size 0x%llx]\n", 894 priv->mem.bus_start, priv->mem.bus_start + priv->mem.size, 895 priv->mem.size); 896 897 dev_dbg(dev, "MEM64 space: [0x%llx - 0x%llx, size 0x%llx]\n", 898 priv->mem64.phys_start, priv->mem64.phys_start + priv->mem64.size, 899 priv->mem64.size); 900 901 dev_dbg(dev, "MEM64 bus: [0x%llx - 0x%llx, size 0x%llx]\n", 902 priv->mem64.bus_start, priv->mem64.bus_start + priv->mem64.size, 903 priv->mem64.size); 904 905 rk_pcie_prog_outbound_atu_unroll(priv, PCIE_ATU_REGION_INDEX2, 906 PCIE_ATU_TYPE_MEM, 907 priv->mem64.phys_start, 908 priv->mem64.bus_start, priv->mem64.size); 909 #else 910 dev_dbg(dev, "Config space: [0x%p - 0x%p, size 0x%llx]\n", 911 priv->cfg_base, priv->cfg_base + priv->cfg_size, 912 priv->cfg_size); 913 914 dev_dbg(dev, "IO space: [0x%llx - 0x%llx, size 0x%x]\n", 915 priv->io.phys_start, priv->io.phys_start + priv->io.size, 916 priv->io.size); 917 918 dev_dbg(dev, "IO bus: [0x%x - 0x%x, size 0x%x]\n", 919 priv->io.bus_start, priv->io.bus_start + priv->io.size, 920 priv->io.size); 921 922 dev_dbg(dev, "MEM32 space: [0x%llx - 0x%llx, size 0x%x]\n", 923 priv->mem.phys_start, priv->mem.phys_start + priv->mem.size, 924 priv->mem.size); 925 926 dev_dbg(dev, "MEM32 bus: [0x%x - 0x%x, size 0x%x]\n", 927 priv->mem.bus_start, priv->mem.bus_start + priv->mem.size, 928 priv->mem.size); 929 930 #endif 931 rk_pcie_prog_outbound_atu_unroll(priv, PCIE_ATU_REGION_INDEX0, 932 PCIE_ATU_TYPE_MEM, 933 priv->mem.phys_start, 934 priv->mem.bus_start, priv->mem.size); 935 936 priv->rasdes_off = dm_pci_find_ext_capability(dev, PCI_EXT_CAP_ID_VNDR); 937 if (priv->rasdes_off) { 938 /* Enable RC's err dump */ 939 writel(0x1c, priv->dbi_base + priv->rasdes_off + 8); 940 writel(0x3, priv->dbi_base + priv->rasdes_off + 8); 941 } 942 943 return 0; 944 free_rst: 945 dm_gpio_free(dev, &priv->rst_gpio); 946 return ret; 947 } 948 949 #define RAS_DES_EVENT(ss, v) \ 950 do { \ 951 writel(v, priv->dbi_base + cap_base + 8); \ 952 printf(ss "0x%x\n", readl(priv->dbi_base + cap_base + 0xc)); \ 953 } while (0) 954 955 static int rockchip_pcie_err_dump(struct udevice *bus) 956 { 957 struct rk_pcie *priv = dev_get_priv(bus); 958 u32 val = rk_pcie_readl_apb(priv, PCIE_CLIENT_CDM_RASDES_TBA_INFO_CMN); 959 int cap_base; 960 char *pm; 961 962 if (val & BIT(6)) 963 pm = "In training"; 964 else if (val & BIT(5)) 965 pm = "L1.2"; 966 else if (val & BIT(4)) 967 pm = "L1.1"; 968 else if (val & BIT(3)) 969 pm = "L1"; 970 else if (val & BIT(2)) 971 pm = "L0"; 972 else if (val & 0x3) 973 pm = (val == 0x3) ? "L0s" : (val & BIT(1) ? "RX L0s" : "TX L0s"); 974 else 975 pm = "Invalid"; 976 977 printf("Common event signal status: %s\n", pm); 978 979 cap_base = priv->rasdes_off; 980 if (!priv->rasdes_off) 981 return 0; 982 983 RAS_DES_EVENT("EBUF Overflow: ", 0); 984 RAS_DES_EVENT("EBUF Under-run: ", 0x0010000); 985 RAS_DES_EVENT("Decode Error: ", 0x0020000); 986 RAS_DES_EVENT("Running Disparity Error: ", 0x0030000); 987 RAS_DES_EVENT("SKP OS Parity Error: ", 0x0040000); 988 RAS_DES_EVENT("SYNC Header Error: ", 0x0050000); 989 RAS_DES_EVENT("CTL SKP OS Parity Error: ", 0x0060000); 990 RAS_DES_EVENT("Detect EI Infer: ", 0x1050000); 991 RAS_DES_EVENT("Receiver Error: ", 0x1060000); 992 RAS_DES_EVENT("Rx Recovery Request: ", 0x1070000); 993 RAS_DES_EVENT("N_FTS Timeout: ", 0x1080000); 994 RAS_DES_EVENT("Framing Error: ", 0x1090000); 995 RAS_DES_EVENT("Deskew Error: ", 0x10a0000); 996 RAS_DES_EVENT("BAD TLP: ", 0x2000000); 997 RAS_DES_EVENT("LCRC Error: ", 0x2010000); 998 RAS_DES_EVENT("BAD DLLP: ", 0x2020000); 999 RAS_DES_EVENT("Replay Number Rollover: ", 0x2030000); 1000 RAS_DES_EVENT("Replay Timeout: ", 0x2040000); 1001 RAS_DES_EVENT("Rx Nak DLLP: ", 0x2050000); 1002 RAS_DES_EVENT("Tx Nak DLLP: ", 0x2060000); 1003 RAS_DES_EVENT("Retry TLP: ", 0x2070000); 1004 RAS_DES_EVENT("FC Timeout: ", 0x3000000); 1005 RAS_DES_EVENT("Poisoned TLP: ", 0x3010000); 1006 RAS_DES_EVENT("ECRC Error: ", 0x3020000); 1007 RAS_DES_EVENT("Unsupported Request: ", 0x3030000); 1008 RAS_DES_EVENT("Completer Abort: ", 0x3040000); 1009 RAS_DES_EVENT("Completion Timeout: ", 0x3050000); 1010 1011 return 0; 1012 } 1013 1014 static const struct dm_pci_ops rockchip_pcie_ops = { 1015 .read_config = rockchip_pcie_rd_conf, 1016 .write_config = rockchip_pcie_wr_conf, 1017 .vendor_aer_dump = rockchip_pcie_err_dump, 1018 }; 1019 1020 static const struct udevice_id rockchip_pcie_ids[] = { 1021 { .compatible = "rockchip,rk3528-pcie" }, 1022 { .compatible = "rockchip,rk3562-pcie" }, 1023 { .compatible = "rockchip,rk3568-pcie" }, 1024 { .compatible = "rockchip,rk3588-pcie" }, 1025 { .compatible = "rockchip,rk3576-pcie" }, 1026 { } 1027 }; 1028 1029 U_BOOT_DRIVER(rockchip_pcie) = { 1030 .name = "pcie_dw_rockchip", 1031 .id = UCLASS_PCI, 1032 .of_match = rockchip_pcie_ids, 1033 .ops = &rockchip_pcie_ops, 1034 .probe = rockchip_pcie_probe, 1035 .priv_auto_alloc_size = sizeof(struct rk_pcie), 1036 }; 1037