1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Rockchip DesignWare based PCIe host controller driver 4 * 5 * Copyright (c) 2021 Rockchip, Inc. 6 */ 7 8 #include <common.h> 9 #include <clk.h> 10 #include <dm.h> 11 #include <generic-phy.h> 12 #include <pci.h> 13 #include <power-domain.h> 14 #include <power/regulator.h> 15 #include <reset.h> 16 #include <syscon.h> 17 #include <asm/io.h> 18 #include <asm-generic/gpio.h> 19 #include <asm/arch-rockchip/clock.h> 20 #include <linux/iopoll.h> 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 struct rk_pcie { 25 struct udevice *dev; 26 struct udevice *vpcie3v3; 27 void *dbi_base; 28 void *apb_base; 29 void *cfg_base; 30 fdt_size_t cfg_size; 31 struct phy phy; 32 struct clk_bulk clks; 33 int first_busno; 34 struct reset_ctl_bulk rsts; 35 struct gpio_desc rst_gpio; 36 struct pci_region io; 37 struct pci_region mem; 38 bool is_bifurcation; 39 u32 gen; 40 }; 41 42 enum { 43 PCIBIOS_SUCCESSFUL = 0x0000, 44 PCIBIOS_UNSUPPORTED = -ENODEV, 45 PCIBIOS_NODEV = -ENODEV, 46 }; 47 48 #define msleep(a) udelay((a) * 1000) 49 50 /* Parameters for the waiting for iATU enabled routine */ 51 #define PCIE_CLIENT_GENERAL_DEBUG 0x104 52 #define PCIE_CLIENT_HOT_RESET_CTRL 0x180 53 #define PCIE_LTSSM_ENABLE_ENHANCE BIT(4) 54 #define PCIE_CLIENT_LTSSM_STATUS 0x300 55 #define SMLH_LINKUP BIT(16) 56 #define RDLH_LINKUP BIT(17) 57 #define PCIE_CLIENT_DBG_FIFO_MODE_CON 0x310 58 #define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0 0x320 59 #define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1 0x324 60 #define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0 0x328 61 #define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1 0x32c 62 #define PCIE_CLIENT_DBG_FIFO_STATUS 0x350 63 #define PCIE_CLIENT_DBG_TRANSITION_DATA 0xffff0000 64 #define PCIE_CLIENT_DBF_EN 0xffff0003 65 #define RK_PCIE_DBG 0 66 67 /* PCI DBICS registers */ 68 #define PCIE_LINK_STATUS_REG 0x80 69 #define PCIE_LINK_STATUS_SPEED_OFF 16 70 #define PCIE_LINK_STATUS_SPEED_MASK (0xf << PCIE_LINK_STATUS_SPEED_OFF) 71 #define PCIE_LINK_STATUS_WIDTH_OFF 20 72 #define PCIE_LINK_STATUS_WIDTH_MASK (0xf << PCIE_LINK_STATUS_WIDTH_OFF) 73 74 #define PCIE_LINK_CAPABILITY 0x7c 75 #define PCIE_LINK_CTL_2 0xa0 76 #define TARGET_LINK_SPEED_MASK 0xf 77 #define LINK_SPEED_GEN_1 0x1 78 #define LINK_SPEED_GEN_2 0x2 79 #define LINK_SPEED_GEN_3 0x3 80 81 #define PCIE_MISC_CONTROL_1_OFF 0x8bc 82 #define PCIE_DBI_RO_WR_EN BIT(0) 83 84 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80c 85 #define PORT_LOGIC_SPEED_CHANGE BIT(17) 86 87 /* 88 * iATU Unroll-specific register definitions 89 * From 4.80 core version the address translation will be made by unroll. 90 * The registers are offset from atu_base 91 */ 92 #define PCIE_ATU_UNR_REGION_CTRL1 0x00 93 #define PCIE_ATU_UNR_REGION_CTRL2 0x04 94 #define PCIE_ATU_UNR_LOWER_BASE 0x08 95 #define PCIE_ATU_UNR_UPPER_BASE 0x0c 96 #define PCIE_ATU_UNR_LIMIT 0x10 97 #define PCIE_ATU_UNR_LOWER_TARGET 0x14 98 #define PCIE_ATU_UNR_UPPER_TARGET 0x18 99 100 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0) 101 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0) 102 #define PCIE_ATU_TYPE_MEM (0x0 << 0) 103 #define PCIE_ATU_TYPE_IO (0x2 << 0) 104 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0) 105 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0) 106 #define PCIE_ATU_ENABLE (0x1 << 31) 107 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) 108 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) 109 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) 110 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) 111 112 /* Register address builder */ 113 #define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) \ 114 ((0x3 << 20) | ((region) << 9)) 115 #define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region) \ 116 ((0x3 << 20) | ((region) << 9) | (0x1 << 8)) 117 118 /* Parameters for the waiting for iATU enabled routine */ 119 #define LINK_WAIT_MAX_IATU_RETRIES 5 120 #define LINK_WAIT_IATU 10000 121 122 static int rk_pcie_read(void __iomem *addr, int size, u32 *val) 123 { 124 if ((uintptr_t)addr & (size - 1)) { 125 *val = 0; 126 return PCIBIOS_UNSUPPORTED; 127 } 128 129 if (size == 4) { 130 *val = readl(addr); 131 } else if (size == 2) { 132 *val = readw(addr); 133 } else if (size == 1) { 134 *val = readb(addr); 135 } else { 136 *val = 0; 137 return PCIBIOS_NODEV; 138 } 139 140 return PCIBIOS_SUCCESSFUL; 141 } 142 143 static int rk_pcie_write(void __iomem *addr, int size, u32 val) 144 { 145 if ((uintptr_t)addr & (size - 1)) 146 return PCIBIOS_UNSUPPORTED; 147 148 if (size == 4) 149 writel(val, addr); 150 else if (size == 2) 151 writew(val, addr); 152 else if (size == 1) 153 writeb(val, addr); 154 else 155 return PCIBIOS_NODEV; 156 157 return PCIBIOS_SUCCESSFUL; 158 } 159 160 static u32 __rk_pcie_read_apb(struct rk_pcie *rk_pcie, void __iomem *base, 161 u32 reg, size_t size) 162 { 163 int ret; 164 u32 val; 165 166 ret = rk_pcie_read(base + reg, size, &val); 167 if (ret) 168 dev_err(rk_pcie->pci->dev, "Read APB address failed\n"); 169 170 return val; 171 } 172 173 static void __rk_pcie_write_apb(struct rk_pcie *rk_pcie, void __iomem *base, 174 u32 reg, size_t size, u32 val) 175 { 176 int ret; 177 178 ret = rk_pcie_write(base + reg, size, val); 179 if (ret) 180 dev_err(rk_pcie->pci->dev, "Write APB address failed\n"); 181 } 182 183 static inline u32 rk_pcie_readl_apb(struct rk_pcie *rk_pcie, u32 reg) 184 { 185 return __rk_pcie_read_apb(rk_pcie, rk_pcie->apb_base, reg, 0x4); 186 } 187 188 static inline void rk_pcie_writel_apb(struct rk_pcie *rk_pcie, u32 reg, 189 u32 val) 190 { 191 __rk_pcie_write_apb(rk_pcie, rk_pcie->apb_base, reg, 0x4, val); 192 } 193 194 static int rk_pcie_get_link_speed(struct rk_pcie *rk_pcie) 195 { 196 return (readl(rk_pcie->dbi_base + PCIE_LINK_STATUS_REG) & 197 PCIE_LINK_STATUS_SPEED_MASK) >> PCIE_LINK_STATUS_SPEED_OFF; 198 } 199 200 static int rk_pcie_get_link_width(struct rk_pcie *rk_pcie) 201 { 202 return (readl(rk_pcie->dbi_base + PCIE_LINK_STATUS_REG) & 203 PCIE_LINK_STATUS_WIDTH_MASK) >> PCIE_LINK_STATUS_WIDTH_OFF; 204 } 205 206 static void rk_pcie_writel_ob_unroll(struct rk_pcie *rk_pcie, u32 index, 207 u32 reg, u32 val) 208 { 209 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); 210 void __iomem *base = rk_pcie->dbi_base; 211 212 writel(val, base + offset + reg); 213 } 214 215 static u32 rk_pcie_readl_ob_unroll(struct rk_pcie *rk_pcie, u32 index, u32 reg) 216 { 217 u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); 218 void __iomem *base = rk_pcie->dbi_base; 219 220 return readl(base + offset + reg); 221 } 222 223 static inline void rk_pcie_dbi_write_enable(struct rk_pcie *rk_pcie, bool en) 224 { 225 u32 val; 226 227 val = readl(rk_pcie->dbi_base + PCIE_MISC_CONTROL_1_OFF); 228 229 if (en) 230 val |= PCIE_DBI_RO_WR_EN; 231 else 232 val &= ~PCIE_DBI_RO_WR_EN; 233 writel(val, rk_pcie->dbi_base + PCIE_MISC_CONTROL_1_OFF); 234 } 235 236 static void rk_pcie_setup_host(struct rk_pcie *rk_pcie) 237 { 238 u32 val; 239 240 rk_pcie_dbi_write_enable(rk_pcie, true); 241 242 /* setup RC BARs */ 243 writel(PCI_BASE_ADDRESS_MEM_TYPE_64, 244 rk_pcie->dbi_base + PCI_BASE_ADDRESS_0); 245 writel(0x0, rk_pcie->dbi_base + PCI_BASE_ADDRESS_1); 246 247 /* setup interrupt pins */ 248 val = readl(rk_pcie->dbi_base + PCI_INTERRUPT_LINE); 249 val &= 0xffff00ff; 250 val |= 0x00000100; 251 writel(val, rk_pcie->dbi_base + PCI_INTERRUPT_LINE); 252 253 /* setup bus numbers */ 254 val = readl(rk_pcie->dbi_base + PCI_PRIMARY_BUS); 255 val &= 0xff000000; 256 val |= 0x00ff0100; 257 writel(val, rk_pcie->dbi_base + PCI_PRIMARY_BUS); 258 259 val = readl(rk_pcie->dbi_base + PCI_PRIMARY_BUS); 260 261 /* setup command register */ 262 val = readl(rk_pcie->dbi_base + PCI_COMMAND); 263 val &= 0xffff0000; 264 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 265 PCI_COMMAND_MASTER | PCI_COMMAND_SERR; 266 writel(val, rk_pcie->dbi_base + PCI_COMMAND); 267 268 /* program correct class for RC */ 269 writew(PCI_CLASS_BRIDGE_PCI, rk_pcie->dbi_base + PCI_CLASS_DEVICE); 270 /* Better disable write permission right after the update */ 271 272 val = readl(rk_pcie->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); 273 val |= PORT_LOGIC_SPEED_CHANGE; 274 writel(val, rk_pcie->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); 275 276 rk_pcie_dbi_write_enable(rk_pcie, false); 277 } 278 279 static void rk_pcie_configure(struct rk_pcie *pci, u32 cap_speed) 280 { 281 u32 val; 282 283 rk_pcie_dbi_write_enable(pci, true); 284 285 val = readl(pci->dbi_base + PCIE_LINK_CAPABILITY); 286 val &= ~TARGET_LINK_SPEED_MASK; 287 val |= cap_speed; 288 writel(val, pci->dbi_base + PCIE_LINK_CAPABILITY); 289 290 val = readl(pci->dbi_base + PCIE_LINK_CTL_2); 291 val &= ~TARGET_LINK_SPEED_MASK; 292 val |= cap_speed; 293 writel(val, pci->dbi_base + PCIE_LINK_CTL_2); 294 295 rk_pcie_dbi_write_enable(pci, false); 296 } 297 298 static void rk_pcie_prog_outbound_atu_unroll(struct rk_pcie *pci, int index, 299 int type, u64 cpu_addr, 300 u64 pci_addr, u32 size) 301 { 302 u32 retries, val; 303 304 dev_dbg(pci->dev, "ATU programmed with: index: %d, type: %d, cpu addr: %8llx, pci addr: %8llx, size: %8x\n", 305 index, type, cpu_addr, pci_addr, size); 306 307 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE, 308 lower_32_bits(cpu_addr)); 309 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE, 310 upper_32_bits(cpu_addr)); 311 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LIMIT, 312 lower_32_bits(cpu_addr + size - 1)); 313 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET, 314 lower_32_bits(pci_addr)); 315 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET, 316 upper_32_bits(pci_addr)); 317 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, 318 type); 319 rk_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2, 320 PCIE_ATU_ENABLE); 321 322 /* 323 * Make sure ATU enable takes effect before any subsequent config 324 * and I/O accesses. 325 */ 326 for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { 327 val = rk_pcie_readl_ob_unroll(pci, index, 328 PCIE_ATU_UNR_REGION_CTRL2); 329 if (val & PCIE_ATU_ENABLE) 330 return; 331 332 udelay(LINK_WAIT_IATU); 333 } 334 dev_err(pci->dev, "outbound iATU is not being enabled\n"); 335 } 336 337 static int rk_pcie_addr_valid(pci_dev_t d, int first_busno) 338 { 339 if ((PCI_BUS(d) == first_busno) && (PCI_DEV(d) > 0)) 340 return 0; 341 if ((PCI_BUS(d) == first_busno + 1) && (PCI_DEV(d) > 0)) 342 return 0; 343 344 return 1; 345 } 346 347 static uintptr_t set_cfg_address(struct rk_pcie *pcie, 348 pci_dev_t d, uint where) 349 { 350 int bus = PCI_BUS(d) - pcie->first_busno; 351 uintptr_t va_address; 352 u32 atu_type; 353 354 /* Use dbi_base for own configuration read and write */ 355 if (!bus) { 356 va_address = (uintptr_t)pcie->dbi_base; 357 goto out; 358 } 359 360 if (bus == 1) 361 /* 362 * For local bus whose primary bus number is root bridge, 363 * change TLP Type field to 4. 364 */ 365 atu_type = PCIE_ATU_TYPE_CFG0; 366 else 367 /* Otherwise, change TLP Type field to 5. */ 368 atu_type = PCIE_ATU_TYPE_CFG1; 369 370 /* 371 * Not accessing root port configuration space? 372 * Region #0 is used for Outbound CFG space access. 373 * Direction = Outbound 374 * Region Index = 0 375 */ 376 d = PCI_MASK_BUS(d); 377 d = PCI_ADD_BUS(bus, d); 378 rk_pcie_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1, 379 atu_type, (u64)pcie->cfg_base, 380 d << 8, pcie->cfg_size); 381 382 va_address = (uintptr_t)pcie->cfg_base; 383 384 out: 385 va_address += where & ~0x3; 386 387 return va_address; 388 } 389 390 static int rockchip_pcie_rd_conf(struct udevice *bus, pci_dev_t bdf, 391 uint offset, ulong *valuep, 392 enum pci_size_t size) 393 { 394 struct rk_pcie *pcie = dev_get_priv(bus); 395 uintptr_t va_address; 396 ulong value; 397 398 debug("PCIE CFG read: bdf=%2x:%2x:%2x\n", 399 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); 400 401 if (!rk_pcie_addr_valid(bdf, pcie->first_busno)) { 402 debug("- out of range\n"); 403 *valuep = pci_get_ff(size); 404 return 0; 405 } 406 407 va_address = set_cfg_address(pcie, bdf, offset); 408 409 value = readl(va_address); 410 411 debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value); 412 *valuep = pci_conv_32_to_size(value, offset, size); 413 414 rk_pcie_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1, 415 PCIE_ATU_TYPE_IO, pcie->io.phys_start, 416 pcie->io.bus_start, pcie->io.size); 417 418 return 0; 419 } 420 421 static int rockchip_pcie_wr_conf(struct udevice *bus, pci_dev_t bdf, 422 uint offset, ulong value, 423 enum pci_size_t size) 424 { 425 struct rk_pcie *pcie = dev_get_priv(bus); 426 uintptr_t va_address; 427 ulong old; 428 429 debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d)\n", 430 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); 431 debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value); 432 433 if (!rk_pcie_addr_valid(bdf, pcie->first_busno)) { 434 debug("- out of range\n"); 435 return 0; 436 } 437 438 va_address = set_cfg_address(pcie, bdf, offset); 439 440 old = readl(va_address); 441 value = pci_conv_size_to_32(old, value, offset, size); 442 writel(value, va_address); 443 444 rk_pcie_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1, 445 PCIE_ATU_TYPE_IO, pcie->io.phys_start, 446 pcie->io.bus_start, pcie->io.size); 447 448 return 0; 449 } 450 451 static void rk_pcie_enable_debug(struct rk_pcie *rk_pcie) 452 { 453 #if RK_PCIE_DBG 454 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0, 455 PCIE_CLIENT_DBG_TRANSITION_DATA); 456 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1, 457 PCIE_CLIENT_DBG_TRANSITION_DATA); 458 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0, 459 PCIE_CLIENT_DBG_TRANSITION_DATA); 460 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1, 461 PCIE_CLIENT_DBG_TRANSITION_DATA); 462 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_MODE_CON, 463 PCIE_CLIENT_DBF_EN); 464 #endif 465 } 466 467 static void rk_pcie_debug_dump(struct rk_pcie *rk_pcie) 468 { 469 #if RK_PCIE_DBG 470 u32 loop; 471 472 dev_info(rk_pcie->dev, "ltssm = 0x%x\n", 473 rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_LTSSM_STATUS)); 474 for (loop = 0; loop < 64; loop++) 475 dev_info(rk_pcie->dev, "fifo_status = 0x%x\n", 476 rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_STATUS)); 477 #endif 478 } 479 480 static inline void rk_pcie_link_status_clear(struct rk_pcie *rk_pcie) 481 { 482 rk_pcie_writel_apb(rk_pcie, PCIE_CLIENT_GENERAL_DEBUG, 0x0); 483 } 484 485 static inline void rk_pcie_disable_ltssm(struct rk_pcie *rk_pcie) 486 { 487 rk_pcie_writel_apb(rk_pcie, 0x0, 0xc0008); 488 } 489 490 static inline void rk_pcie_enable_ltssm(struct rk_pcie *rk_pcie) 491 { 492 rk_pcie_writel_apb(rk_pcie, 0x0, 0xc000c); 493 } 494 495 static int is_link_up(struct rk_pcie *priv) 496 { 497 u32 val; 498 499 val = rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS); 500 if ((val & (RDLH_LINKUP | SMLH_LINKUP)) == 0x30000 && 501 (val & GENMASK(5, 0)) == 0x11) 502 return 1; 503 504 return 0; 505 } 506 507 static int rk_pcie_link_up(struct rk_pcie *priv, u32 cap_speed) 508 { 509 int retries; 510 511 if (is_link_up(priv)) { 512 printf("PCI Link already up before configuration!\n"); 513 return 1; 514 } 515 516 /* DW pre link configurations */ 517 rk_pcie_configure(priv, cap_speed); 518 519 /* Release the device */ 520 if (dm_gpio_is_valid(&priv->rst_gpio)) 521 dm_gpio_set_value(&priv->rst_gpio, 1); 522 523 rk_pcie_disable_ltssm(priv); 524 rk_pcie_link_status_clear(priv); 525 rk_pcie_enable_debug(priv); 526 527 /* Enable LTSSM */ 528 rk_pcie_enable_ltssm(priv); 529 530 for (retries = 0; retries < 50; retries++) { 531 if (is_link_up(priv)) { 532 dev_info(priv->dev, "PCIe Link up, LTSSM is 0x%x\n", 533 rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS)); 534 rk_pcie_debug_dump(priv); 535 /* Link maybe in Gen switch recovery but we need to wait more 1s */ 536 msleep(1000); 537 return 0; 538 } 539 540 dev_info(priv->dev, "PCIe Linking... LTSSM is 0x%x\n", 541 rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS)); 542 rk_pcie_debug_dump(priv); 543 msleep(10); 544 } 545 546 dev_err(priv->dev, "PCIe-%d Link Fail\n", priv->dev->seq); 547 return -EINVAL; 548 } 549 550 static int rockchip_pcie_init_port(struct udevice *dev) 551 { 552 int ret; 553 u32 val; 554 struct rk_pcie *priv = dev_get_priv(dev); 555 union phy_configure_opts phy_cfg; 556 557 /* Rest the device */ 558 if (dm_gpio_is_valid(&priv->rst_gpio)) 559 dm_gpio_set_value(&priv->rst_gpio, 0); 560 561 /* Set power and maybe external ref clk input */ 562 if (priv->vpcie3v3) { 563 ret = regulator_set_enable(priv->vpcie3v3, true); 564 if (ret) { 565 dev_err(priv->dev, "failed to enable vpcie3v3 (ret=%d)\n", 566 ret); 567 return ret; 568 } 569 } 570 571 if (priv->is_bifurcation) { 572 phy_cfg.pcie.is_bifurcation = true; 573 ret = generic_phy_configure(&priv->phy, &phy_cfg); 574 if (ret) 575 dev_err(dev, "failed to set bifurcation for phy (ret=%d)\n", ret); 576 } 577 578 ret = generic_phy_init(&priv->phy); 579 if (ret) { 580 dev_err(dev, "failed to init phy (ret=%d)\n", ret); 581 return ret; 582 } 583 584 ret = generic_phy_power_on(&priv->phy); 585 if (ret) { 586 dev_err(dev, "failed to power on phy (ret=%d)\n", ret); 587 goto err_exit_phy; 588 } 589 590 ret = reset_deassert_bulk(&priv->rsts); 591 if (ret) { 592 dev_err(dev, "failed to deassert resets (ret=%d)\n", ret); 593 goto err_power_off_phy; 594 } 595 596 ret = clk_enable_bulk(&priv->clks); 597 if (ret) { 598 dev_err(dev, "failed to enable clks (ret=%d)\n", ret); 599 goto err_deassert_bulk; 600 } 601 602 /* LTSSM EN ctrl mode */ 603 val = rk_pcie_readl_apb(priv, PCIE_CLIENT_HOT_RESET_CTRL); 604 val |= PCIE_LTSSM_ENABLE_ENHANCE | (PCIE_LTSSM_ENABLE_ENHANCE << 16); 605 rk_pcie_writel_apb(priv, PCIE_CLIENT_HOT_RESET_CTRL, val); 606 607 /* Set RC mode */ 608 rk_pcie_writel_apb(priv, 0x0, 0xf00040); 609 rk_pcie_setup_host(priv); 610 611 ret = rk_pcie_link_up(priv, priv->gen); 612 if (ret < 0) 613 goto err_link_up; 614 615 return 0; 616 err_link_up: 617 clk_disable_bulk(&priv->clks); 618 err_deassert_bulk: 619 reset_assert_bulk(&priv->rsts); 620 err_power_off_phy: 621 generic_phy_power_off(&priv->phy); 622 err_exit_phy: 623 generic_phy_exit(&priv->phy); 624 return ret; 625 } 626 627 static int rockchip_pcie_parse_dt(struct udevice *dev) 628 { 629 struct rk_pcie *priv = dev_get_priv(dev); 630 u32 max_link_speed; 631 int ret; 632 633 priv->dbi_base = (void *)dev_read_addr_index(dev, 0); 634 if (!priv->dbi_base) 635 return -ENODEV; 636 637 dev_dbg(dev, "DBI address is 0x%p\n", priv->dbi_base); 638 639 priv->apb_base = (void *)dev_read_addr_index(dev, 1); 640 if (!priv->apb_base) 641 return -ENODEV; 642 643 dev_dbg(dev, "APB address is 0x%p\n", priv->apb_base); 644 645 ret = gpio_request_by_name(dev, "reset-gpios", 0, 646 &priv->rst_gpio, GPIOD_IS_OUT); 647 if (ret) { 648 dev_err(dev, "failed to find reset-gpios property\n"); 649 return ret; 650 } 651 652 ret = reset_get_bulk(dev, &priv->rsts); 653 if (ret) { 654 dev_err(dev, "Can't get reset: %d\n", ret); 655 return ret; 656 } 657 658 ret = clk_get_bulk(dev, &priv->clks); 659 if (ret) { 660 dev_err(dev, "Can't get clock: %d\n", ret); 661 return ret; 662 } 663 664 ret = device_get_supply_regulator(dev, "vpcie3v3-supply", 665 &priv->vpcie3v3); 666 if (ret && ret != -ENOENT) { 667 dev_err(dev, "failed to get vpcie3v3 supply (ret=%d)\n", ret); 668 return ret; 669 } 670 671 ret = generic_phy_get_by_index(dev, 0, &priv->phy); 672 if (ret) { 673 dev_err(dev, "failed to get pcie phy (ret=%d)\n", ret); 674 return ret; 675 } 676 677 if (dev_read_bool(dev, "rockchip,bifurcation")) 678 priv->is_bifurcation = true; 679 680 ret = ofnode_read_u32(dev->node, "max-link-speed", &max_link_speed); 681 if (ret < 0 || max_link_speed > 4) 682 priv->gen = 0; 683 else 684 priv->gen = max_link_speed; 685 686 return 0; 687 } 688 689 static int rockchip_pcie_probe(struct udevice *dev) 690 { 691 struct rk_pcie *priv = dev_get_priv(dev); 692 struct udevice *ctlr = pci_get_controller(dev); 693 struct pci_controller *hose = dev_get_uclass_priv(ctlr); 694 int ret; 695 696 priv->first_busno = dev->seq; 697 priv->dev = dev; 698 699 ret = rockchip_pcie_parse_dt(dev); 700 if (ret) 701 return ret; 702 703 ret = rockchip_pcie_init_port(dev); 704 if (ret) 705 return ret; 706 707 dev_info(dev, "PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", 708 dev->seq, rk_pcie_get_link_speed(priv), 709 rk_pcie_get_link_width(priv), 710 hose->first_busno); 711 712 for (ret = 0; ret < hose->region_count; ret++) { 713 if (hose->regions[ret].flags == PCI_REGION_IO) { 714 priv->io.phys_start = hose->regions[ret].phys_start; /* IO base */ 715 priv->io.bus_start = hose->regions[ret].bus_start; /* IO_bus_addr */ 716 priv->io.size = hose->regions[ret].size; /* IO size */ 717 } else if (hose->regions[ret].flags == PCI_REGION_MEM) { 718 priv->mem.phys_start = hose->regions[ret].phys_start; /* MEM base */ 719 priv->mem.bus_start = hose->regions[ret].bus_start; /* MEM_bus_addr */ 720 priv->mem.size = hose->regions[ret].size; /* MEM size */ 721 } else if (hose->regions[ret].flags == PCI_REGION_SYS_MEMORY) { 722 priv->cfg_base = (void *)(priv->io.phys_start - priv->io.size); 723 priv->cfg_size = priv->io.size; 724 } else { 725 dev_err(dev, "invalid flags type!\n"); 726 } 727 } 728 729 dev_dbg(dev, "Config space: [0x%p - 0x%p, size 0x%llx]\n", 730 priv->cfg_base, priv->cfg_base + priv->cfg_size, 731 priv->cfg_size); 732 733 dev_dbg(dev, "IO space: [0x%llx - 0x%llx, size 0x%x]\n", 734 priv->io.phys_start, priv->io.phys_start + priv->io.size, 735 priv->io.size); 736 737 dev_dbg(dev, "IO bus: [0x%x - 0x%x, size 0x%x]\n", 738 priv->io.bus_start, priv->io.bus_start + priv->io.size, 739 priv->io.size); 740 741 dev_dbg(dev, "MEM space: [0x%llx - 0x%llx, size 0x%x]\n", 742 priv->mem.phys_start, priv->mem.phys_start + priv->mem.size, 743 priv->mem.size); 744 745 dev_dbg(dev, "MEM bus: [0x%x - 0x%x, size 0x%x]\n", 746 priv->mem.bus_start, priv->mem.bus_start + priv->mem.size, 747 priv->mem.size); 748 749 rk_pcie_prog_outbound_atu_unroll(priv, PCIE_ATU_REGION_INDEX0, 750 PCIE_ATU_TYPE_MEM, 751 priv->mem.phys_start, 752 priv->mem.bus_start, priv->mem.size); 753 return 0; 754 } 755 756 static const struct dm_pci_ops rockchip_pcie_ops = { 757 .read_config = rockchip_pcie_rd_conf, 758 .write_config = rockchip_pcie_wr_conf, 759 }; 760 761 static const struct udevice_id rockchip_pcie_ids[] = { 762 { .compatible = "rockchip,rk3568-pcie" }, 763 { .compatible = "rockchip,rk3588-pcie" }, 764 { } 765 }; 766 767 U_BOOT_DRIVER(rockchip_pcie) = { 768 .name = "pcie_dw_rockchip", 769 .id = UCLASS_PCI, 770 .of_match = rockchip_pcie_ids, 771 .ops = &rockchip_pcie_ops, 772 .probe = rockchip_pcie_probe, 773 .priv_auto_alloc_size = sizeof(struct rk_pcie), 774 }; 775