1 /* 2 * Marvell PHY drivers 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Copyright 2010-2011 Freescale Semiconductor, Inc. 7 * author Andy Fleming 8 */ 9 #include <config.h> 10 #include <common.h> 11 #include <errno.h> 12 #include <phy.h> 13 14 #define PHY_AUTONEGOTIATE_TIMEOUT 5000 15 16 /* 88E1011 PHY Status Register */ 17 #define MIIM_88E1xxx_PHY_STATUS 0x11 18 #define MIIM_88E1xxx_PHYSTAT_SPEED 0xc000 19 #define MIIM_88E1xxx_PHYSTAT_GBIT 0x8000 20 #define MIIM_88E1xxx_PHYSTAT_100 0x4000 21 #define MIIM_88E1xxx_PHYSTAT_DUPLEX 0x2000 22 #define MIIM_88E1xxx_PHYSTAT_SPDDONE 0x0800 23 #define MIIM_88E1xxx_PHYSTAT_LINK 0x0400 24 25 #define MIIM_88E1xxx_PHY_SCR 0x10 26 #define MIIM_88E1xxx_PHY_MDI_X_AUTO 0x0060 27 28 /* 88E1111 PHY LED Control Register */ 29 #define MIIM_88E1111_PHY_LED_CONTROL 24 30 #define MIIM_88E1111_PHY_LED_DIRECT 0x4100 31 #define MIIM_88E1111_PHY_LED_COMBINE 0x411C 32 33 /* 88E1111 Extended PHY Specific Control Register */ 34 #define MIIM_88E1111_PHY_EXT_CR 0x14 35 #define MIIM_88E1111_RX_DELAY 0x80 36 #define MIIM_88E1111_TX_DELAY 0x2 37 38 /* 88E1111 Extended PHY Specific Status Register */ 39 #define MIIM_88E1111_PHY_EXT_SR 0x1b 40 #define MIIM_88E1111_HWCFG_MODE_MASK 0xf 41 #define MIIM_88E1111_HWCFG_MODE_COPPER_RGMII 0xb 42 #define MIIM_88E1111_HWCFG_MODE_FIBER_RGMII 0x3 43 #define MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK 0x4 44 #define MIIM_88E1111_HWCFG_MODE_COPPER_RTBI 0x9 45 #define MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO 0x8000 46 #define MIIM_88E1111_HWCFG_FIBER_COPPER_RES 0x2000 47 48 #define MIIM_88E1111_COPPER 0 49 #define MIIM_88E1111_FIBER 1 50 51 /* 88E1118 PHY defines */ 52 #define MIIM_88E1118_PHY_PAGE 22 53 #define MIIM_88E1118_PHY_LED_PAGE 3 54 55 /* 88E1121 PHY LED Control Register */ 56 #define MIIM_88E1121_PHY_LED_CTRL 16 57 #define MIIM_88E1121_PHY_LED_PAGE 3 58 #define MIIM_88E1121_PHY_LED_DEF 0x0030 59 60 /* 88E1121 PHY IRQ Enable/Status Register */ 61 #define MIIM_88E1121_PHY_IRQ_EN 18 62 #define MIIM_88E1121_PHY_IRQ_STATUS 19 63 64 #define MIIM_88E1121_PHY_PAGE 22 65 66 /* 88E1145 Extended PHY Specific Control Register */ 67 #define MIIM_88E1145_PHY_EXT_CR 20 68 #define MIIM_M88E1145_RGMII_RX_DELAY 0x0080 69 #define MIIM_M88E1145_RGMII_TX_DELAY 0x0002 70 71 #define MIIM_88E1145_PHY_LED_CONTROL 24 72 #define MIIM_88E1145_PHY_LED_DIRECT 0x4100 73 74 #define MIIM_88E1145_PHY_PAGE 29 75 #define MIIM_88E1145_PHY_CAL_OV 30 76 77 #define MIIM_88E1149_PHY_PAGE 29 78 79 /* 88E1310 PHY defines */ 80 #define MIIM_88E1310_PHY_LED_CTRL 16 81 #define MIIM_88E1310_PHY_IRQ_EN 18 82 #define MIIM_88E1310_PHY_RGMII_CTRL 21 83 #define MIIM_88E1310_PHY_PAGE 22 84 85 /* Marvell 88E1011S */ 86 static int m88e1011s_config(struct phy_device *phydev) 87 { 88 /* Reset and configure the PHY */ 89 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); 90 91 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); 92 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c); 93 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); 94 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0); 95 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); 96 97 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); 98 99 genphy_config_aneg(phydev); 100 101 return 0; 102 } 103 104 /* Parse the 88E1011's status register for speed and duplex 105 * information 106 */ 107 static int m88e1xxx_parse_status(struct phy_device *phydev) 108 { 109 unsigned int speed; 110 unsigned int mii_reg; 111 112 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_STATUS); 113 114 if ((mii_reg & MIIM_88E1xxx_PHYSTAT_LINK) && 115 !(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) { 116 int i = 0; 117 118 puts("Waiting for PHY realtime link"); 119 while (!(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) { 120 /* Timeout reached ? */ 121 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 122 puts(" TIMEOUT !\n"); 123 phydev->link = 0; 124 return -ETIMEDOUT; 125 } 126 127 if ((i++ % 1000) == 0) 128 putc('.'); 129 udelay(1000); 130 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, 131 MIIM_88E1xxx_PHY_STATUS); 132 } 133 puts(" done\n"); 134 udelay(500000); /* another 500 ms (results in faster booting) */ 135 } else { 136 if (mii_reg & MIIM_88E1xxx_PHYSTAT_LINK) 137 phydev->link = 1; 138 else 139 phydev->link = 0; 140 } 141 142 if (mii_reg & MIIM_88E1xxx_PHYSTAT_DUPLEX) 143 phydev->duplex = DUPLEX_FULL; 144 else 145 phydev->duplex = DUPLEX_HALF; 146 147 speed = mii_reg & MIIM_88E1xxx_PHYSTAT_SPEED; 148 149 switch (speed) { 150 case MIIM_88E1xxx_PHYSTAT_GBIT: 151 phydev->speed = SPEED_1000; 152 break; 153 case MIIM_88E1xxx_PHYSTAT_100: 154 phydev->speed = SPEED_100; 155 break; 156 default: 157 phydev->speed = SPEED_10; 158 break; 159 } 160 161 return 0; 162 } 163 164 static int m88e1011s_startup(struct phy_device *phydev) 165 { 166 int ret; 167 168 ret = genphy_update_link(phydev); 169 if (ret) 170 return ret; 171 172 return m88e1xxx_parse_status(phydev); 173 } 174 175 /* Marvell 88E1111S */ 176 static int m88e1111s_config(struct phy_device *phydev) 177 { 178 int reg; 179 180 if (phy_interface_is_rgmii(phydev)) { 181 reg = phy_read(phydev, 182 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR); 183 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) || 184 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)) { 185 reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY); 186 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { 187 reg &= ~MIIM_88E1111_TX_DELAY; 188 reg |= MIIM_88E1111_RX_DELAY; 189 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { 190 reg &= ~MIIM_88E1111_RX_DELAY; 191 reg |= MIIM_88E1111_TX_DELAY; 192 } 193 194 phy_write(phydev, 195 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg); 196 197 reg = phy_read(phydev, 198 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR); 199 200 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK); 201 202 if (reg & MIIM_88E1111_HWCFG_FIBER_COPPER_RES) 203 reg |= MIIM_88E1111_HWCFG_MODE_FIBER_RGMII; 204 else 205 reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RGMII; 206 207 phy_write(phydev, 208 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR, reg); 209 } 210 211 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 212 reg = phy_read(phydev, 213 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR); 214 215 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK); 216 reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK; 217 reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; 218 219 phy_write(phydev, MDIO_DEVAD_NONE, 220 MIIM_88E1111_PHY_EXT_SR, reg); 221 } 222 223 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) { 224 reg = phy_read(phydev, 225 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR); 226 reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY); 227 phy_write(phydev, 228 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg); 229 230 reg = phy_read(phydev, MDIO_DEVAD_NONE, 231 MIIM_88E1111_PHY_EXT_SR); 232 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK | 233 MIIM_88E1111_HWCFG_FIBER_COPPER_RES); 234 reg |= 0x7 | MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; 235 phy_write(phydev, MDIO_DEVAD_NONE, 236 MIIM_88E1111_PHY_EXT_SR, reg); 237 238 /* soft reset */ 239 phy_reset(phydev); 240 241 reg = phy_read(phydev, MDIO_DEVAD_NONE, 242 MIIM_88E1111_PHY_EXT_SR); 243 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK | 244 MIIM_88E1111_HWCFG_FIBER_COPPER_RES); 245 reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RTBI | 246 MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; 247 phy_write(phydev, MDIO_DEVAD_NONE, 248 MIIM_88E1111_PHY_EXT_SR, reg); 249 } 250 251 /* soft reset */ 252 phy_reset(phydev); 253 254 genphy_config_aneg(phydev); 255 genphy_restart_aneg(phydev); 256 257 return 0; 258 } 259 260 /** 261 * m88e1518_phy_writebits - write bits to a register 262 */ 263 void m88e1518_phy_writebits(struct phy_device *phydev, 264 u8 reg_num, u16 offset, u16 len, u16 data) 265 { 266 u16 reg, mask; 267 268 if ((len + offset) >= 16) 269 mask = 0 - (1 << offset); 270 else 271 mask = (1 << (len + offset)) - (1 << offset); 272 273 reg = phy_read(phydev, MDIO_DEVAD_NONE, reg_num); 274 275 reg &= ~mask; 276 reg |= data << offset; 277 278 phy_write(phydev, MDIO_DEVAD_NONE, reg_num, reg); 279 } 280 281 static int m88e1518_config(struct phy_device *phydev) 282 { 283 /* 284 * As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512 285 * /88E1514 Rev A0, Errata Section 3.1 286 */ 287 288 /* EEE initialization */ 289 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x00ff); 290 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x214B); 291 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2144); 292 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x0C28); 293 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2146); 294 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xB233); 295 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x214D); 296 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xCC0C); 297 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2159); 298 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000); 299 300 /* SGMII-to-Copper mode initialization */ 301 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 302 /* Select page 18 */ 303 phy_write(phydev, MDIO_DEVAD_NONE, 22, 18); 304 305 /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */ 306 m88e1518_phy_writebits(phydev, 20, 0, 3, 1); 307 308 /* PHY reset is necessary after changing MODE[2:0] */ 309 m88e1518_phy_writebits(phydev, 20, 15, 1, 1); 310 311 /* Reset page selection */ 312 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0); 313 314 udelay(100); 315 } 316 317 return m88e1111s_config(phydev); 318 } 319 320 /* Marvell 88E1510 */ 321 static int m88e1510_config(struct phy_device *phydev) 322 { 323 /* Select page 3 */ 324 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3); 325 326 /* Enable INTn output on LED[2] */ 327 m88e1518_phy_writebits(phydev, 18, 7, 1, 1); 328 329 /* Configure LEDs */ 330 m88e1518_phy_writebits(phydev, 16, 0, 4, 3); /* LED[0]:0011 (ACT) */ 331 m88e1518_phy_writebits(phydev, 16, 4, 4, 6); /* LED[1]:0110 (LINK) */ 332 333 /* Reset page selection */ 334 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0); 335 336 return m88e1518_config(phydev); 337 } 338 339 /* Marvell 88E1118 */ 340 static int m88e1118_config(struct phy_device *phydev) 341 { 342 /* Change Page Number */ 343 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0002); 344 /* Delay RGMII TX and RX */ 345 phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x1070); 346 /* Change Page Number */ 347 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0003); 348 /* Adjust LED control */ 349 phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x021e); 350 /* Change Page Number */ 351 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); 352 353 return genphy_config_aneg(phydev); 354 } 355 356 static int m88e1118_startup(struct phy_device *phydev) 357 { 358 int ret; 359 360 /* Change Page Number */ 361 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); 362 363 ret = genphy_update_link(phydev); 364 if (ret) 365 return ret; 366 367 return m88e1xxx_parse_status(phydev); 368 } 369 370 /* Marvell 88E1121R */ 371 static int m88e1121_config(struct phy_device *phydev) 372 { 373 int pg; 374 375 /* Configure the PHY */ 376 genphy_config_aneg(phydev); 377 378 /* Switch the page to access the led register */ 379 pg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE); 380 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE, 381 MIIM_88E1121_PHY_LED_PAGE); 382 /* Configure leds */ 383 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_LED_CTRL, 384 MIIM_88E1121_PHY_LED_DEF); 385 /* Restore the page pointer */ 386 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE, pg); 387 388 /* Disable IRQs and de-assert interrupt */ 389 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_EN, 0); 390 phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_STATUS); 391 392 return 0; 393 } 394 395 /* Marvell 88E1145 */ 396 static int m88e1145_config(struct phy_device *phydev) 397 { 398 int reg; 399 400 /* Errata E0, E1 */ 401 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x001b); 402 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0x418f); 403 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x0016); 404 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0xa2da); 405 406 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_SCR, 407 MIIM_88E1xxx_PHY_MDI_X_AUTO); 408 409 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR); 410 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) 411 reg |= MIIM_M88E1145_RGMII_RX_DELAY | 412 MIIM_M88E1145_RGMII_TX_DELAY; 413 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR, reg); 414 415 genphy_config_aneg(phydev); 416 417 phy_reset(phydev); 418 419 return 0; 420 } 421 422 static int m88e1145_startup(struct phy_device *phydev) 423 { 424 int ret; 425 426 ret = genphy_update_link(phydev); 427 if (ret) 428 return ret; 429 430 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_LED_CONTROL, 431 MIIM_88E1145_PHY_LED_DIRECT); 432 return m88e1xxx_parse_status(phydev); 433 } 434 435 /* Marvell 88E1149S */ 436 static int m88e1149_config(struct phy_device *phydev) 437 { 438 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x1f); 439 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c); 440 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x5); 441 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x0); 442 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); 443 444 genphy_config_aneg(phydev); 445 446 phy_reset(phydev); 447 448 return 0; 449 } 450 451 /* Marvell 88E1310 */ 452 static int m88e1310_config(struct phy_device *phydev) 453 { 454 u16 reg; 455 456 /* LED link and activity */ 457 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003); 458 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL); 459 reg = (reg & ~0xf) | 0x1; 460 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL, reg); 461 462 /* Set LED2/INT to INT mode, low active */ 463 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003); 464 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN); 465 reg = (reg & 0x77ff) | 0x0880; 466 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN, reg); 467 468 /* Set RGMII delay */ 469 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0002); 470 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL); 471 reg |= 0x0030; 472 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL, reg); 473 474 /* Ensure to return to page 0 */ 475 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0000); 476 477 return genphy_config_aneg(phydev); 478 } 479 480 static int m88e1680_config(struct phy_device *phydev) 481 { 482 /* 483 * As per Marvell Release Notes - Alaska V 88E1680 Rev A2 484 * Errata Section 4.1 485 */ 486 u16 reg; 487 int res; 488 489 /* Matrix LED mode (not neede if single LED mode is used */ 490 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0004); 491 reg = phy_read(phydev, MDIO_DEVAD_NONE, 27); 492 reg |= (1 << 5); 493 phy_write(phydev, MDIO_DEVAD_NONE, 27, reg); 494 495 /* QSGMII TX amplitude change */ 496 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00fd); 497 phy_write(phydev, MDIO_DEVAD_NONE, 8, 0x0b53); 498 phy_write(phydev, MDIO_DEVAD_NONE, 7, 0x200d); 499 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); 500 501 /* EEE initialization */ 502 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00ff); 503 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xb030); 504 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x215c); 505 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x00fc); 506 phy_write(phydev, MDIO_DEVAD_NONE, 24, 0x888c); 507 phy_write(phydev, MDIO_DEVAD_NONE, 25, 0x888c); 508 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); 509 phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x9140); 510 511 res = genphy_config_aneg(phydev); 512 if (res < 0) 513 return res; 514 515 /* soft reset */ 516 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); 517 reg |= BMCR_RESET; 518 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg); 519 520 return 0; 521 } 522 523 static struct phy_driver M88E1011S_driver = { 524 .name = "Marvell 88E1011S", 525 .uid = 0x1410c60, 526 .mask = 0xffffff0, 527 .features = PHY_GBIT_FEATURES, 528 .config = &m88e1011s_config, 529 .startup = &m88e1011s_startup, 530 .shutdown = &genphy_shutdown, 531 }; 532 533 static struct phy_driver M88E1111S_driver = { 534 .name = "Marvell 88E1111S", 535 .uid = 0x1410cc0, 536 .mask = 0xffffff0, 537 .features = PHY_GBIT_FEATURES, 538 .config = &m88e1111s_config, 539 .startup = &m88e1011s_startup, 540 .shutdown = &genphy_shutdown, 541 }; 542 543 static struct phy_driver M88E1118_driver = { 544 .name = "Marvell 88E1118", 545 .uid = 0x1410e10, 546 .mask = 0xffffff0, 547 .features = PHY_GBIT_FEATURES, 548 .config = &m88e1118_config, 549 .startup = &m88e1118_startup, 550 .shutdown = &genphy_shutdown, 551 }; 552 553 static struct phy_driver M88E1118R_driver = { 554 .name = "Marvell 88E1118R", 555 .uid = 0x1410e40, 556 .mask = 0xffffff0, 557 .features = PHY_GBIT_FEATURES, 558 .config = &m88e1118_config, 559 .startup = &m88e1118_startup, 560 .shutdown = &genphy_shutdown, 561 }; 562 563 static struct phy_driver M88E1121R_driver = { 564 .name = "Marvell 88E1121R", 565 .uid = 0x1410cb0, 566 .mask = 0xffffff0, 567 .features = PHY_GBIT_FEATURES, 568 .config = &m88e1121_config, 569 .startup = &genphy_startup, 570 .shutdown = &genphy_shutdown, 571 }; 572 573 static struct phy_driver M88E1145_driver = { 574 .name = "Marvell 88E1145", 575 .uid = 0x1410cd0, 576 .mask = 0xffffff0, 577 .features = PHY_GBIT_FEATURES, 578 .config = &m88e1145_config, 579 .startup = &m88e1145_startup, 580 .shutdown = &genphy_shutdown, 581 }; 582 583 static struct phy_driver M88E1149S_driver = { 584 .name = "Marvell 88E1149S", 585 .uid = 0x1410ca0, 586 .mask = 0xffffff0, 587 .features = PHY_GBIT_FEATURES, 588 .config = &m88e1149_config, 589 .startup = &m88e1011s_startup, 590 .shutdown = &genphy_shutdown, 591 }; 592 593 static struct phy_driver M88E1510_driver = { 594 .name = "Marvell 88E1510", 595 .uid = 0x1410dd0, 596 .mask = 0xfffffff, 597 .features = PHY_GBIT_FEATURES, 598 .config = &m88e1510_config, 599 .startup = &m88e1011s_startup, 600 .shutdown = &genphy_shutdown, 601 }; 602 603 /* 604 * This supports: 605 * 88E1518, uid 0x1410dd1 606 * 88E1512, uid 0x1410dd4 607 */ 608 static struct phy_driver M88E1518_driver = { 609 .name = "Marvell 88E1518", 610 .uid = 0x1410dd0, 611 .mask = 0xffffffa, 612 .features = PHY_GBIT_FEATURES, 613 .config = &m88e1518_config, 614 .startup = &m88e1011s_startup, 615 .shutdown = &genphy_shutdown, 616 }; 617 618 static struct phy_driver M88E1310_driver = { 619 .name = "Marvell 88E1310", 620 .uid = 0x01410e90, 621 .mask = 0xffffff0, 622 .features = PHY_GBIT_FEATURES, 623 .config = &m88e1310_config, 624 .startup = &m88e1011s_startup, 625 .shutdown = &genphy_shutdown, 626 }; 627 628 static struct phy_driver M88E1680_driver = { 629 .name = "Marvell 88E1680", 630 .uid = 0x1410ed0, 631 .mask = 0xffffff0, 632 .features = PHY_GBIT_FEATURES, 633 .config = &m88e1680_config, 634 .startup = &genphy_startup, 635 .shutdown = &genphy_shutdown, 636 }; 637 638 int phy_marvell_init(void) 639 { 640 phy_register(&M88E1310_driver); 641 phy_register(&M88E1149S_driver); 642 phy_register(&M88E1145_driver); 643 phy_register(&M88E1121R_driver); 644 phy_register(&M88E1118_driver); 645 phy_register(&M88E1118R_driver); 646 phy_register(&M88E1111S_driver); 647 phy_register(&M88E1011S_driver); 648 phy_register(&M88E1510_driver); 649 phy_register(&M88E1518_driver); 650 phy_register(&M88E1680_driver); 651 652 return 0; 653 } 654