xref: /rk3399_rockchip-uboot/drivers/net/dwc_eth_qos.h (revision fc99c7ab0358f90c533f152c5a2e7a6bb1f4e7bf)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2020
4  */
5 
6 #ifndef _DWC_ETH_QOS_H
7 #define _DWC_ETH_QOS_H
8 
9 #include <reset.h>
10 
11 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED		0
12 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB		2
13 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV		1
14 
15 #define EQOS_MAC_MDIO_ADDRESS_CR_20_35			2
16 #define EQOS_MAC_MDIO_ADDRESS_CR_250_300		5
17 
18 
19 struct eqos_config {
20 	bool reg_access_always_ok;
21 	int mdio_wait;
22 	int swr_wait;
23 	int config_mac;
24 	int config_mac_mdio;
25 	struct eqos_ops *ops;
26 };
27 
28 struct eqos_ops {
29 	void (*eqos_inval_desc)(void *desc);
30 	void (*eqos_flush_desc)(void *desc);
31 	void (*eqos_inval_buffer)(void *buf, size_t size);
32 	void (*eqos_flush_buffer)(void *buf, size_t size);
33 	int (*eqos_probe_resources)(struct udevice *dev);
34 	int (*eqos_remove_resources)(struct udevice *dev);
35 	int (*eqos_stop_resets)(struct udevice *dev);
36 	int (*eqos_start_resets)(struct udevice *dev);
37 	void (*eqos_stop_clks)(struct udevice *dev);
38 	int (*eqos_start_clks)(struct udevice *dev);
39 	int (*eqos_calibrate_pads)(struct udevice *dev);
40 	int (*eqos_disable_calibration)(struct udevice *dev);
41 	int (*eqos_set_tx_clk_speed)(struct udevice *dev);
42 	ulong (*eqos_get_tick_clk_rate)(struct udevice *dev);
43 	phy_interface_t (*eqos_get_interface)(struct udevice *dev);
44 };
45 
46 struct eqos_priv {
47 	struct udevice *dev;
48 	const struct eqos_config *config;
49 	fdt_addr_t regs;
50 	struct eqos_mac_regs *mac_regs;
51 	struct eqos_mtl_regs *mtl_regs;
52 	struct eqos_dma_regs *dma_regs;
53 	struct eqos_tegra186_regs *tegra186_regs;
54 	struct reset_ctl reset_ctl;
55 	struct gpio_desc phy_reset_gpio;
56 	u32 reset_delays[3];
57 	struct clk clk_master_bus;
58 	struct clk clk_rx;
59 	struct clk clk_ptp_ref;
60 	struct clk clk_tx;
61 	struct clk clk_ck;
62 	struct clk clk_slave_bus;
63 	struct mii_dev *mii;
64 	struct phy_device *phy;
65 	int phyaddr;
66 	u32 max_speed;
67 	void *descs;
68 	struct eqos_desc *tx_descs;
69 	struct eqos_desc *rx_descs;
70 	int tx_desc_idx, rx_desc_idx;
71 	void *tx_dma_buf;
72 	void *rx_dma_buf;
73 	void *rx_pkt;
74 	bool started;
75 	bool reg_access_ok;
76 };
77 
78 int eqos_init(struct udevice *dev);
79 void eqos_enable(struct udevice *dev);
80 int eqos_probe(struct udevice *dev);
81 void eqos_stop(struct udevice *dev);
82 int eqos_send(struct udevice *dev, void *packet, int length);
83 int eqos_recv(struct udevice *dev, int flags, uchar **packetp);
84 int eqos_free_pkt(struct udevice *dev, uchar *packet, int length);
85 int eqos_write_hwaddr(struct udevice *dev);
86 
87 extern struct eqos_ops eqos_rockchip_ops;
88 
89 #endif
90