1 /* 2 * Copyright (c) 2016, NVIDIA CORPORATION. 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 * 6 * Portions based on U-Boot's rtl8169.c. 7 */ 8 9 /* 10 * This driver supports the Synopsys Designware Ethernet QOS (Quality Of 11 * Service) IP block. The IP supports multiple options for bus type, clocking/ 12 * reset structure, and feature list. 13 * 14 * The driver is written such that generic core logic is kept separate from 15 * configuration-specific logic. Code that interacts with configuration- 16 * specific resources is split out into separate functions to avoid polluting 17 * common code. If/when this driver is enhanced to support multiple 18 * configurations, the core code should be adapted to call all configuration- 19 * specific functions through function pointers, with the definition of those 20 * function pointers being supplied by struct udevice_id eqos_ids[]'s .data 21 * field. 22 * 23 * The following configurations are currently supported: 24 * tegra186: 25 * NVIDIA's Tegra186 chip. This configuration uses an AXI master/DMA bus, an 26 * AHB slave/register bus, contains the DMA, MTL, and MAC sub-blocks, and 27 * supports a single RGMII PHY. This configuration also has SW control over 28 * all clock and reset signals to the HW block. 29 */ 30 #include <common.h> 31 #include <clk.h> 32 #include <dm.h> 33 #include <errno.h> 34 #include <memalign.h> 35 #include <miiphy.h> 36 #include <net.h> 37 #include <netdev.h> 38 #include <phy.h> 39 #include <reset.h> 40 #include <wait_bit.h> 41 #include <asm/io.h> 42 #include <eth_phy.h> 43 #ifdef CONFIG_ARCH_IMX8M 44 #include <asm/arch/clock.h> 45 #include <asm/mach-imx/sys_proto.h> 46 #endif 47 #include "dwc_eth_qos.h" 48 49 /* Core registers */ 50 51 #define EQOS_MAC_REGS_BASE 0x000 52 struct eqos_mac_regs { 53 uint32_t configuration; /* 0x000 */ 54 uint32_t unused_004[(0x070 - 0x004) / 4]; /* 0x004 */ 55 uint32_t q0_tx_flow_ctrl; /* 0x070 */ 56 uint32_t unused_070[(0x090 - 0x074) / 4]; /* 0x074 */ 57 uint32_t rx_flow_ctrl; /* 0x090 */ 58 uint32_t unused_094; /* 0x094 */ 59 uint32_t txq_prty_map0; /* 0x098 */ 60 uint32_t unused_09c; /* 0x09c */ 61 uint32_t rxq_ctrl0; /* 0x0a0 */ 62 uint32_t unused_0a4; /* 0x0a4 */ 63 uint32_t rxq_ctrl2; /* 0x0a8 */ 64 uint32_t unused_0ac[(0x0dc - 0x0ac) / 4]; /* 0x0ac */ 65 uint32_t us_tic_counter; /* 0x0dc */ 66 uint32_t unused_0e0[(0x11c - 0x0e0) / 4]; /* 0x0e0 */ 67 uint32_t hw_feature0; /* 0x11c */ 68 uint32_t hw_feature1; /* 0x120 */ 69 uint32_t hw_feature2; /* 0x124 */ 70 uint32_t unused_128[(0x200 - 0x128) / 4]; /* 0x128 */ 71 uint32_t mdio_address; /* 0x200 */ 72 uint32_t mdio_data; /* 0x204 */ 73 uint32_t unused_208[(0x300 - 0x208) / 4]; /* 0x208 */ 74 uint32_t address0_high; /* 0x300 */ 75 uint32_t address0_low; /* 0x304 */ 76 }; 77 78 #define EQOS_MAC_CONFIGURATION_GPSLCE BIT(23) 79 #define EQOS_MAC_CONFIGURATION_CST BIT(21) 80 #define EQOS_MAC_CONFIGURATION_ACS BIT(20) 81 #define EQOS_MAC_CONFIGURATION_WD BIT(19) 82 #define EQOS_MAC_CONFIGURATION_JD BIT(17) 83 #define EQOS_MAC_CONFIGURATION_JE BIT(16) 84 #define EQOS_MAC_CONFIGURATION_PS BIT(15) 85 #define EQOS_MAC_CONFIGURATION_FES BIT(14) 86 #define EQOS_MAC_CONFIGURATION_DM BIT(13) 87 #define EQOS_MAC_CONFIGURATION_LM BIT(12) 88 #define EQOS_MAC_CONFIGURATION_TE BIT(1) 89 #define EQOS_MAC_CONFIGURATION_RE BIT(0) 90 91 #define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16 92 #define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_MASK 0xffff 93 #define EQOS_MAC_Q0_TX_FLOW_CTRL_TFE BIT(1) 94 95 #define EQOS_MAC_RX_FLOW_CTRL_RFE BIT(0) 96 97 #define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT 0 98 #define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK 0xff 99 100 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT 0 101 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK 3 102 103 #define EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT 0 104 #define EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK 0xff 105 106 #define EQOS_MAC_HW_FEATURE0_MMCSEL_SHIFT 8 107 #define EQOS_MAC_HW_FEATURE0_HDSEL_SHIFT 2 108 #define EQOS_MAC_HW_FEATURE0_GMIISEL_SHIFT 1 109 #define EQOS_MAC_HW_FEATURE0_MIISEL_SHIFT 0 110 111 #define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT 6 112 #define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK 0x1f 113 #define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT 0 114 #define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK 0x1f 115 116 #define EQOS_MAC_HW_FEATURE3_ASP_SHIFT 28 117 #define EQOS_MAC_HW_FEATURE3_ASP_MASK 0x3 118 119 #define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21 120 #define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT 16 121 #define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8 122 #define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4) 123 #define EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT 2 124 #define EQOS_MAC_MDIO_ADDRESS_GOC_READ 3 125 #define EQOS_MAC_MDIO_ADDRESS_GOC_WRITE 1 126 #define EQOS_MAC_MDIO_ADDRESS_C45E BIT(1) 127 #define EQOS_MAC_MDIO_ADDRESS_GB BIT(0) 128 129 #define EQOS_MAC_MDIO_DATA_GD_MASK 0xffff 130 131 #define EQOS_MTL_REGS_BASE 0xd00 132 struct eqos_mtl_regs { 133 uint32_t txq0_operation_mode; /* 0xd00 */ 134 uint32_t unused_d04; /* 0xd04 */ 135 uint32_t txq0_debug; /* 0xd08 */ 136 uint32_t unused_d0c[(0xd18 - 0xd0c) / 4]; /* 0xd0c */ 137 uint32_t txq0_quantum_weight; /* 0xd18 */ 138 uint32_t unused_d1c[(0xd30 - 0xd1c) / 4]; /* 0xd1c */ 139 uint32_t rxq0_operation_mode; /* 0xd30 */ 140 uint32_t unused_d34; /* 0xd34 */ 141 uint32_t rxq0_debug; /* 0xd38 */ 142 }; 143 144 #define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT 16 145 #define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK 0x1ff 146 #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT 2 147 #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK 3 148 #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED 2 149 #define EQOS_MTL_TXQ0_OPERATION_MODE_TSF BIT(1) 150 #define EQOS_MTL_TXQ0_OPERATION_MODE_FTQ BIT(0) 151 152 #define EQOS_MTL_TXQ0_DEBUG_TXQSTS BIT(4) 153 #define EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT 1 154 #define EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK 3 155 156 #define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT 20 157 #define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK 0x3ff 158 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT 14 159 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK 0x3f 160 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT 8 161 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK 0x3f 162 #define EQOS_MTL_RXQ0_OPERATION_MODE_EHFC BIT(7) 163 #define EQOS_MTL_RXQ0_OPERATION_MODE_RSF BIT(5) 164 #define EQOS_MTL_RXQ0_OPERATION_MODE_FEP BIT(4) 165 #define EQOS_MTL_RXQ0_OPERATION_MODE_FUP BIT(3) 166 167 #define EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT 16 168 #define EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK 0x7fff 169 #define EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT 4 170 #define EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK 3 171 172 #define EQOS_DMA_REGS_BASE 0x1000 173 struct eqos_dma_regs { 174 uint32_t mode; /* 0x1000 */ 175 uint32_t sysbus_mode; /* 0x1004 */ 176 uint32_t unused_1008[(0x1100 - 0x1008) / 4]; /* 0x1008 */ 177 uint32_t ch0_control; /* 0x1100 */ 178 uint32_t ch0_tx_control; /* 0x1104 */ 179 uint32_t ch0_rx_control; /* 0x1108 */ 180 uint32_t unused_110c; /* 0x110c */ 181 uint32_t ch0_txdesc_list_haddress; /* 0x1110 */ 182 uint32_t ch0_txdesc_list_address; /* 0x1114 */ 183 uint32_t ch0_rxdesc_list_haddress; /* 0x1118 */ 184 uint32_t ch0_rxdesc_list_address; /* 0x111c */ 185 uint32_t ch0_txdesc_tail_pointer; /* 0x1120 */ 186 uint32_t unused_1124; /* 0x1124 */ 187 uint32_t ch0_rxdesc_tail_pointer; /* 0x1128 */ 188 uint32_t ch0_txdesc_ring_length; /* 0x112c */ 189 uint32_t ch0_rxdesc_ring_length; /* 0x1130 */ 190 }; 191 192 #define EQOS_DMA_MODE_SWR BIT(0) 193 194 #define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT 16 195 #define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK 0xf 196 #define EQOS_DMA_SYSBUS_MODE_EAME BIT(11) 197 #define EQOS_DMA_SYSBUS_MODE_BLEN16 BIT(3) 198 #define EQOS_DMA_SYSBUS_MODE_BLEN8 BIT(2) 199 #define EQOS_DMA_SYSBUS_MODE_BLEN4 BIT(1) 200 201 #define EQOS_DMA_CH0_CONTROL_PBLX8 BIT(16) 202 203 #define EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT 16 204 #define EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK 0x3f 205 #define EQOS_DMA_CH0_TX_CONTROL_OSP BIT(4) 206 #define EQOS_DMA_CH0_TX_CONTROL_ST BIT(0) 207 208 #define EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT 16 209 #define EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK 0x3f 210 #define EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT 1 211 #define EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK 0x3fff 212 #define EQOS_DMA_CH0_RX_CONTROL_SR BIT(0) 213 214 /* These registers are Tegra186-specific */ 215 #define EQOS_TEGRA186_REGS_BASE 0x8800 216 struct eqos_tegra186_regs { 217 uint32_t sdmemcomppadctrl; /* 0x8800 */ 218 uint32_t auto_cal_config; /* 0x8804 */ 219 uint32_t unused_8808; /* 0x8808 */ 220 uint32_t auto_cal_status; /* 0x880c */ 221 }; 222 223 #define EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD BIT(31) 224 225 #define EQOS_AUTO_CAL_CONFIG_START BIT(31) 226 #define EQOS_AUTO_CAL_CONFIG_ENABLE BIT(29) 227 228 #define EQOS_AUTO_CAL_STATUS_ACTIVE BIT(31) 229 230 /* Descriptors */ 231 232 #define EQOS_DESCRIPTOR_WORDS 4 233 #define EQOS_DESCRIPTOR_SIZE (EQOS_DESCRIPTOR_WORDS * 4) 234 /* We assume ARCH_DMA_MINALIGN >= 16; 16 is the EQOS HW minimum */ 235 #define EQOS_DESCRIPTOR_ALIGN ARCH_DMA_MINALIGN 236 #define EQOS_DESCRIPTORS_TX 4 237 #define EQOS_DESCRIPTORS_RX 4 238 #define EQOS_DESCRIPTORS_NUM (EQOS_DESCRIPTORS_TX + EQOS_DESCRIPTORS_RX) 239 #define EQOS_DESCRIPTORS_SIZE ALIGN(EQOS_DESCRIPTORS_NUM * \ 240 EQOS_DESCRIPTOR_SIZE, ARCH_DMA_MINALIGN) 241 #define EQOS_BUFFER_ALIGN ARCH_DMA_MINALIGN 242 #define EQOS_MAX_PACKET_SIZE ALIGN(1568, ARCH_DMA_MINALIGN) 243 #define EQOS_RX_BUFFER_SIZE (EQOS_DESCRIPTORS_RX * EQOS_MAX_PACKET_SIZE) 244 245 /* 246 * Warn if the cache-line size is larger than the descriptor size. In such 247 * cases the driver will likely fail because the CPU needs to flush the cache 248 * when requeuing RX buffers, therefore descriptors written by the hardware 249 * may be discarded. Architectures with full IO coherence, such as x86, do not 250 * experience this issue, and hence are excluded from this condition. 251 * 252 * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause 253 * the driver to allocate descriptors from a pool of non-cached memory. 254 */ 255 #if EQOS_DESCRIPTOR_SIZE < ARCH_DMA_MINALIGN 256 #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \ 257 !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_X86) 258 #warning Cache line size is larger than descriptor size 259 #endif 260 #endif 261 262 struct eqos_desc { 263 u32 des0; 264 u32 des1; 265 u32 des2; 266 u32 des3; 267 }; 268 269 #define EQOS_DESC3_OWN BIT(31) 270 #define EQOS_DESC3_FD BIT(29) 271 #define EQOS_DESC3_LD BIT(28) 272 #define EQOS_DESC3_BUF1V BIT(24) 273 274 /* 275 * TX and RX descriptors are 16 bytes. This causes problems with the cache 276 * maintenance on CPUs where the cache-line size exceeds the size of these 277 * descriptors. What will happen is that when the driver receives a packet 278 * it will be immediately requeued for the hardware to reuse. The CPU will 279 * therefore need to flush the cache-line containing the descriptor, which 280 * will cause all other descriptors in the same cache-line to be flushed 281 * along with it. If one of those descriptors had been written to by the 282 * device those changes (and the associated packet) will be lost. 283 * 284 * To work around this, we make use of non-cached memory if available. If 285 * descriptors are mapped uncached there's no need to manually flush them 286 * or invalidate them. 287 * 288 * Note that this only applies to descriptors. The packet data buffers do 289 * not have the same constraints since they are 1536 bytes large, so they 290 * are unlikely to share cache-lines. 291 */ 292 static void *eqos_alloc_descs(unsigned int num) 293 { 294 #ifdef CONFIG_SYS_NONCACHED_MEMORY 295 return (void *)noncached_alloc(EQOS_DESCRIPTORS_SIZE, 296 EQOS_DESCRIPTOR_ALIGN); 297 #else 298 return memalign(EQOS_DESCRIPTOR_ALIGN, EQOS_DESCRIPTORS_SIZE); 299 #endif 300 } 301 302 static void eqos_free_descs(void *descs) 303 { 304 #ifdef CONFIG_SYS_NONCACHED_MEMORY 305 /* FIXME: noncached_alloc() has no opposite */ 306 #else 307 free(descs); 308 #endif 309 } 310 311 #ifdef CONFIG_QOS_FULL 312 static void eqos_inval_desc_tegra186(void *desc) 313 { 314 #ifndef CONFIG_SYS_NONCACHED_MEMORY 315 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); 316 unsigned long end = ALIGN(start + EQOS_DESCRIPTOR_SIZE, 317 ARCH_DMA_MINALIGN); 318 319 invalidate_dcache_range(start, end); 320 #endif 321 } 322 #endif 323 324 static void eqos_inval_desc_generic(void *desc) 325 { 326 #ifndef CONFIG_SYS_NONCACHED_MEMORY 327 unsigned long start = rounddown((unsigned long)desc, ARCH_DMA_MINALIGN); 328 unsigned long end = roundup((unsigned long)desc + EQOS_DESCRIPTOR_SIZE, 329 ARCH_DMA_MINALIGN); 330 331 invalidate_dcache_range(start, end); 332 #endif 333 } 334 335 #ifdef CONFIG_QOS_FULL 336 static void eqos_flush_desc_tegra186(void *desc) 337 { 338 #ifndef CONFIG_SYS_NONCACHED_MEMORY 339 flush_cache((unsigned long)desc, EQOS_DESCRIPTOR_SIZE); 340 #endif 341 } 342 #endif 343 344 static void eqos_flush_desc_generic(void *desc) 345 { 346 #ifndef CONFIG_SYS_NONCACHED_MEMORY 347 unsigned long start = rounddown((unsigned long)desc, ARCH_DMA_MINALIGN); 348 unsigned long end = roundup((unsigned long)desc + EQOS_DESCRIPTOR_SIZE, 349 ARCH_DMA_MINALIGN); 350 351 flush_dcache_range(start, end); 352 #endif 353 } 354 355 #ifdef CONFIG_QOS_FULL 356 static void eqos_inval_buffer_tegra186(void *buf, size_t size) 357 { 358 unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1); 359 unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN); 360 361 invalidate_dcache_range(start, end); 362 } 363 #endif 364 365 static void eqos_inval_buffer_generic(void *buf, size_t size) 366 { 367 unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN); 368 unsigned long end = roundup((unsigned long)buf + size, 369 ARCH_DMA_MINALIGN); 370 371 invalidate_dcache_range(start, end); 372 } 373 374 #ifdef CONFIG_QOS_FULL 375 static void eqos_flush_buffer_tegra186(void *buf, size_t size) 376 { 377 flush_cache((unsigned long)buf, size); 378 } 379 #endif 380 381 static void eqos_flush_buffer_generic(void *buf, size_t size) 382 { 383 unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN); 384 unsigned long end = roundup((unsigned long)buf + size, 385 ARCH_DMA_MINALIGN); 386 387 flush_dcache_range(start, end); 388 } 389 390 static int eqos_mdio_wait_idle(struct eqos_priv *eqos) 391 { 392 return wait_for_bit_le32(&eqos->mac_regs->mdio_address, 393 EQOS_MAC_MDIO_ADDRESS_GB, false, 394 1000000, true); 395 } 396 397 static int eqos_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad, 398 int mdio_reg) 399 { 400 struct eqos_priv *eqos = bus->priv; 401 u32 val; 402 int ret; 403 404 debug("%s(dev=%p, addr=%x, reg=%d):\n", __func__, eqos->dev, mdio_addr, 405 mdio_reg); 406 407 ret = eqos_mdio_wait_idle(eqos); 408 if (ret) { 409 pr_err("MDIO not idle at entry"); 410 return ret; 411 } 412 413 val = readl(&eqos->mac_regs->mdio_address); 414 val &= EQOS_MAC_MDIO_ADDRESS_SKAP | 415 EQOS_MAC_MDIO_ADDRESS_C45E; 416 val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) | 417 (mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) | 418 (eqos->config->config_mac_mdio << 419 EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) | 420 (EQOS_MAC_MDIO_ADDRESS_GOC_READ << 421 EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) | 422 EQOS_MAC_MDIO_ADDRESS_GB; 423 writel(val, &eqos->mac_regs->mdio_address); 424 425 udelay(eqos->config->mdio_wait); 426 427 ret = eqos_mdio_wait_idle(eqos); 428 if (ret) { 429 pr_err("MDIO read didn't complete"); 430 return ret; 431 } 432 433 val = readl(&eqos->mac_regs->mdio_data); 434 val &= EQOS_MAC_MDIO_DATA_GD_MASK; 435 436 debug("%s: val=%x\n", __func__, val); 437 438 return val; 439 } 440 441 static int eqos_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad, 442 int mdio_reg, u16 mdio_val) 443 { 444 struct eqos_priv *eqos = bus->priv; 445 u32 val; 446 int ret; 447 448 debug("%s(dev=%p, addr=%x, reg=%d, val=%x):\n", __func__, eqos->dev, 449 mdio_addr, mdio_reg, mdio_val); 450 451 ret = eqos_mdio_wait_idle(eqos); 452 if (ret) { 453 pr_err("MDIO not idle at entry"); 454 return ret; 455 } 456 457 writel(mdio_val, &eqos->mac_regs->mdio_data); 458 459 val = readl(&eqos->mac_regs->mdio_address); 460 val &= EQOS_MAC_MDIO_ADDRESS_SKAP | 461 EQOS_MAC_MDIO_ADDRESS_C45E; 462 val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) | 463 (mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) | 464 (eqos->config->config_mac_mdio << 465 EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) | 466 (EQOS_MAC_MDIO_ADDRESS_GOC_WRITE << 467 EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) | 468 EQOS_MAC_MDIO_ADDRESS_GB; 469 writel(val, &eqos->mac_regs->mdio_address); 470 471 udelay(eqos->config->mdio_wait); 472 473 ret = eqos_mdio_wait_idle(eqos); 474 if (ret) { 475 pr_err("MDIO read didn't complete"); 476 return ret; 477 } 478 479 return 0; 480 } 481 482 #ifdef CONFIG_QOS_FULL 483 static int eqos_start_clks_tegra186(struct udevice *dev) 484 { 485 #ifdef CONFIG_CLK 486 struct eqos_priv *eqos = dev_get_priv(dev); 487 int ret; 488 489 debug("%s(dev=%p):\n", __func__, dev); 490 491 ret = clk_enable(&eqos->clk_slave_bus); 492 if (ret < 0) { 493 pr_err("clk_enable(clk_slave_bus) failed: %d", ret); 494 goto err; 495 } 496 497 ret = clk_enable(&eqos->clk_master_bus); 498 if (ret < 0) { 499 pr_err("clk_enable(clk_master_bus) failed: %d", ret); 500 goto err_disable_clk_slave_bus; 501 } 502 503 ret = clk_enable(&eqos->clk_rx); 504 if (ret < 0) { 505 pr_err("clk_enable(clk_rx) failed: %d", ret); 506 goto err_disable_clk_master_bus; 507 } 508 509 ret = clk_enable(&eqos->clk_ptp_ref); 510 if (ret < 0) { 511 pr_err("clk_enable(clk_ptp_ref) failed: %d", ret); 512 goto err_disable_clk_rx; 513 } 514 515 ret = clk_set_rate(&eqos->clk_ptp_ref, 125 * 1000 * 1000); 516 if (ret < 0) { 517 pr_err("clk_set_rate(clk_ptp_ref) failed: %d", ret); 518 goto err_disable_clk_ptp_ref; 519 } 520 521 ret = clk_enable(&eqos->clk_tx); 522 if (ret < 0) { 523 pr_err("clk_enable(clk_tx) failed: %d", ret); 524 goto err_disable_clk_ptp_ref; 525 } 526 #endif 527 528 debug("%s: OK\n", __func__); 529 return 0; 530 531 #ifdef CONFIG_CLK 532 err_disable_clk_ptp_ref: 533 clk_disable(&eqos->clk_ptp_ref); 534 err_disable_clk_rx: 535 clk_disable(&eqos->clk_rx); 536 err_disable_clk_master_bus: 537 clk_disable(&eqos->clk_master_bus); 538 err_disable_clk_slave_bus: 539 clk_disable(&eqos->clk_slave_bus); 540 err: 541 debug("%s: FAILED: %d\n", __func__, ret); 542 return ret; 543 #endif 544 } 545 546 static int eqos_start_clks_stm32(struct udevice *dev) 547 { 548 #ifdef CONFIG_CLK 549 struct eqos_priv *eqos = dev_get_priv(dev); 550 int ret; 551 552 debug("%s(dev=%p):\n", __func__, dev); 553 554 ret = clk_enable(&eqos->clk_master_bus); 555 if (ret < 0) { 556 pr_err("clk_enable(clk_master_bus) failed: %d", ret); 557 goto err; 558 } 559 560 if (clk_valid(&eqos->clk_rx)) { 561 ret = clk_enable(&eqos->clk_rx); 562 if (ret < 0) { 563 pr_err("clk_enable(clk_rx) failed: %d", ret); 564 goto err_disable_clk_master_bus; 565 } 566 } 567 568 if (clk_valid(&eqos->clk_tx)) { 569 ret = clk_enable(&eqos->clk_tx); 570 if (ret < 0) { 571 pr_err("clk_enable(clk_tx) failed: %d", ret); 572 goto err_disable_clk_rx; 573 } 574 } 575 576 if (clk_valid(&eqos->clk_ck)) { 577 ret = clk_enable(&eqos->clk_ck); 578 if (ret < 0) { 579 pr_err("clk_enable(clk_ck) failed: %d", ret); 580 goto err_disable_clk_tx; 581 } 582 } 583 #endif 584 585 debug("%s: OK\n", __func__); 586 return 0; 587 588 #ifdef CONFIG_CLK 589 err_disable_clk_tx: 590 if (clk_valid(&eqos->clk_tx)) 591 clk_disable(&eqos->clk_tx); 592 err_disable_clk_rx: 593 if (clk_valid(&eqos->clk_rx)) 594 clk_disable(&eqos->clk_rx); 595 err_disable_clk_master_bus: 596 clk_disable(&eqos->clk_master_bus); 597 err: 598 debug("%s: FAILED: %d\n", __func__, ret); 599 return ret; 600 #endif 601 } 602 603 static int eqos_start_clks_imx(struct udevice *dev) 604 { 605 return 0; 606 } 607 608 static void eqos_stop_clks_tegra186(struct udevice *dev) 609 { 610 #ifdef CONFIG_CLK 611 struct eqos_priv *eqos = dev_get_priv(dev); 612 613 debug("%s(dev=%p):\n", __func__, dev); 614 615 clk_disable(&eqos->clk_tx); 616 clk_disable(&eqos->clk_ptp_ref); 617 clk_disable(&eqos->clk_rx); 618 clk_disable(&eqos->clk_master_bus); 619 clk_disable(&eqos->clk_slave_bus); 620 #endif 621 622 debug("%s: OK\n", __func__); 623 } 624 625 static void eqos_stop_clks_stm32(struct udevice *dev) 626 { 627 #ifdef CONFIG_CLK 628 struct eqos_priv *eqos = dev_get_priv(dev); 629 630 debug("%s(dev=%p):\n", __func__, dev); 631 632 if (clk_valid(&eqos->clk_tx)) 633 clk_disable(&eqos->clk_tx); 634 if (clk_valid(&eqos->clk_rx)) 635 clk_disable(&eqos->clk_rx); 636 clk_disable(&eqos->clk_master_bus); 637 if (clk_valid(&eqos->clk_ck)) 638 clk_disable(&eqos->clk_ck); 639 #endif 640 641 debug("%s: OK\n", __func__); 642 } 643 644 static void eqos_stop_clks_imx(struct udevice *dev) 645 { 646 /* empty */ 647 } 648 649 static int eqos_start_resets_tegra186(struct udevice *dev) 650 { 651 struct eqos_priv *eqos = dev_get_priv(dev); 652 int ret; 653 654 debug("%s(dev=%p):\n", __func__, dev); 655 656 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1); 657 if (ret < 0) { 658 pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d", ret); 659 return ret; 660 } 661 662 udelay(2); 663 664 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0); 665 if (ret < 0) { 666 pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d", ret); 667 return ret; 668 } 669 670 ret = reset_assert(&eqos->reset_ctl); 671 if (ret < 0) { 672 pr_err("reset_assert() failed: %d", ret); 673 return ret; 674 } 675 676 udelay(2); 677 678 ret = reset_deassert(&eqos->reset_ctl); 679 if (ret < 0) { 680 pr_err("reset_deassert() failed: %d", ret); 681 return ret; 682 } 683 684 debug("%s: OK\n", __func__); 685 return 0; 686 } 687 #endif 688 689 static int eqos_start_resets_stm32(struct udevice *dev) 690 { 691 struct eqos_priv *eqos = dev_get_priv(dev); 692 int ret; 693 694 debug("%s(dev=%p):\n", __func__, dev); 695 if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) { 696 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0); 697 if (ret < 0) { 698 pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d", 699 ret); 700 return ret; 701 } 702 703 udelay(eqos->reset_delays[0]); 704 705 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1); 706 if (ret < 0) { 707 pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d", 708 ret); 709 return ret; 710 } 711 712 udelay(eqos->reset_delays[1]); 713 714 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0); 715 if (ret < 0) { 716 pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d", 717 ret); 718 return ret; 719 } 720 721 udelay(eqos->reset_delays[2]); 722 } 723 debug("%s: OK\n", __func__); 724 725 return 0; 726 } 727 728 #ifdef CONFIG_QOS_FULL 729 static int eqos_start_resets_imx(struct udevice *dev) 730 { 731 return 0; 732 } 733 734 static int eqos_stop_resets_tegra186(struct udevice *dev) 735 { 736 struct eqos_priv *eqos = dev_get_priv(dev); 737 738 reset_assert(&eqos->reset_ctl); 739 dm_gpio_set_value(&eqos->phy_reset_gpio, 1); 740 741 return 0; 742 } 743 #endif 744 745 static int eqos_stop_resets_stm32(struct udevice *dev) 746 { 747 struct eqos_priv *eqos = dev_get_priv(dev); 748 int ret; 749 750 if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) { 751 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1); 752 if (ret < 0) { 753 pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d", 754 ret); 755 return ret; 756 } 757 } 758 759 return 0; 760 } 761 762 #ifdef CONFIG_QOS_FULL 763 static int eqos_stop_resets_imx(struct udevice *dev) 764 { 765 return 0; 766 } 767 768 static int eqos_calibrate_pads_tegra186(struct udevice *dev) 769 { 770 struct eqos_priv *eqos = dev_get_priv(dev); 771 int ret; 772 773 debug("%s(dev=%p):\n", __func__, dev); 774 775 setbits_le32(&eqos->tegra186_regs->sdmemcomppadctrl, 776 EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD); 777 778 udelay(1); 779 780 setbits_le32(&eqos->tegra186_regs->auto_cal_config, 781 EQOS_AUTO_CAL_CONFIG_START | EQOS_AUTO_CAL_CONFIG_ENABLE); 782 783 ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status, 784 EQOS_AUTO_CAL_STATUS_ACTIVE, true, 10, false); 785 if (ret) { 786 pr_err("calibrate didn't start"); 787 goto failed; 788 } 789 790 ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status, 791 EQOS_AUTO_CAL_STATUS_ACTIVE, false, 10, false); 792 if (ret) { 793 pr_err("calibrate didn't finish"); 794 goto failed; 795 } 796 797 ret = 0; 798 799 failed: 800 clrbits_le32(&eqos->tegra186_regs->sdmemcomppadctrl, 801 EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD); 802 803 debug("%s: returns %d\n", __func__, ret); 804 805 return ret; 806 } 807 808 static int eqos_disable_calibration_tegra186(struct udevice *dev) 809 { 810 struct eqos_priv *eqos = dev_get_priv(dev); 811 812 debug("%s(dev=%p):\n", __func__, dev); 813 814 clrbits_le32(&eqos->tegra186_regs->auto_cal_config, 815 EQOS_AUTO_CAL_CONFIG_ENABLE); 816 817 return 0; 818 } 819 820 static ulong eqos_get_tick_clk_rate_tegra186(struct udevice *dev) 821 { 822 #ifdef CONFIG_CLK 823 struct eqos_priv *eqos = dev_get_priv(dev); 824 825 return clk_get_rate(&eqos->clk_slave_bus); 826 #else 827 return 0; 828 #endif 829 } 830 #endif 831 832 static ulong eqos_get_tick_clk_rate_stm32(struct udevice *dev) 833 { 834 #ifdef CONFIG_CLK 835 struct eqos_priv *eqos = dev_get_priv(dev); 836 837 return clk_get_rate(&eqos->clk_master_bus); 838 #else 839 return 0; 840 #endif 841 } 842 843 #ifdef CONFIG_QOS_FULL 844 __weak u32 imx_get_eqos_csr_clk(void) 845 { 846 return 100 * 1000000; 847 } 848 __weak int imx_eqos_txclk_set_rate(unsigned long rate) 849 { 850 return 0; 851 } 852 853 static ulong eqos_get_tick_clk_rate_imx(struct udevice *dev) 854 { 855 return imx_get_eqos_csr_clk(); 856 } 857 #endif 858 859 static int eqos_calibrate_pads_stm32(struct udevice *dev) 860 { 861 return 0; 862 } 863 864 #ifdef CONFIG_QOS_FULL 865 static int eqos_calibrate_pads_imx(struct udevice *dev) 866 { 867 return 0; 868 } 869 #endif 870 871 static int eqos_disable_calibration_stm32(struct udevice *dev) 872 { 873 return 0; 874 } 875 876 #ifdef CONFIG_QOS_FULL 877 static int eqos_disable_calibration_imx(struct udevice *dev) 878 { 879 return 0; 880 } 881 #endif 882 883 static int eqos_set_full_duplex(struct udevice *dev) 884 { 885 struct eqos_priv *eqos = dev_get_priv(dev); 886 887 debug("%s(dev=%p):\n", __func__, dev); 888 889 setbits_le32(&eqos->mac_regs->configuration, EQOS_MAC_CONFIGURATION_DM); 890 891 return 0; 892 } 893 894 static int eqos_set_half_duplex(struct udevice *dev) 895 { 896 struct eqos_priv *eqos = dev_get_priv(dev); 897 898 debug("%s(dev=%p):\n", __func__, dev); 899 900 clrbits_le32(&eqos->mac_regs->configuration, EQOS_MAC_CONFIGURATION_DM); 901 902 /* WAR: Flush TX queue when switching to half-duplex */ 903 setbits_le32(&eqos->mtl_regs->txq0_operation_mode, 904 EQOS_MTL_TXQ0_OPERATION_MODE_FTQ); 905 906 return 0; 907 } 908 909 static int eqos_set_gmii_speed(struct udevice *dev) 910 { 911 struct eqos_priv *eqos = dev_get_priv(dev); 912 913 debug("%s(dev=%p):\n", __func__, dev); 914 915 clrbits_le32(&eqos->mac_regs->configuration, 916 EQOS_MAC_CONFIGURATION_PS | EQOS_MAC_CONFIGURATION_FES); 917 918 return 0; 919 } 920 921 static int eqos_set_mii_speed_100(struct udevice *dev) 922 { 923 struct eqos_priv *eqos = dev_get_priv(dev); 924 925 debug("%s(dev=%p):\n", __func__, dev); 926 927 setbits_le32(&eqos->mac_regs->configuration, 928 EQOS_MAC_CONFIGURATION_PS | EQOS_MAC_CONFIGURATION_FES); 929 930 return 0; 931 } 932 933 static int eqos_set_mii_speed_10(struct udevice *dev) 934 { 935 struct eqos_priv *eqos = dev_get_priv(dev); 936 937 debug("%s(dev=%p):\n", __func__, dev); 938 939 clrsetbits_le32(&eqos->mac_regs->configuration, 940 EQOS_MAC_CONFIGURATION_FES, EQOS_MAC_CONFIGURATION_PS); 941 942 return 0; 943 } 944 945 #ifdef CONFIG_QOS_FULL 946 static int eqos_set_tx_clk_speed_tegra186(struct udevice *dev) 947 { 948 #ifdef CONFIG_CLK 949 struct eqos_priv *eqos = dev_get_priv(dev); 950 ulong rate; 951 int ret; 952 953 debug("%s(dev=%p):\n", __func__, dev); 954 955 switch (eqos->phy->speed) { 956 case SPEED_1000: 957 rate = 125 * 1000 * 1000; 958 break; 959 case SPEED_100: 960 rate = 25 * 1000 * 1000; 961 break; 962 case SPEED_10: 963 rate = 2.5 * 1000 * 1000; 964 break; 965 default: 966 pr_err("invalid speed %d", eqos->phy->speed); 967 return -EINVAL; 968 } 969 970 ret = clk_set_rate(&eqos->clk_tx, rate); 971 if (ret < 0) { 972 pr_err("clk_set_rate(tx_clk, %lu) failed: %d", rate, ret); 973 return ret; 974 } 975 #endif 976 977 return 0; 978 } 979 #endif 980 981 static int eqos_set_tx_clk_speed_stm32(struct udevice *dev) 982 { 983 return 0; 984 } 985 986 #ifdef CONFIG_QOS_FULL 987 static int eqos_set_tx_clk_speed_imx(struct udevice *dev) 988 { 989 struct eqos_priv *eqos = dev_get_priv(dev); 990 ulong rate; 991 int ret; 992 993 debug("%s(dev=%p):\n", __func__, dev); 994 995 switch (eqos->phy->speed) { 996 case SPEED_1000: 997 rate = 125 * 1000 * 1000; 998 break; 999 case SPEED_100: 1000 rate = 25 * 1000 * 1000; 1001 break; 1002 case SPEED_10: 1003 rate = 2.5 * 1000 * 1000; 1004 break; 1005 default: 1006 pr_err("invalid speed %d", eqos->phy->speed); 1007 return -EINVAL; 1008 } 1009 1010 ret = imx_eqos_txclk_set_rate(rate); 1011 if (ret < 0) { 1012 pr_err("imx (tx_clk, %lu) failed: %d", rate, ret); 1013 return ret; 1014 } 1015 1016 return 0; 1017 } 1018 #endif 1019 1020 static int eqos_adjust_link(struct udevice *dev) 1021 { 1022 struct eqos_priv *eqos = dev_get_priv(dev); 1023 int ret; 1024 bool en_calibration; 1025 1026 debug("%s(dev=%p):\n", __func__, dev); 1027 1028 if (eqos->phy->duplex) 1029 ret = eqos_set_full_duplex(dev); 1030 else 1031 ret = eqos_set_half_duplex(dev); 1032 if (ret < 0) { 1033 pr_err("eqos_set_*_duplex() failed: %d", ret); 1034 return ret; 1035 } 1036 1037 switch (eqos->phy->speed) { 1038 case SPEED_1000: 1039 en_calibration = true; 1040 ret = eqos_set_gmii_speed(dev); 1041 break; 1042 case SPEED_100: 1043 en_calibration = true; 1044 ret = eqos_set_mii_speed_100(dev); 1045 break; 1046 case SPEED_10: 1047 en_calibration = false; 1048 ret = eqos_set_mii_speed_10(dev); 1049 break; 1050 default: 1051 pr_err("invalid speed %d", eqos->phy->speed); 1052 return -EINVAL; 1053 } 1054 if (ret < 0) { 1055 pr_err("eqos_set_*mii_speed*() failed: %d", ret); 1056 return ret; 1057 } 1058 1059 if (en_calibration) { 1060 ret = eqos->config->ops->eqos_calibrate_pads(dev); 1061 if (ret < 0) { 1062 pr_err("eqos_calibrate_pads() failed: %d", 1063 ret); 1064 return ret; 1065 } 1066 } else { 1067 ret = eqos->config->ops->eqos_disable_calibration(dev); 1068 if (ret < 0) { 1069 pr_err("eqos_disable_calibration() failed: %d", 1070 ret); 1071 return ret; 1072 } 1073 } 1074 ret = eqos->config->ops->eqos_set_tx_clk_speed(dev); 1075 if (ret < 0) { 1076 pr_err("eqos_set_tx_clk_speed() failed: %d", ret); 1077 return ret; 1078 } 1079 1080 return 0; 1081 } 1082 1083 int eqos_write_hwaddr(struct udevice *dev) 1084 { 1085 struct eth_pdata *plat = dev_get_platdata(dev); 1086 struct eqos_priv *eqos = dev_get_priv(dev); 1087 uint32_t val; 1088 1089 /* 1090 * This function may be called before start() or after stop(). At that 1091 * time, on at least some configurations of the EQoS HW, all clocks to 1092 * the EQoS HW block will be stopped, and a reset signal applied. If 1093 * any register access is attempted in this state, bus timeouts or CPU 1094 * hangs may occur. This check prevents that. 1095 * 1096 * A simple solution to this problem would be to not implement 1097 * write_hwaddr(), since start() always writes the MAC address into HW 1098 * anyway. However, it is desirable to implement write_hwaddr() to 1099 * support the case of SW that runs subsequent to U-Boot which expects 1100 * the MAC address to already be programmed into the EQoS registers, 1101 * which must happen irrespective of whether the U-Boot user (or 1102 * scripts) actually made use of the EQoS device, and hence 1103 * irrespective of whether start() was ever called. 1104 * 1105 * Note that this requirement by subsequent SW is not valid for 1106 * Tegra186, and is likely not valid for any non-PCI instantiation of 1107 * the EQoS HW block. This function is implemented solely as 1108 * future-proofing with the expectation the driver will eventually be 1109 * ported to some system where the expectation above is true. 1110 */ 1111 if (!eqos->config->reg_access_always_ok && !eqos->reg_access_ok) 1112 return 0; 1113 1114 /* Update the MAC address */ 1115 val = (plat->enetaddr[5] << 8) | 1116 (plat->enetaddr[4]); 1117 writel(val, &eqos->mac_regs->address0_high); 1118 val = (plat->enetaddr[3] << 24) | 1119 (plat->enetaddr[2] << 16) | 1120 (plat->enetaddr[1] << 8) | 1121 (plat->enetaddr[0]); 1122 writel(val, &eqos->mac_regs->address0_low); 1123 1124 return 0; 1125 } 1126 1127 #ifdef CONFIG_QOS_FULL 1128 static int eqos_read_rom_hwaddr(struct udevice *dev) 1129 { 1130 struct eth_pdata *pdata = dev_get_platdata(dev); 1131 1132 #ifdef CONFIG_ARCH_IMX8M 1133 imx_get_mac_from_fuse(dev->req_seq, pdata->enetaddr); 1134 #endif 1135 return !is_valid_ethaddr(pdata->enetaddr); 1136 } 1137 #endif 1138 1139 int eqos_init(struct udevice *dev) 1140 { 1141 struct eqos_priv *eqos = dev_get_priv(dev); 1142 int ret = 0, limit = 10; 1143 ulong rate; 1144 u32 val; 1145 1146 debug("%s(dev=%p):\n", __func__, dev); 1147 1148 if (eqos->config->ops->eqos_start_clks) { 1149 ret = eqos->config->ops->eqos_start_clks(dev); 1150 if (ret < 0) { 1151 pr_err("eqos_start_clks() failed: %d", ret); 1152 goto err; 1153 } 1154 } 1155 1156 if (!eqos->mii_reseted) { 1157 ret = eqos->config->ops->eqos_start_resets(dev); 1158 if (ret < 0) { 1159 pr_err("eqos_start_resets() failed: %d", ret); 1160 goto err_stop_clks; 1161 } 1162 1163 eqos->mii_reseted = true; 1164 udelay(10); 1165 } 1166 1167 eqos->reg_access_ok = true; 1168 1169 /* DMA SW reset */ 1170 val = readl(&eqos->dma_regs->mode); 1171 val |= EQOS_DMA_MODE_SWR; 1172 writel(val, &eqos->dma_regs->mode); 1173 while (limit--) { 1174 if (!(readl(&eqos->dma_regs->mode) & EQOS_DMA_MODE_SWR)) 1175 break; 1176 mdelay(10); 1177 } 1178 1179 if (limit < 0) { 1180 pr_err("EQOS_DMA_MODE_SWR stuck"); 1181 goto err_stop_resets; 1182 } 1183 1184 ret = eqos->config->ops->eqos_calibrate_pads(dev); 1185 if (ret < 0) { 1186 pr_err("eqos_calibrate_pads() failed: %d", ret); 1187 goto err_stop_resets; 1188 } 1189 rate = eqos->config->ops->eqos_get_tick_clk_rate(dev); 1190 1191 val = (rate / 1000000) - 1; 1192 writel(val, &eqos->mac_regs->us_tic_counter); 1193 1194 /* 1195 * if PHY was already connected and configured, 1196 * don't need to reconnect/reconfigure again 1197 */ 1198 if (!eqos->phy) { 1199 int addr = -1; 1200 #ifdef CONFIG_DM_ETH_PHY 1201 addr = eth_phy_get_addr(dev); 1202 #endif 1203 #ifdef DWC_NET_PHYADDR 1204 addr = DWC_NET_PHYADDR; 1205 #endif 1206 eqos->phy = phy_connect(eqos->mii, addr, dev, 1207 eqos->config->ops->eqos_get_interface(dev)); 1208 if (!eqos->phy) { 1209 pr_err("phy_connect() failed"); 1210 goto err_stop_resets; 1211 } 1212 1213 if (eqos->max_speed) { 1214 ret = phy_set_supported(eqos->phy, eqos->max_speed); 1215 if (ret) { 1216 pr_err("phy_set_supported() failed: %d", ret); 1217 goto err_shutdown_phy; 1218 } 1219 } 1220 1221 ret = phy_config(eqos->phy); 1222 if (ret < 0) { 1223 pr_err("phy_config() failed: %d", ret); 1224 goto err_shutdown_phy; 1225 } 1226 } 1227 1228 ret = phy_startup(eqos->phy); 1229 if (ret < 0) { 1230 pr_err("phy_startup() failed: %d", ret); 1231 goto err_shutdown_phy; 1232 } 1233 1234 if (!eqos->phy->link) { 1235 pr_err("No link"); 1236 goto err_shutdown_phy; 1237 } 1238 1239 ret = eqos_adjust_link(dev); 1240 if (ret < 0) { 1241 pr_err("eqos_adjust_link() failed: %d", ret); 1242 goto err_shutdown_phy; 1243 } 1244 1245 debug("%s: OK\n", __func__); 1246 return 0; 1247 1248 err_shutdown_phy: 1249 phy_shutdown(eqos->phy); 1250 err_stop_resets: 1251 eqos->config->ops->eqos_stop_resets(dev); 1252 eqos->mii_reseted = false; 1253 err_stop_clks: 1254 if (eqos->config->ops->eqos_stop_clks) 1255 eqos->config->ops->eqos_stop_clks(dev); 1256 err: 1257 pr_err("FAILED: %d", ret); 1258 return ret; 1259 } 1260 1261 void eqos_enable(struct udevice *dev) 1262 { 1263 struct eqos_priv *eqos = dev_get_priv(dev); 1264 u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl; 1265 ulong last_rx_desc; 1266 int i; 1267 1268 eqos->tx_desc_idx = 0; 1269 eqos->rx_desc_idx = 0; 1270 1271 /* Configure MTL */ 1272 writel(0x60, &eqos->mtl_regs->txq0_quantum_weight - 0x100); 1273 1274 /* Enable Store and Forward mode for TX */ 1275 /* Program Tx operating mode */ 1276 setbits_le32(&eqos->mtl_regs->txq0_operation_mode, 1277 EQOS_MTL_TXQ0_OPERATION_MODE_TSF | 1278 (EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED << 1279 EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT)); 1280 1281 /* Transmit Queue weight */ 1282 writel(0x10, &eqos->mtl_regs->txq0_quantum_weight); 1283 1284 /* Enable Store and Forward mode for RX, since no jumbo frame */ 1285 setbits_le32(&eqos->mtl_regs->rxq0_operation_mode, 1286 EQOS_MTL_RXQ0_OPERATION_MODE_RSF | 1287 EQOS_MTL_RXQ0_OPERATION_MODE_FEP | 1288 EQOS_MTL_RXQ0_OPERATION_MODE_FUP); 1289 1290 /* Transmit/Receive queue fifo size; use all RAM for 1 queue */ 1291 val = readl(&eqos->mac_regs->hw_feature1); 1292 tx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT) & 1293 EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK; 1294 rx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) & 1295 EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK; 1296 1297 /* 1298 * r/tx_fifo_sz is encoded as log2(n / 128). Undo that by shifting. 1299 * r/tqs is encoded as (n / 256) - 1. 1300 */ 1301 tqs = (128 << tx_fifo_sz) / 256 - 1; 1302 rqs = (128 << rx_fifo_sz) / 256 - 1; 1303 1304 clrsetbits_le32(&eqos->mtl_regs->txq0_operation_mode, 1305 EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK << 1306 EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT, 1307 tqs << EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT); 1308 clrsetbits_le32(&eqos->mtl_regs->rxq0_operation_mode, 1309 EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK << 1310 EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT, 1311 rqs << EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT); 1312 1313 /* Flow control used only if each channel gets 4KB or more FIFO */ 1314 if (rqs >= ((4096 / 256) - 1)) { 1315 u32 rfd, rfa; 1316 1317 setbits_le32(&eqos->mtl_regs->rxq0_operation_mode, 1318 EQOS_MTL_RXQ0_OPERATION_MODE_EHFC); 1319 1320 /* 1321 * Set Threshold for Activating Flow Contol space for min 2 1322 * frames ie, (1500 * 1) = 1500 bytes. 1323 * 1324 * Set Threshold for Deactivating Flow Contol for space of 1325 * min 1 frame (frame size 1500bytes) in receive fifo 1326 */ 1327 if (rqs == ((4096 / 256) - 1)) { 1328 /* 1329 * This violates the above formula because of FIFO size 1330 * limit therefore overflow may occur inspite of this. 1331 */ 1332 rfd = 0x3; /* Full-3K */ 1333 rfa = 0x1; /* Full-1.5K */ 1334 } else if (rqs == ((8192 / 256) - 1)) { 1335 rfd = 0x6; /* Full-4K */ 1336 rfa = 0xa; /* Full-6K */ 1337 } else if (rqs == ((16384 / 256) - 1)) { 1338 rfd = 0x6; /* Full-4K */ 1339 rfa = 0x12; /* Full-10K */ 1340 } else { 1341 rfd = 0x6; /* Full-4K */ 1342 rfa = 0x1E; /* Full-16K */ 1343 } 1344 1345 clrsetbits_le32(&eqos->mtl_regs->rxq0_operation_mode, 1346 (EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK << 1347 EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) | 1348 (EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK << 1349 EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT), 1350 (rfd << 1351 EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) | 1352 (rfa << 1353 EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT)); 1354 } 1355 1356 /* Configure MAC */ 1357 1358 clrsetbits_le32(&eqos->mac_regs->rxq_ctrl0, 1359 EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK << 1360 EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT, 1361 eqos->config->config_mac << 1362 EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT); 1363 1364 clrsetbits_le32(&eqos->mac_regs->rxq_ctrl0, 1365 EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK << 1366 EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT, 1367 0x2 << 1368 EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT); 1369 1370 /* Multicast and Broadcast Queue Enable */ 1371 setbits_le32(&eqos->mac_regs->unused_0a4, 1372 0x00100000); 1373 /* enable promise mode */ 1374 setbits_le32(&eqos->mac_regs->unused_004[1], 1375 0x1); 1376 1377 /* Set TX flow control parameters */ 1378 /* Set Pause Time */ 1379 setbits_le32(&eqos->mac_regs->q0_tx_flow_ctrl, 1380 0xffff << EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT); 1381 /* Assign priority for TX flow control */ 1382 clrbits_le32(&eqos->mac_regs->txq_prty_map0, 1383 EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK << 1384 EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT); 1385 /* Assign priority for RX flow control */ 1386 clrbits_le32(&eqos->mac_regs->rxq_ctrl2, 1387 EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK << 1388 EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT); 1389 /* Enable flow control */ 1390 setbits_le32(&eqos->mac_regs->q0_tx_flow_ctrl, 1391 EQOS_MAC_Q0_TX_FLOW_CTRL_TFE); 1392 setbits_le32(&eqos->mac_regs->rx_flow_ctrl, 1393 EQOS_MAC_RX_FLOW_CTRL_RFE); 1394 1395 clrsetbits_le32(&eqos->mac_regs->configuration, 1396 EQOS_MAC_CONFIGURATION_GPSLCE | 1397 EQOS_MAC_CONFIGURATION_WD | 1398 EQOS_MAC_CONFIGURATION_JD | 1399 EQOS_MAC_CONFIGURATION_JE, 1400 EQOS_MAC_CONFIGURATION_CST | 1401 EQOS_MAC_CONFIGURATION_ACS); 1402 1403 eqos_write_hwaddr(dev); 1404 1405 /* Configure DMA */ 1406 1407 /* Enable OSP mode */ 1408 setbits_le32(&eqos->dma_regs->ch0_tx_control, 1409 EQOS_DMA_CH0_TX_CONTROL_OSP); 1410 1411 /* RX buffer size. Must be a multiple of bus width */ 1412 clrsetbits_le32(&eqos->dma_regs->ch0_rx_control, 1413 EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK << 1414 EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT, 1415 EQOS_MAX_PACKET_SIZE << 1416 EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT); 1417 1418 setbits_le32(&eqos->dma_regs->ch0_control, 1419 EQOS_DMA_CH0_CONTROL_PBLX8); 1420 1421 /* 1422 * Burst length must be < 1/2 FIFO size. 1423 * FIFO size in tqs is encoded as (n / 256) - 1. 1424 * Each burst is n * 8 (PBLX8) * 16 (AXI width) == 128 bytes. 1425 * Half of n * 256 is n * 128, so pbl == tqs, modulo the -1. 1426 */ 1427 pbl = tqs + 1; 1428 if (pbl > 32) 1429 pbl = 32; 1430 clrsetbits_le32(&eqos->dma_regs->ch0_tx_control, 1431 EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK << 1432 EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT, 1433 pbl << EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT); 1434 1435 clrsetbits_le32(&eqos->dma_regs->ch0_rx_control, 1436 EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK << 1437 EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT, 1438 8 << EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT); 1439 1440 /* DMA performance configuration */ 1441 val = (2 << EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT) | 1442 EQOS_DMA_SYSBUS_MODE_EAME | EQOS_DMA_SYSBUS_MODE_BLEN16 | 1443 EQOS_DMA_SYSBUS_MODE_BLEN8 | EQOS_DMA_SYSBUS_MODE_BLEN4; 1444 writel(val, &eqos->dma_regs->sysbus_mode); 1445 1446 /* Set up descriptors */ 1447 1448 memset(eqos->descs, 0, EQOS_DESCRIPTORS_SIZE); 1449 for (i = 0; i < EQOS_DESCRIPTORS_RX; i++) { 1450 struct eqos_desc *rx_desc = &(eqos->rx_descs[i]); 1451 rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf + 1452 (i * EQOS_MAX_PACKET_SIZE)); 1453 rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V; 1454 mb(); 1455 eqos->config->ops->eqos_flush_desc(rx_desc); 1456 eqos->config->ops->eqos_inval_buffer(eqos->rx_dma_buf + 1457 (i * EQOS_MAX_PACKET_SIZE), 1458 EQOS_MAX_PACKET_SIZE); 1459 } 1460 1461 writel(0, &eqos->dma_regs->ch0_txdesc_list_haddress); 1462 writel((ulong)eqos->tx_descs, &eqos->dma_regs->ch0_txdesc_list_address); 1463 writel(EQOS_DESCRIPTORS_TX - 1, 1464 &eqos->dma_regs->ch0_txdesc_ring_length); 1465 1466 writel(0, &eqos->dma_regs->ch0_rxdesc_list_haddress); 1467 writel((ulong)eqos->rx_descs, &eqos->dma_regs->ch0_rxdesc_list_address); 1468 writel(EQOS_DESCRIPTORS_RX - 1, 1469 &eqos->dma_regs->ch0_rxdesc_ring_length); 1470 1471 /* Enable everything */ 1472 setbits_le32(&eqos->dma_regs->ch0_tx_control, 1473 EQOS_DMA_CH0_TX_CONTROL_ST); 1474 setbits_le32(&eqos->dma_regs->ch0_rx_control, 1475 EQOS_DMA_CH0_RX_CONTROL_SR); 1476 setbits_le32(&eqos->mac_regs->configuration, 1477 EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE); 1478 1479 /* TX tail pointer not written until we need to TX a packet */ 1480 /* 1481 * Point RX tail pointer at last descriptor. Ideally, we'd point at the 1482 * first descriptor, implying all descriptors were available. However, 1483 * that's not distinguishable from none of the descriptors being 1484 * available. 1485 */ 1486 last_rx_desc = (ulong)&(eqos->rx_descs[(EQOS_DESCRIPTORS_RX - 1)]); 1487 writel(last_rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer); 1488 1489 eqos->started = true; 1490 } 1491 1492 static int __maybe_unused eqos_start(struct udevice *dev) 1493 { 1494 int ret; 1495 1496 ret = eqos_init(dev); 1497 if (ret) 1498 return ret; 1499 1500 eqos_enable(dev); 1501 1502 return 0; 1503 } 1504 1505 void eqos_stop(struct udevice *dev) 1506 { 1507 struct eqos_priv *eqos = dev_get_priv(dev); 1508 int i; 1509 1510 debug("%s(dev=%p):\n", __func__, dev); 1511 1512 if (!eqos->started) 1513 return; 1514 eqos->started = false; 1515 eqos->reg_access_ok = false; 1516 1517 /* Disable TX DMA */ 1518 clrbits_le32(&eqos->dma_regs->ch0_tx_control, 1519 EQOS_DMA_CH0_TX_CONTROL_ST); 1520 1521 /* Wait for TX all packets to drain out of MTL */ 1522 for (i = 0; i < 1000000; i++) { 1523 u32 val = readl(&eqos->mtl_regs->txq0_debug); 1524 u32 trcsts = (val >> EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT) & 1525 EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK; 1526 u32 txqsts = val & EQOS_MTL_TXQ0_DEBUG_TXQSTS; 1527 if ((trcsts != 1) && (!txqsts)) 1528 break; 1529 } 1530 1531 /* Turn off MAC TX and RX */ 1532 clrbits_le32(&eqos->mac_regs->configuration, 1533 EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE); 1534 1535 /* Wait for all RX packets to drain out of MTL */ 1536 for (i = 0; i < 1000000; i++) { 1537 u32 val = readl(&eqos->mtl_regs->rxq0_debug); 1538 u32 prxq = (val >> EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT) & 1539 EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK; 1540 u32 rxqsts = (val >> EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT) & 1541 EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK; 1542 if ((!prxq) && (!rxqsts)) 1543 break; 1544 } 1545 1546 /* Turn off RX DMA */ 1547 clrbits_le32(&eqos->dma_regs->ch0_rx_control, 1548 EQOS_DMA_CH0_RX_CONTROL_SR); 1549 1550 if (eqos->phy) { 1551 phy_shutdown(eqos->phy); 1552 } 1553 if (eqos->config->ops->eqos_stop_clks) 1554 eqos->config->ops->eqos_stop_clks(dev); 1555 1556 debug("%s: OK\n", __func__); 1557 } 1558 1559 int eqos_send(struct udevice *dev, void *packet, int length) 1560 { 1561 struct eqos_priv *eqos = dev_get_priv(dev); 1562 struct eqos_desc *tx_desc; 1563 int i; 1564 1565 debug("%s(dev=%p, packet=%p, length=%d):\n", __func__, dev, packet, 1566 length); 1567 1568 memcpy(eqos->tx_dma_buf, packet, length); 1569 eqos->config->ops->eqos_flush_buffer(eqos->tx_dma_buf, length); 1570 1571 tx_desc = &(eqos->tx_descs[eqos->tx_desc_idx]); 1572 eqos->tx_desc_idx++; 1573 eqos->tx_desc_idx %= EQOS_DESCRIPTORS_TX; 1574 1575 tx_desc->des0 = (ulong)eqos->tx_dma_buf; 1576 tx_desc->des1 = 0; 1577 tx_desc->des2 = length; 1578 /* 1579 * Make sure that if HW sees the _OWN write below, it will see all the 1580 * writes to the rest of the descriptor too. 1581 */ 1582 mb(); 1583 tx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_FD | EQOS_DESC3_LD | length; 1584 eqos->config->ops->eqos_flush_desc(tx_desc); 1585 1586 writel((ulong)(&(eqos->tx_descs[eqos->tx_desc_idx])), 1587 &eqos->dma_regs->ch0_txdesc_tail_pointer); 1588 1589 for (i = 0; i < 1000000; i++) { 1590 eqos->config->ops->eqos_inval_desc(tx_desc); 1591 if (!(readl(&tx_desc->des3) & EQOS_DESC3_OWN)) 1592 return 0; 1593 udelay(1); 1594 } 1595 1596 debug("%s: TX timeout\n", __func__); 1597 1598 return -ETIMEDOUT; 1599 } 1600 1601 int eqos_recv(struct udevice *dev, int flags, uchar **packetp) 1602 { 1603 struct eqos_priv *eqos = dev_get_priv(dev); 1604 struct eqos_desc *rx_desc; 1605 int length; 1606 1607 debug("%s(dev=%p, flags=%x):\n", __func__, dev, flags); 1608 1609 rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]); 1610 eqos->config->ops->eqos_inval_desc(rx_desc); 1611 if (rx_desc->des3 & EQOS_DESC3_OWN) { 1612 debug("%s: RX packet not available\n", __func__); 1613 return -EAGAIN; 1614 } 1615 1616 *packetp = eqos->rx_dma_buf + 1617 (eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE); 1618 length = rx_desc->des3 & 0x7fff; 1619 debug("%s: *packetp=%p, length=%d\n", __func__, *packetp, length); 1620 1621 eqos->config->ops->eqos_inval_buffer(*packetp, length); 1622 1623 return length; 1624 } 1625 1626 int eqos_free_pkt(struct udevice *dev, uchar *packet, int length) 1627 { 1628 struct eqos_priv *eqos = dev_get_priv(dev); 1629 uchar *packet_expected; 1630 struct eqos_desc *rx_desc; 1631 1632 debug("%s(packet=%p, length=%d)\n", __func__, packet, length); 1633 1634 packet_expected = eqos->rx_dma_buf + 1635 (eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE); 1636 if (packet != packet_expected) { 1637 debug("%s: Unexpected packet (expected %p)\n", __func__, 1638 packet_expected); 1639 return -EINVAL; 1640 } 1641 1642 eqos->config->ops->eqos_inval_buffer(packet, length); 1643 1644 rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]); 1645 1646 rx_desc->des0 = 0; 1647 mb(); 1648 eqos->config->ops->eqos_flush_desc(rx_desc); 1649 eqos->config->ops->eqos_inval_buffer(packet, length); 1650 rx_desc->des0 = (u32)(ulong)packet; 1651 rx_desc->des1 = 0; 1652 rx_desc->des2 = 0; 1653 /* 1654 * Make sure that if HW sees the _OWN write below, it will see all the 1655 * writes to the rest of the descriptor too. 1656 */ 1657 mb(); 1658 rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V; 1659 eqos->config->ops->eqos_flush_desc(rx_desc); 1660 1661 writel((ulong)rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer); 1662 1663 eqos->rx_desc_idx++; 1664 eqos->rx_desc_idx %= EQOS_DESCRIPTORS_RX; 1665 1666 return 0; 1667 } 1668 1669 static int eqos_probe_resources_core(struct udevice *dev) 1670 { 1671 struct eqos_priv *eqos = dev_get_priv(dev); 1672 int ret; 1673 1674 debug("%s(dev=%p):\n", __func__, dev); 1675 1676 eqos->descs = eqos_alloc_descs(EQOS_DESCRIPTORS_TX + 1677 EQOS_DESCRIPTORS_RX); 1678 if (!eqos->descs) { 1679 debug("%s: eqos_alloc_descs() failed\n", __func__); 1680 ret = -ENOMEM; 1681 goto err; 1682 } 1683 eqos->tx_descs = (struct eqos_desc *)eqos->descs; 1684 eqos->rx_descs = (eqos->tx_descs + EQOS_DESCRIPTORS_TX); 1685 debug("%s: tx_descs=%p, rx_descs=%p\n", __func__, eqos->tx_descs, 1686 eqos->rx_descs); 1687 1688 eqos->tx_dma_buf = memalign(EQOS_BUFFER_ALIGN, EQOS_MAX_PACKET_SIZE); 1689 if (!eqos->tx_dma_buf) { 1690 debug("%s: memalign(tx_dma_buf) failed\n", __func__); 1691 ret = -ENOMEM; 1692 goto err_free_descs; 1693 } 1694 debug("%s: tx_dma_buf=%p\n", __func__, eqos->tx_dma_buf); 1695 1696 eqos->rx_dma_buf = memalign(EQOS_BUFFER_ALIGN, EQOS_RX_BUFFER_SIZE); 1697 if (!eqos->rx_dma_buf) { 1698 debug("%s: memalign(rx_dma_buf) failed\n", __func__); 1699 ret = -ENOMEM; 1700 goto err_free_tx_dma_buf; 1701 } 1702 debug("%s: rx_dma_buf=%p\n", __func__, eqos->rx_dma_buf); 1703 1704 eqos->rx_pkt = malloc(EQOS_MAX_PACKET_SIZE); 1705 if (!eqos->rx_pkt) { 1706 debug("%s: malloc(rx_pkt) failed\n", __func__); 1707 ret = -ENOMEM; 1708 goto err_free_rx_dma_buf; 1709 } 1710 debug("%s: rx_pkt=%p\n", __func__, eqos->rx_pkt); 1711 1712 eqos->config->ops->eqos_inval_buffer(eqos->rx_dma_buf, 1713 EQOS_MAX_PACKET_SIZE * EQOS_DESCRIPTORS_RX); 1714 1715 debug("%s: OK\n", __func__); 1716 return 0; 1717 1718 err_free_rx_dma_buf: 1719 free(eqos->rx_dma_buf); 1720 err_free_tx_dma_buf: 1721 free(eqos->tx_dma_buf); 1722 err_free_descs: 1723 eqos_free_descs(eqos->descs); 1724 err: 1725 1726 debug("%s: returns %d\n", __func__, ret); 1727 return ret; 1728 } 1729 1730 static int eqos_remove_resources_core(struct udevice *dev) 1731 { 1732 struct eqos_priv *eqos = dev_get_priv(dev); 1733 1734 debug("%s(dev=%p):\n", __func__, dev); 1735 1736 free(eqos->rx_pkt); 1737 free(eqos->rx_dma_buf); 1738 free(eqos->tx_dma_buf); 1739 eqos_free_descs(eqos->descs); 1740 1741 debug("%s: OK\n", __func__); 1742 return 0; 1743 } 1744 1745 #ifdef CONFIG_QOS_FULL 1746 static int eqos_probe_resources_tegra186(struct udevice *dev) 1747 { 1748 struct eqos_priv *eqos = dev_get_priv(dev); 1749 int ret; 1750 1751 debug("%s(dev=%p):\n", __func__, dev); 1752 1753 ret = reset_get_by_name(dev, "eqos", &eqos->reset_ctl); 1754 if (ret) { 1755 pr_err("reset_get_by_name(rst) failed: %d", ret); 1756 return ret; 1757 } 1758 1759 ret = gpio_request_by_name(dev, "phy-reset-gpios", 0, 1760 &eqos->phy_reset_gpio, 1761 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); 1762 if (ret) { 1763 pr_err("gpio_request_by_name(phy reset) failed: %d", ret); 1764 goto err_free_reset_eqos; 1765 } 1766 1767 ret = clk_get_by_name(dev, "slave_bus", &eqos->clk_slave_bus); 1768 if (ret) { 1769 pr_err("clk_get_by_name(slave_bus) failed: %d", ret); 1770 goto err_free_gpio_phy_reset; 1771 } 1772 1773 ret = clk_get_by_name(dev, "master_bus", &eqos->clk_master_bus); 1774 if (ret) { 1775 pr_err("clk_get_by_name(master_bus) failed: %d", ret); 1776 goto err_free_clk_slave_bus; 1777 } 1778 1779 ret = clk_get_by_name(dev, "rx", &eqos->clk_rx); 1780 if (ret) { 1781 pr_err("clk_get_by_name(rx) failed: %d", ret); 1782 goto err_free_clk_master_bus; 1783 } 1784 1785 ret = clk_get_by_name(dev, "ptp_ref", &eqos->clk_ptp_ref); 1786 if (ret) { 1787 pr_err("clk_get_by_name(ptp_ref) failed: %d", ret); 1788 goto err_free_clk_rx; 1789 return ret; 1790 } 1791 1792 ret = clk_get_by_name(dev, "tx", &eqos->clk_tx); 1793 if (ret) { 1794 pr_err("clk_get_by_name(tx) failed: %d", ret); 1795 goto err_free_clk_ptp_ref; 1796 } 1797 1798 debug("%s: OK\n", __func__); 1799 return 0; 1800 1801 err_free_clk_ptp_ref: 1802 clk_free(&eqos->clk_ptp_ref); 1803 err_free_clk_rx: 1804 clk_free(&eqos->clk_rx); 1805 err_free_clk_master_bus: 1806 clk_free(&eqos->clk_master_bus); 1807 err_free_clk_slave_bus: 1808 clk_free(&eqos->clk_slave_bus); 1809 err_free_gpio_phy_reset: 1810 dm_gpio_free(dev, &eqos->phy_reset_gpio); 1811 err_free_reset_eqos: 1812 reset_free(&eqos->reset_ctl); 1813 1814 debug("%s: returns %d\n", __func__, ret); 1815 return ret; 1816 } 1817 #endif 1818 1819 /* board-specific Ethernet Interface initializations. */ 1820 __weak int board_interface_eth_init(struct udevice *dev, 1821 phy_interface_t interface_type) 1822 { 1823 return 0; 1824 } 1825 1826 static int eqos_probe_resources_stm32(struct udevice *dev) 1827 { 1828 struct eqos_priv *eqos = dev_get_priv(dev); 1829 int ret; 1830 phy_interface_t interface; 1831 struct ofnode_phandle_args phandle_args; 1832 1833 debug("%s(dev=%p):\n", __func__, dev); 1834 1835 interface = eqos->config->ops->eqos_get_interface(dev); 1836 1837 if (interface == PHY_INTERFACE_MODE_NONE) { 1838 pr_err("Invalid PHY interface\n"); 1839 return -EINVAL; 1840 } 1841 1842 ret = board_interface_eth_init(dev, interface); 1843 if (ret) 1844 return -EINVAL; 1845 1846 eqos->max_speed = dev_read_u32_default(dev, "max-speed", 0); 1847 1848 ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus); 1849 if (ret) { 1850 pr_err("clk_get_by_name(master_bus) failed: %d", ret); 1851 return ret; 1852 } 1853 1854 ret = clk_get_by_name(dev, "mac-clk-rx", &eqos->clk_rx); 1855 if (ret) 1856 pr_warn("clk_get_by_name(rx) failed: %d", ret); 1857 1858 ret = clk_get_by_name(dev, "mac-clk-tx", &eqos->clk_tx); 1859 if (ret) 1860 pr_warn("clk_get_by_name(tx) failed: %d", ret); 1861 1862 /* Get ETH_CLK clocks (optional) */ 1863 ret = clk_get_by_name(dev, "eth-ck", &eqos->clk_ck); 1864 if (ret) 1865 pr_warn("No phy clock provided %d", ret); 1866 1867 eqos->phyaddr = -1; 1868 ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, 1869 &phandle_args); 1870 if (!ret) { 1871 /* search "reset-gpios" in phy node */ 1872 ret = gpio_request_by_name_nodev(phandle_args.node, 1873 "reset-gpios", 0, 1874 &eqos->phy_reset_gpio, 1875 GPIOD_IS_OUT | 1876 GPIOD_IS_OUT_ACTIVE); 1877 if (ret) 1878 pr_warn("gpio_request_by_name(phy reset) not provided %d", 1879 ret); 1880 else 1881 eqos->reset_delays[1] = 2; 1882 1883 eqos->phyaddr = ofnode_read_u32_default(phandle_args.node, 1884 "reg", -1); 1885 } 1886 1887 if (!dm_gpio_is_valid(&eqos->phy_reset_gpio)) { 1888 int reset_flags = GPIOD_IS_OUT; 1889 1890 if (dev_read_bool(dev, "snps,reset-active-low")) 1891 reset_flags |= GPIOD_ACTIVE_LOW; 1892 1893 ret = gpio_request_by_name(dev, "snps,reset-gpio", 0, 1894 &eqos->phy_reset_gpio, reset_flags); 1895 if (ret == 0) 1896 ret = dev_read_u32_array(dev, "snps,reset-delays-us", 1897 eqos->reset_delays, 3); 1898 else 1899 pr_warn("gpio_request_by_name(snps,reset-gpio) failed: %d", 1900 ret); 1901 } 1902 1903 debug("%s: OK\n", __func__); 1904 return 0; 1905 } 1906 1907 static phy_interface_t eqos_get_interface_stm32(struct udevice *dev) 1908 { 1909 const char *phy_mode; 1910 phy_interface_t interface = PHY_INTERFACE_MODE_NONE; 1911 1912 debug("%s(dev=%p):\n", __func__, dev); 1913 1914 phy_mode = dev_read_string(dev, "phy-mode"); 1915 if (phy_mode) 1916 interface = phy_get_interface_by_name(phy_mode); 1917 1918 return interface; 1919 } 1920 1921 #ifdef CONFIG_QOS_FULL 1922 static phy_interface_t eqos_get_interface_tegra186(struct udevice *dev) 1923 { 1924 return PHY_INTERFACE_MODE_MII; 1925 } 1926 1927 static int eqos_probe_resources_imx(struct udevice *dev) 1928 { 1929 struct eqos_priv *eqos = dev_get_priv(dev); 1930 phy_interface_t interface; 1931 1932 debug("%s(dev=%p):\n", __func__, dev); 1933 1934 interface = eqos->config->ops->eqos_get_interface(dev); 1935 1936 if (interface == PHY_INTERFACE_MODE_NONE) { 1937 pr_err("Invalid PHY interface\n"); 1938 return -EINVAL; 1939 } 1940 1941 debug("%s: OK\n", __func__); 1942 return 0; 1943 } 1944 1945 static phy_interface_t eqos_get_interface_imx(struct udevice *dev) 1946 { 1947 const char *phy_mode; 1948 phy_interface_t interface = PHY_INTERFACE_MODE_NONE; 1949 1950 debug("%s(dev=%p):\n", __func__, dev); 1951 1952 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode", 1953 NULL); 1954 if (phy_mode) 1955 interface = phy_get_interface_by_name(phy_mode); 1956 1957 return interface; 1958 } 1959 1960 static int eqos_remove_resources_tegra186(struct udevice *dev) 1961 { 1962 struct eqos_priv *eqos = dev_get_priv(dev); 1963 1964 debug("%s(dev=%p):\n", __func__, dev); 1965 1966 #ifdef CONFIG_CLK 1967 clk_free(&eqos->clk_tx); 1968 clk_free(&eqos->clk_ptp_ref); 1969 clk_free(&eqos->clk_rx); 1970 clk_free(&eqos->clk_slave_bus); 1971 clk_free(&eqos->clk_master_bus); 1972 #endif 1973 dm_gpio_free(dev, &eqos->phy_reset_gpio); 1974 reset_free(&eqos->reset_ctl); 1975 1976 debug("%s: OK\n", __func__); 1977 return 0; 1978 } 1979 #endif 1980 1981 static int eqos_remove_resources_stm32(struct udevice *dev) 1982 { 1983 #ifdef CONFIG_CLK 1984 struct eqos_priv *eqos = dev_get_priv(dev); 1985 1986 debug("%s(dev=%p):\n", __func__, dev); 1987 1988 if (clk_valid(&eqos->clk_tx)) 1989 clk_free(&eqos->clk_tx); 1990 if (clk_valid(&eqos->clk_rx)) 1991 clk_free(&eqos->clk_rx); 1992 clk_free(&eqos->clk_master_bus); 1993 if (clk_valid(&eqos->clk_ck)) 1994 clk_free(&eqos->clk_ck); 1995 #endif 1996 1997 if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) 1998 dm_gpio_free(dev, &eqos->phy_reset_gpio); 1999 2000 debug("%s: OK\n", __func__); 2001 return 0; 2002 } 2003 2004 #ifdef CONFIG_QOS_FULL 2005 static int eqos_remove_resources_imx(struct udevice *dev) 2006 { 2007 return 0; 2008 } 2009 #endif 2010 2011 int eqos_probe(struct udevice *dev) 2012 { 2013 struct eqos_priv *eqos = dev_get_priv(dev); 2014 int ret; 2015 2016 debug("%s(dev=%p):\n", __func__, dev); 2017 2018 eqos->dev = dev; 2019 eqos->config = (void *)dev_get_driver_data(dev); 2020 2021 eqos->regs = dev_read_addr(dev); 2022 if (eqos->regs == FDT_ADDR_T_NONE) { 2023 pr_err("dev_read_addr() failed"); 2024 return -ENODEV; 2025 } 2026 eqos->mac_regs = (void *)(eqos->regs + EQOS_MAC_REGS_BASE); 2027 eqos->mtl_regs = (void *)(eqos->regs + EQOS_MTL_REGS_BASE); 2028 eqos->dma_regs = (void *)(eqos->regs + EQOS_DMA_REGS_BASE); 2029 eqos->tegra186_regs = (void *)(eqos->regs + EQOS_TEGRA186_REGS_BASE); 2030 2031 ret = eqos_probe_resources_core(dev); 2032 if (ret < 0) { 2033 pr_err("eqos_probe_resources_core() failed: %d", ret); 2034 return ret; 2035 } 2036 2037 ret = eqos->config->ops->eqos_probe_resources(dev); 2038 if (ret < 0) { 2039 pr_err("eqos_probe_resources() failed: %d", ret); 2040 goto err_remove_resources_core; 2041 } 2042 2043 #ifdef CONFIG_DM_ETH_PHY 2044 eqos->mii = eth_phy_get_mdio_bus(dev); 2045 #endif 2046 if (!eqos->mii) { 2047 eqos->mii = mdio_alloc(); 2048 if (!eqos->mii) { 2049 pr_err("mdio_alloc() failed"); 2050 ret = -ENOMEM; 2051 goto err_remove_resources_tegra; 2052 } 2053 eqos->mii->read = eqos_mdio_read; 2054 eqos->mii->write = eqos_mdio_write; 2055 eqos->mii->priv = eqos; 2056 strcpy(eqos->mii->name, dev->name); 2057 2058 ret = mdio_register(eqos->mii); 2059 if (ret < 0) { 2060 pr_err("mdio_register() failed: %d", ret); 2061 goto err_free_mdio; 2062 } 2063 } 2064 2065 #ifdef CONFIG_DM_ETH_PHY 2066 eth_phy_set_mdio_bus(dev, eqos->mii); 2067 #endif 2068 2069 debug("%s: OK\n", __func__); 2070 return 0; 2071 2072 err_free_mdio: 2073 mdio_free(eqos->mii); 2074 err_remove_resources_tegra: 2075 eqos->config->ops->eqos_remove_resources(dev); 2076 err_remove_resources_core: 2077 eqos_remove_resources_core(dev); 2078 2079 debug("%s: returns %d\n", __func__, ret); 2080 return ret; 2081 } 2082 2083 static int __maybe_unused eqos_remove(struct udevice *dev) 2084 { 2085 struct eqos_priv *eqos = dev_get_priv(dev); 2086 2087 debug("%s(dev=%p):\n", __func__, dev); 2088 2089 mdio_unregister(eqos->mii); 2090 mdio_free(eqos->mii); 2091 eqos->config->ops->eqos_remove_resources(dev); 2092 2093 eqos_probe_resources_core(dev); 2094 2095 debug("%s: OK\n", __func__); 2096 return 0; 2097 } 2098 2099 #ifdef CONFIG_QOS_FULL 2100 static const struct eth_ops eqos_ops = { 2101 .start = eqos_start, 2102 .stop = eqos_stop, 2103 .send = eqos_send, 2104 .recv = eqos_recv, 2105 .free_pkt = eqos_free_pkt, 2106 .write_hwaddr = eqos_write_hwaddr, 2107 .read_rom_hwaddr = eqos_read_rom_hwaddr, 2108 }; 2109 2110 static struct eqos_ops eqos_tegra186_ops = { 2111 .eqos_inval_desc = eqos_inval_desc_tegra186, 2112 .eqos_flush_desc = eqos_flush_desc_tegra186, 2113 .eqos_inval_buffer = eqos_inval_buffer_tegra186, 2114 .eqos_flush_buffer = eqos_flush_buffer_tegra186, 2115 .eqos_probe_resources = eqos_probe_resources_tegra186, 2116 .eqos_remove_resources = eqos_remove_resources_tegra186, 2117 .eqos_stop_resets = eqos_stop_resets_tegra186, 2118 .eqos_start_resets = eqos_start_resets_tegra186, 2119 .eqos_stop_clks = eqos_stop_clks_tegra186, 2120 .eqos_start_clks = eqos_start_clks_tegra186, 2121 .eqos_calibrate_pads = eqos_calibrate_pads_tegra186, 2122 .eqos_disable_calibration = eqos_disable_calibration_tegra186, 2123 .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_tegra186, 2124 .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_tegra186, 2125 .eqos_get_interface = eqos_get_interface_tegra186 2126 }; 2127 2128 static const struct eqos_config eqos_tegra186_config = { 2129 .reg_access_always_ok = false, 2130 .mdio_wait = 10, 2131 .swr_wait = 10, 2132 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB, 2133 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_20_35, 2134 .ops = &eqos_tegra186_ops 2135 }; 2136 2137 static struct eqos_ops eqos_stm32_ops = { 2138 .eqos_inval_desc = eqos_inval_desc_generic, 2139 .eqos_flush_desc = eqos_flush_desc_generic, 2140 .eqos_inval_buffer = eqos_inval_buffer_generic, 2141 .eqos_flush_buffer = eqos_flush_buffer_generic, 2142 .eqos_probe_resources = eqos_probe_resources_stm32, 2143 .eqos_remove_resources = eqos_remove_resources_stm32, 2144 .eqos_stop_resets = eqos_stop_resets_stm32, 2145 .eqos_start_resets = eqos_start_resets_stm32, 2146 .eqos_stop_clks = eqos_stop_clks_stm32, 2147 .eqos_start_clks = eqos_start_clks_stm32, 2148 .eqos_calibrate_pads = eqos_calibrate_pads_stm32, 2149 .eqos_disable_calibration = eqos_disable_calibration_stm32, 2150 .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_stm32, 2151 .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32, 2152 .eqos_get_interface = eqos_get_interface_stm32 2153 }; 2154 2155 static const struct eqos_config eqos_stm32_config = { 2156 .reg_access_always_ok = false, 2157 .mdio_wait = 10000, 2158 .swr_wait = 50, 2159 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV, 2160 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300, 2161 .ops = &eqos_stm32_ops 2162 }; 2163 2164 static struct eqos_ops eqos_imx_ops = { 2165 .eqos_inval_desc = eqos_inval_desc_generic, 2166 .eqos_flush_desc = eqos_flush_desc_generic, 2167 .eqos_inval_buffer = eqos_inval_buffer_generic, 2168 .eqos_flush_buffer = eqos_flush_buffer_generic, 2169 .eqos_probe_resources = eqos_probe_resources_imx, 2170 .eqos_remove_resources = eqos_remove_resources_imx, 2171 .eqos_stop_resets = eqos_stop_resets_imx, 2172 .eqos_start_resets = eqos_start_resets_imx, 2173 .eqos_stop_clks = eqos_stop_clks_imx, 2174 .eqos_start_clks = eqos_start_clks_imx, 2175 .eqos_calibrate_pads = eqos_calibrate_pads_imx, 2176 .eqos_disable_calibration = eqos_disable_calibration_imx, 2177 .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_imx, 2178 .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_imx, 2179 .eqos_get_interface = eqos_get_interface_imx 2180 }; 2181 2182 struct eqos_config eqos_imx_config = { 2183 .reg_access_always_ok = false, 2184 .mdio_wait = 10000, 2185 .swr_wait = 50, 2186 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB, 2187 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300, 2188 .ops = &eqos_imx_ops 2189 }; 2190 #endif 2191 2192 struct eqos_ops eqos_rockchip_ops = { 2193 .eqos_inval_desc = eqos_inval_desc_generic, 2194 .eqos_flush_desc = eqos_flush_desc_generic, 2195 .eqos_inval_buffer = eqos_inval_buffer_generic, 2196 .eqos_flush_buffer = eqos_flush_buffer_generic, 2197 .eqos_probe_resources = eqos_probe_resources_stm32, 2198 .eqos_remove_resources = eqos_remove_resources_stm32, 2199 .eqos_stop_resets = eqos_stop_resets_stm32, 2200 .eqos_start_resets = eqos_start_resets_stm32, 2201 .eqos_calibrate_pads = eqos_calibrate_pads_stm32, 2202 .eqos_disable_calibration = eqos_disable_calibration_stm32, 2203 .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_stm32, 2204 .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32, 2205 .eqos_get_interface = eqos_get_interface_stm32 2206 }; 2207 2208 #ifdef CONFIG_QOS_FULL 2209 static const struct udevice_id eqos_ids[] = { 2210 { 2211 .compatible = "nvidia,tegra186-eqos", 2212 .data = (ulong)&eqos_tegra186_config 2213 }, 2214 { 2215 .compatible = "snps,dwmac-4.20a", 2216 .data = (ulong)&eqos_stm32_config 2217 }, 2218 { 2219 .compatible = "fsl,imx-eqos", 2220 .data = (ulong)&eqos_imx_config 2221 }, 2222 2223 { } 2224 }; 2225 2226 U_BOOT_DRIVER(eth_eqos) = { 2227 .name = "eth_eqos", 2228 .id = UCLASS_ETH, 2229 .of_match = of_match_ptr(eqos_ids), 2230 .probe = eqos_probe, 2231 .remove = eqos_remove, 2232 .ops = &eqos_ops, 2233 .priv_auto_alloc_size = sizeof(struct eqos_priv), 2234 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 2235 }; 2236 #endif 2237