1 /* 2 * SPI Flash Core 3 * 4 * Copyright (C) 2015 Jagan Teki <jteki@openedev.com> 5 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. 6 * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik 7 * Copyright (C) 2008 Atmel Corporation 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <errno.h> 14 #include <malloc.h> 15 #include <mapmem.h> 16 #include <spi.h> 17 #include <spi_flash.h> 18 #include <linux/log2.h> 19 20 #include "sf_internal.h" 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 static void spi_flash_addr(u32 addr, u8 *cmd) 25 { 26 /* cmd[0] is actual command */ 27 cmd[1] = addr >> 16; 28 cmd[2] = addr >> 8; 29 cmd[3] = addr >> 0; 30 } 31 32 /* Read commands array */ 33 static u8 spi_read_cmds_array[] = { 34 CMD_READ_ARRAY_SLOW, 35 CMD_READ_ARRAY_FAST, 36 CMD_READ_DUAL_OUTPUT_FAST, 37 CMD_READ_DUAL_IO_FAST, 38 CMD_READ_QUAD_OUTPUT_FAST, 39 CMD_READ_QUAD_IO_FAST, 40 }; 41 42 static int read_sr(struct spi_flash *flash, u8 *rs) 43 { 44 int ret; 45 u8 cmd; 46 47 cmd = CMD_READ_STATUS; 48 ret = spi_flash_read_common(flash, &cmd, 1, rs, 1); 49 if (ret < 0) { 50 debug("SF: fail to read status register\n"); 51 return ret; 52 } 53 54 return 0; 55 } 56 57 static int read_fsr(struct spi_flash *flash, u8 *fsr) 58 { 59 int ret; 60 const u8 cmd = CMD_FLAG_STATUS; 61 62 ret = spi_flash_read_common(flash, &cmd, 1, fsr, 1); 63 if (ret < 0) { 64 debug("SF: fail to read flag status register\n"); 65 return ret; 66 } 67 68 return 0; 69 } 70 71 static int write_sr(struct spi_flash *flash, u8 ws) 72 { 73 u8 cmd; 74 int ret; 75 76 cmd = CMD_WRITE_STATUS; 77 ret = spi_flash_write_common(flash, &cmd, 1, &ws, 1); 78 if (ret < 0) { 79 debug("SF: fail to write status register\n"); 80 return ret; 81 } 82 83 return 0; 84 } 85 86 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 87 static int read_cr(struct spi_flash *flash, u8 *rc) 88 { 89 int ret; 90 u8 cmd; 91 92 cmd = CMD_READ_CONFIG; 93 ret = spi_flash_read_common(flash, &cmd, 1, rc, 1); 94 if (ret < 0) { 95 debug("SF: fail to read config register\n"); 96 return ret; 97 } 98 99 return 0; 100 } 101 102 static int write_cr(struct spi_flash *flash, u8 wc) 103 { 104 u8 data[2]; 105 u8 cmd; 106 int ret; 107 108 ret = read_sr(flash, &data[0]); 109 if (ret < 0) 110 return ret; 111 112 cmd = CMD_WRITE_STATUS; 113 data[1] = wc; 114 ret = spi_flash_write_common(flash, &cmd, 1, &data, 2); 115 if (ret) { 116 debug("SF: fail to write config register\n"); 117 return ret; 118 } 119 120 return 0; 121 } 122 #endif 123 124 #ifdef CONFIG_SPI_FLASH_BAR 125 static int spi_flash_write_bar(struct spi_flash *flash, u32 offset) 126 { 127 u8 cmd, bank_sel; 128 int ret; 129 130 bank_sel = offset / (SPI_FLASH_16MB_BOUN << flash->shift); 131 if (bank_sel == flash->bank_curr) 132 goto bar_end; 133 134 cmd = flash->bank_write_cmd; 135 ret = spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1); 136 if (ret < 0) { 137 debug("SF: fail to write bank register\n"); 138 return ret; 139 } 140 141 bar_end: 142 flash->bank_curr = bank_sel; 143 return flash->bank_curr; 144 } 145 146 static int spi_flash_read_bar(struct spi_flash *flash, u8 idcode0) 147 { 148 u8 curr_bank = 0; 149 int ret; 150 151 if (flash->size <= SPI_FLASH_16MB_BOUN) 152 goto bank_end; 153 154 switch (idcode0) { 155 case SPI_FLASH_CFI_MFR_SPANSION: 156 flash->bank_read_cmd = CMD_BANKADDR_BRRD; 157 flash->bank_write_cmd = CMD_BANKADDR_BRWR; 158 break; 159 default: 160 flash->bank_read_cmd = CMD_EXTNADDR_RDEAR; 161 flash->bank_write_cmd = CMD_EXTNADDR_WREAR; 162 } 163 164 ret = spi_flash_read_common(flash, &flash->bank_read_cmd, 1, 165 &curr_bank, 1); 166 if (ret) { 167 debug("SF: fail to read bank addr register\n"); 168 return ret; 169 } 170 171 bank_end: 172 flash->bank_curr = curr_bank; 173 return 0; 174 } 175 #endif 176 177 #ifdef CONFIG_SF_DUAL_FLASH 178 static void spi_flash_dual(struct spi_flash *flash, u32 *addr) 179 { 180 switch (flash->dual_flash) { 181 case SF_DUAL_STACKED_FLASH: 182 if (*addr >= (flash->size >> 1)) { 183 *addr -= flash->size >> 1; 184 flash->spi->flags |= SPI_XFER_U_PAGE; 185 } else { 186 flash->spi->flags &= ~SPI_XFER_U_PAGE; 187 } 188 break; 189 case SF_DUAL_PARALLEL_FLASH: 190 *addr >>= flash->shift; 191 break; 192 default: 193 debug("SF: Unsupported dual_flash=%d\n", flash->dual_flash); 194 break; 195 } 196 } 197 #endif 198 199 static int spi_flash_sr_ready(struct spi_flash *flash) 200 { 201 u8 sr; 202 int ret; 203 204 ret = read_sr(flash, &sr); 205 if (ret < 0) 206 return ret; 207 208 return !(sr & STATUS_WIP); 209 } 210 211 static int spi_flash_fsr_ready(struct spi_flash *flash) 212 { 213 u8 fsr; 214 int ret; 215 216 ret = read_fsr(flash, &fsr); 217 if (ret < 0) 218 return ret; 219 220 return fsr & STATUS_PEC; 221 } 222 223 static int spi_flash_ready(struct spi_flash *flash) 224 { 225 int sr, fsr; 226 227 sr = spi_flash_sr_ready(flash); 228 if (sr < 0) 229 return sr; 230 231 fsr = 1; 232 if (flash->flags & SNOR_F_USE_FSR) { 233 fsr = spi_flash_fsr_ready(flash); 234 if (fsr < 0) 235 return fsr; 236 } 237 238 return sr && fsr; 239 } 240 241 static int spi_flash_cmd_wait_ready(struct spi_flash *flash, 242 unsigned long timeout) 243 { 244 int timebase, ret; 245 246 timebase = get_timer(0); 247 248 while (get_timer(timebase) < timeout) { 249 ret = spi_flash_ready(flash); 250 if (ret < 0) 251 return ret; 252 if (ret) 253 return 0; 254 } 255 256 printf("SF: Timeout!\n"); 257 258 return -ETIMEDOUT; 259 } 260 261 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, 262 size_t cmd_len, const void *buf, size_t buf_len) 263 { 264 struct spi_slave *spi = flash->spi; 265 unsigned long timeout = SPI_FLASH_PROG_TIMEOUT; 266 int ret; 267 268 if (buf == NULL) 269 timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT; 270 271 ret = spi_claim_bus(flash->spi); 272 if (ret) { 273 debug("SF: unable to claim SPI bus\n"); 274 return ret; 275 } 276 277 ret = spi_flash_cmd_write_enable(flash); 278 if (ret < 0) { 279 debug("SF: enabling write failed\n"); 280 return ret; 281 } 282 283 ret = spi_flash_cmd_write(spi, cmd, cmd_len, buf, buf_len); 284 if (ret < 0) { 285 debug("SF: write cmd failed\n"); 286 return ret; 287 } 288 289 ret = spi_flash_cmd_wait_ready(flash, timeout); 290 if (ret < 0) { 291 debug("SF: write %s timed out\n", 292 timeout == SPI_FLASH_PROG_TIMEOUT ? 293 "program" : "page erase"); 294 return ret; 295 } 296 297 spi_release_bus(spi); 298 299 return ret; 300 } 301 302 int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) 303 { 304 u32 erase_size, erase_addr; 305 u8 cmd[SPI_FLASH_CMD_LEN]; 306 int ret = -1; 307 308 erase_size = flash->erase_size; 309 if (offset % erase_size || len % erase_size) { 310 debug("SF: Erase offset/length not multiple of erase size\n"); 311 return -1; 312 } 313 314 if (flash->flash_is_locked) { 315 if (flash->flash_is_locked(flash, offset, len) > 0) { 316 printf("offset 0x%x is protected and cannot be erased\n", 317 offset); 318 return -EINVAL; 319 } 320 } 321 322 cmd[0] = flash->erase_cmd; 323 while (len) { 324 erase_addr = offset; 325 326 #ifdef CONFIG_SF_DUAL_FLASH 327 if (flash->dual_flash > SF_SINGLE_FLASH) 328 spi_flash_dual(flash, &erase_addr); 329 #endif 330 #ifdef CONFIG_SPI_FLASH_BAR 331 ret = spi_flash_write_bar(flash, erase_addr); 332 if (ret < 0) 333 return ret; 334 #endif 335 spi_flash_addr(erase_addr, cmd); 336 337 debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1], 338 cmd[2], cmd[3], erase_addr); 339 340 ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0); 341 if (ret < 0) { 342 debug("SF: erase failed\n"); 343 break; 344 } 345 346 offset += erase_size; 347 len -= erase_size; 348 } 349 350 return ret; 351 } 352 353 int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, 354 size_t len, const void *buf) 355 { 356 unsigned long byte_addr, page_size; 357 u32 write_addr; 358 size_t chunk_len, actual; 359 u8 cmd[SPI_FLASH_CMD_LEN]; 360 int ret = -1; 361 362 page_size = flash->page_size; 363 364 if (flash->flash_is_locked) { 365 if (flash->flash_is_locked(flash, offset, len) > 0) { 366 printf("offset 0x%x is protected and cannot be written\n", 367 offset); 368 return -EINVAL; 369 } 370 } 371 372 cmd[0] = flash->write_cmd; 373 for (actual = 0; actual < len; actual += chunk_len) { 374 write_addr = offset; 375 376 #ifdef CONFIG_SF_DUAL_FLASH 377 if (flash->dual_flash > SF_SINGLE_FLASH) 378 spi_flash_dual(flash, &write_addr); 379 #endif 380 #ifdef CONFIG_SPI_FLASH_BAR 381 ret = spi_flash_write_bar(flash, write_addr); 382 if (ret < 0) 383 return ret; 384 #endif 385 byte_addr = offset % page_size; 386 chunk_len = min(len - actual, (size_t)(page_size - byte_addr)); 387 388 if (flash->spi->max_write_size) 389 chunk_len = min(chunk_len, 390 (size_t)flash->spi->max_write_size); 391 392 spi_flash_addr(write_addr, cmd); 393 394 debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", 395 buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); 396 397 ret = spi_flash_write_common(flash, cmd, sizeof(cmd), 398 buf + actual, chunk_len); 399 if (ret < 0) { 400 debug("SF: write failed\n"); 401 break; 402 } 403 404 offset += chunk_len; 405 } 406 407 return ret; 408 } 409 410 int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, 411 size_t cmd_len, void *data, size_t data_len) 412 { 413 struct spi_slave *spi = flash->spi; 414 int ret; 415 416 ret = spi_claim_bus(flash->spi); 417 if (ret) { 418 debug("SF: unable to claim SPI bus\n"); 419 return ret; 420 } 421 422 ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len); 423 if (ret < 0) { 424 debug("SF: read cmd failed\n"); 425 return ret; 426 } 427 428 spi_release_bus(spi); 429 430 return ret; 431 } 432 433 void __weak spi_flash_copy_mmap(void *data, void *offset, size_t len) 434 { 435 memcpy(data, offset, len); 436 } 437 438 int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, 439 size_t len, void *data) 440 { 441 u8 *cmd, cmdsz; 442 u32 remain_len, read_len, read_addr; 443 int bank_sel = 0; 444 int ret = -1; 445 446 /* Handle memory-mapped SPI */ 447 if (flash->memory_map) { 448 ret = spi_claim_bus(flash->spi); 449 if (ret) { 450 debug("SF: unable to claim SPI bus\n"); 451 return ret; 452 } 453 spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP); 454 spi_flash_copy_mmap(data, flash->memory_map + offset, len); 455 spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP_END); 456 spi_release_bus(flash->spi); 457 return 0; 458 } 459 460 cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte; 461 cmd = calloc(1, cmdsz); 462 if (!cmd) { 463 debug("SF: Failed to allocate cmd\n"); 464 return -ENOMEM; 465 } 466 467 cmd[0] = flash->read_cmd; 468 while (len) { 469 read_addr = offset; 470 471 #ifdef CONFIG_SF_DUAL_FLASH 472 if (flash->dual_flash > SF_SINGLE_FLASH) 473 spi_flash_dual(flash, &read_addr); 474 #endif 475 #ifdef CONFIG_SPI_FLASH_BAR 476 ret = spi_flash_write_bar(flash, read_addr); 477 if (ret < 0) 478 return ret; 479 bank_sel = flash->bank_curr; 480 #endif 481 remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) * 482 (bank_sel + 1)) - offset; 483 if (len < remain_len) 484 read_len = len; 485 else 486 read_len = remain_len; 487 488 spi_flash_addr(read_addr, cmd); 489 490 ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len); 491 if (ret < 0) { 492 debug("SF: read failed\n"); 493 break; 494 } 495 496 offset += read_len; 497 len -= read_len; 498 data += read_len; 499 } 500 501 free(cmd); 502 return ret; 503 } 504 505 #ifdef CONFIG_SPI_FLASH_SST 506 static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf) 507 { 508 int ret; 509 u8 cmd[4] = { 510 CMD_SST_BP, 511 offset >> 16, 512 offset >> 8, 513 offset, 514 }; 515 516 debug("BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", 517 spi_w8r8(flash->spi, CMD_READ_STATUS), buf, cmd[0], offset); 518 519 ret = spi_flash_cmd_write_enable(flash); 520 if (ret) 521 return ret; 522 523 ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), buf, 1); 524 if (ret) 525 return ret; 526 527 return spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); 528 } 529 530 int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, 531 const void *buf) 532 { 533 size_t actual, cmd_len; 534 int ret; 535 u8 cmd[4]; 536 537 ret = spi_claim_bus(flash->spi); 538 if (ret) { 539 debug("SF: Unable to claim SPI bus\n"); 540 return ret; 541 } 542 543 /* If the data is not word aligned, write out leading single byte */ 544 actual = offset % 2; 545 if (actual) { 546 ret = sst_byte_write(flash, offset, buf); 547 if (ret) 548 goto done; 549 } 550 offset += actual; 551 552 ret = spi_flash_cmd_write_enable(flash); 553 if (ret) 554 goto done; 555 556 cmd_len = 4; 557 cmd[0] = CMD_SST_AAI_WP; 558 cmd[1] = offset >> 16; 559 cmd[2] = offset >> 8; 560 cmd[3] = offset; 561 562 for (; actual < len - 1; actual += 2) { 563 debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", 564 spi_w8r8(flash->spi, CMD_READ_STATUS), buf + actual, 565 cmd[0], offset); 566 567 ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len, 568 buf + actual, 2); 569 if (ret) { 570 debug("SF: sst word program failed\n"); 571 break; 572 } 573 574 ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); 575 if (ret) 576 break; 577 578 cmd_len = 1; 579 offset += 2; 580 } 581 582 if (!ret) 583 ret = spi_flash_cmd_write_disable(flash); 584 585 /* If there is a single trailing byte, write it out */ 586 if (!ret && actual != len) 587 ret = sst_byte_write(flash, offset, buf + actual); 588 589 done: 590 debug("SF: sst: program %s %zu bytes @ 0x%zx\n", 591 ret ? "failure" : "success", len, offset - actual); 592 593 spi_release_bus(flash->spi); 594 return ret; 595 } 596 597 int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len, 598 const void *buf) 599 { 600 size_t actual; 601 int ret; 602 603 ret = spi_claim_bus(flash->spi); 604 if (ret) { 605 debug("SF: Unable to claim SPI bus\n"); 606 return ret; 607 } 608 609 for (actual = 0; actual < len; actual++) { 610 ret = sst_byte_write(flash, offset, buf + actual); 611 if (ret) { 612 debug("SF: sst byte program failed\n"); 613 break; 614 } 615 offset++; 616 } 617 618 if (!ret) 619 ret = spi_flash_cmd_write_disable(flash); 620 621 debug("SF: sst: program %s %zu bytes @ 0x%zx\n", 622 ret ? "failure" : "success", len, offset - actual); 623 624 spi_release_bus(flash->spi); 625 return ret; 626 } 627 #endif 628 629 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) 630 static void stm_get_locked_range(struct spi_flash *flash, u8 sr, loff_t *ofs, 631 u32 *len) 632 { 633 u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 634 int shift = ffs(mask) - 1; 635 int pow; 636 637 if (!(sr & mask)) { 638 /* No protection */ 639 *ofs = 0; 640 *len = 0; 641 } else { 642 pow = ((sr & mask) ^ mask) >> shift; 643 *len = flash->size >> pow; 644 *ofs = flash->size - *len; 645 } 646 } 647 648 /* 649 * Return 1 if the entire region is locked, 0 otherwise 650 */ 651 static int stm_is_locked_sr(struct spi_flash *flash, u32 ofs, u32 len, 652 u8 sr) 653 { 654 loff_t lock_offs; 655 u32 lock_len; 656 657 stm_get_locked_range(flash, sr, &lock_offs, &lock_len); 658 659 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs); 660 } 661 662 /* 663 * Check if a region of the flash is (completely) locked. See stm_lock() for 664 * more info. 665 * 666 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and 667 * negative on errors. 668 */ 669 int stm_is_locked(struct spi_flash *flash, u32 ofs, size_t len) 670 { 671 int status; 672 u8 sr; 673 674 status = read_sr(flash, &sr); 675 if (status < 0) 676 return status; 677 678 return stm_is_locked_sr(flash, ofs, len, sr); 679 } 680 681 /* 682 * Lock a region of the flash. Compatible with ST Micro and similar flash. 683 * Supports only the block protection bits BP{0,1,2} in the status register 684 * (SR). Does not support these features found in newer SR bitfields: 685 * - TB: top/bottom protect - only handle TB=0 (top protect) 686 * - SEC: sector/block protect - only handle SEC=0 (block protect) 687 * - CMP: complement protect - only support CMP=0 (range is not complemented) 688 * 689 * Sample table portion for 8MB flash (Winbond w25q64fw): 690 * 691 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion 692 * -------------------------------------------------------------------------- 693 * X | X | 0 | 0 | 0 | NONE | NONE 694 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64 695 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32 696 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16 697 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8 698 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4 699 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2 700 * X | X | 1 | 1 | 1 | 8 MB | ALL 701 * 702 * Returns negative on errors, 0 on success. 703 */ 704 int stm_lock(struct spi_flash *flash, u32 ofs, size_t len) 705 { 706 u8 status_old, status_new; 707 u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 708 u8 shift = ffs(mask) - 1, pow, val; 709 int ret; 710 711 ret = read_sr(flash, &status_old); 712 if (ret < 0) 713 return ret; 714 715 /* SPI NOR always locks to the end */ 716 if (ofs + len != flash->size) { 717 /* Does combined region extend to end? */ 718 if (!stm_is_locked_sr(flash, ofs + len, flash->size - ofs - len, 719 status_old)) 720 return -EINVAL; 721 len = flash->size - ofs; 722 } 723 724 /* 725 * Need smallest pow such that: 726 * 727 * 1 / (2^pow) <= (len / size) 728 * 729 * so (assuming power-of-2 size) we do: 730 * 731 * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len)) 732 */ 733 pow = ilog2(flash->size) - ilog2(len); 734 val = mask - (pow << shift); 735 if (val & ~mask) 736 return -EINVAL; 737 738 /* Don't "lock" with no region! */ 739 if (!(val & mask)) 740 return -EINVAL; 741 742 status_new = (status_old & ~mask) | val; 743 744 /* Only modify protection if it will not unlock other areas */ 745 if ((status_new & mask) <= (status_old & mask)) 746 return -EINVAL; 747 748 write_sr(flash, status_new); 749 750 return 0; 751 } 752 753 /* 754 * Unlock a region of the flash. See stm_lock() for more info 755 * 756 * Returns negative on errors, 0 on success. 757 */ 758 int stm_unlock(struct spi_flash *flash, u32 ofs, size_t len) 759 { 760 uint8_t status_old, status_new; 761 u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 762 u8 shift = ffs(mask) - 1, pow, val; 763 int ret; 764 765 ret = read_sr(flash, &status_old); 766 if (ret < 0) 767 return ret; 768 769 /* Cannot unlock; would unlock larger region than requested */ 770 if (stm_is_locked_sr(flash, ofs - flash->erase_size, flash->erase_size, 771 status_old)) 772 return -EINVAL; 773 /* 774 * Need largest pow such that: 775 * 776 * 1 / (2^pow) >= (len / size) 777 * 778 * so (assuming power-of-2 size) we do: 779 * 780 * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len)) 781 */ 782 pow = ilog2(flash->size) - order_base_2(flash->size - (ofs + len)); 783 if (ofs + len == flash->size) { 784 val = 0; /* fully unlocked */ 785 } else { 786 val = mask - (pow << shift); 787 /* Some power-of-two sizes are not supported */ 788 if (val & ~mask) 789 return -EINVAL; 790 } 791 792 status_new = (status_old & ~mask) | val; 793 794 /* Only modify protection if it will not lock other areas */ 795 if ((status_new & mask) >= (status_old & mask)) 796 return -EINVAL; 797 798 write_sr(flash, status_new); 799 800 return 0; 801 } 802 #endif 803 804 805 #ifdef CONFIG_SPI_FLASH_MACRONIX 806 static int spi_flash_set_qeb_mxic(struct spi_flash *flash) 807 { 808 u8 qeb_status; 809 int ret; 810 811 ret = read_sr(flash, &qeb_status); 812 if (ret < 0) 813 return ret; 814 815 if (qeb_status & STATUS_QEB_MXIC) { 816 debug("SF: mxic: QEB is already set\n"); 817 } else { 818 ret = write_sr(flash, STATUS_QEB_MXIC); 819 if (ret < 0) 820 return ret; 821 } 822 823 return ret; 824 } 825 #endif 826 827 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 828 static int spi_flash_set_qeb_winspan(struct spi_flash *flash) 829 { 830 u8 qeb_status; 831 int ret; 832 833 ret = read_cr(flash, &qeb_status); 834 if (ret < 0) 835 return ret; 836 837 if (qeb_status & STATUS_QEB_WINSPAN) { 838 debug("SF: winspan: QEB is already set\n"); 839 } else { 840 ret = write_cr(flash, STATUS_QEB_WINSPAN); 841 if (ret < 0) 842 return ret; 843 } 844 845 return ret; 846 } 847 #endif 848 849 static int spi_flash_set_qeb(struct spi_flash *flash, u8 idcode0) 850 { 851 switch (idcode0) { 852 #ifdef CONFIG_SPI_FLASH_MACRONIX 853 case SPI_FLASH_CFI_MFR_MACRONIX: 854 return spi_flash_set_qeb_mxic(flash); 855 #endif 856 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 857 case SPI_FLASH_CFI_MFR_SPANSION: 858 case SPI_FLASH_CFI_MFR_WINBOND: 859 return spi_flash_set_qeb_winspan(flash); 860 #endif 861 #ifdef CONFIG_SPI_FLASH_STMICRO 862 case SPI_FLASH_CFI_MFR_STMICRO: 863 debug("SF: QEB is volatile for %02x flash\n", idcode0); 864 return 0; 865 #endif 866 default: 867 printf("SF: Need set QEB func for %02x flash\n", idcode0); 868 return -1; 869 } 870 } 871 872 #if CONFIG_IS_ENABLED(OF_CONTROL) 873 int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash) 874 { 875 fdt_addr_t addr; 876 fdt_size_t size; 877 int node; 878 879 /* If there is no node, do nothing */ 880 node = fdtdec_next_compatible(blob, 0, COMPAT_GENERIC_SPI_FLASH); 881 if (node < 0) 882 return 0; 883 884 addr = fdtdec_get_addr_size(blob, node, "memory-map", &size); 885 if (addr == FDT_ADDR_T_NONE) { 886 debug("%s: Cannot decode address\n", __func__); 887 return 0; 888 } 889 890 if (flash->size != size) { 891 debug("%s: Memory map must cover entire device\n", __func__); 892 return -1; 893 } 894 flash->memory_map = map_sysmem(addr, size); 895 896 return 0; 897 } 898 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */ 899 900 int spi_flash_scan(struct spi_flash *flash) 901 { 902 struct spi_slave *spi = flash->spi; 903 const struct spi_flash_params *params; 904 u16 jedec, ext_jedec; 905 u8 idcode[5]; 906 u8 cmd; 907 int ret; 908 909 /* Read the ID codes */ 910 ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode)); 911 if (ret) { 912 printf("SF: Failed to get idcodes\n"); 913 return -EINVAL; 914 } 915 916 #ifdef DEBUG 917 printf("SF: Got idcodes\n"); 918 print_buffer(0, idcode, 1, sizeof(idcode), 0); 919 #endif 920 921 jedec = idcode[1] << 8 | idcode[2]; 922 ext_jedec = idcode[3] << 8 | idcode[4]; 923 924 /* Validate params from spi_flash_params table */ 925 params = spi_flash_params_table; 926 for (; params->name != NULL; params++) { 927 if ((params->jedec >> 16) == idcode[0]) { 928 if ((params->jedec & 0xFFFF) == jedec) { 929 if (params->ext_jedec == 0) 930 break; 931 else if (params->ext_jedec == ext_jedec) 932 break; 933 } 934 } 935 } 936 937 if (!params->name) { 938 printf("SF: Unsupported flash IDs: "); 939 printf("manuf %02x, jedec %04x, ext_jedec %04x\n", 940 idcode[0], jedec, ext_jedec); 941 return -EPROTONOSUPPORT; 942 } 943 944 /* Flash powers up read-only, so clear BP# bits */ 945 if (idcode[0] == SPI_FLASH_CFI_MFR_ATMEL || 946 idcode[0] == SPI_FLASH_CFI_MFR_MACRONIX || 947 idcode[0] == SPI_FLASH_CFI_MFR_SST) 948 write_sr(flash, 0); 949 950 /* Assign spi data */ 951 flash->name = params->name; 952 flash->memory_map = spi->memory_map; 953 flash->dual_flash = flash->spi->option; 954 955 /* Assign spi flash flags */ 956 if (params->flags & SST_WR) 957 flash->flags |= SNOR_F_SST_WR; 958 959 /* Assign spi_flash ops */ 960 #ifndef CONFIG_DM_SPI_FLASH 961 flash->write = spi_flash_cmd_write_ops; 962 #if defined(CONFIG_SPI_FLASH_SST) 963 if (flash->flags & SNOR_F_SST_WR) { 964 if (flash->spi->op_mode_tx & SPI_OPM_TX_BP) 965 flash->write = sst_write_bp; 966 else 967 flash->write = sst_write_wp; 968 } 969 #endif 970 flash->erase = spi_flash_cmd_erase_ops; 971 flash->read = spi_flash_cmd_read_ops; 972 #endif 973 974 /* lock hooks are flash specific - assign them based on idcode0 */ 975 switch (idcode[0]) { 976 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) 977 case SPI_FLASH_CFI_MFR_STMICRO: 978 case SPI_FLASH_CFI_MFR_SST: 979 flash->flash_lock = stm_lock; 980 flash->flash_unlock = stm_unlock; 981 flash->flash_is_locked = stm_is_locked; 982 #endif 983 break; 984 default: 985 debug("SF: Lock ops not supported for %02x flash\n", idcode[0]); 986 } 987 988 /* Compute the flash size */ 989 flash->shift = (flash->dual_flash & SF_DUAL_PARALLEL_FLASH) ? 1 : 0; 990 /* 991 * The Spansion S25FL032P and S25FL064P have 256b pages, yet use the 992 * 0x4d00 Extended JEDEC code. The rest of the Spansion flashes with 993 * the 0x4d00 Extended JEDEC code have 512b pages. All of the others 994 * have 256b pages. 995 */ 996 if (ext_jedec == 0x4d00) { 997 if ((jedec == 0x0215) || (jedec == 0x216)) 998 flash->page_size = 256; 999 else 1000 flash->page_size = 512; 1001 } else { 1002 flash->page_size = 256; 1003 } 1004 flash->page_size <<= flash->shift; 1005 flash->sector_size = params->sector_size << flash->shift; 1006 flash->size = flash->sector_size * params->nr_sectors << flash->shift; 1007 #ifdef CONFIG_SF_DUAL_FLASH 1008 if (flash->dual_flash & SF_DUAL_STACKED_FLASH) 1009 flash->size <<= 1; 1010 #endif 1011 1012 /* Compute erase sector and command */ 1013 if (params->flags & SECT_4K) { 1014 flash->erase_cmd = CMD_ERASE_4K; 1015 flash->erase_size = 4096 << flash->shift; 1016 } else if (params->flags & SECT_32K) { 1017 flash->erase_cmd = CMD_ERASE_32K; 1018 flash->erase_size = 32768 << flash->shift; 1019 } else { 1020 flash->erase_cmd = CMD_ERASE_64K; 1021 flash->erase_size = flash->sector_size; 1022 } 1023 1024 /* Now erase size becomes valid sector size */ 1025 flash->sector_size = flash->erase_size; 1026 1027 /* Look for the fastest read cmd */ 1028 cmd = fls(params->e_rd_cmd & flash->spi->op_mode_rx); 1029 if (cmd) { 1030 cmd = spi_read_cmds_array[cmd - 1]; 1031 flash->read_cmd = cmd; 1032 } else { 1033 /* Go for default supported read cmd */ 1034 flash->read_cmd = CMD_READ_ARRAY_FAST; 1035 } 1036 1037 /* Not require to look for fastest only two write cmds yet */ 1038 if (params->flags & WR_QPP && flash->spi->op_mode_tx & SPI_OPM_TX_QPP) 1039 flash->write_cmd = CMD_QUAD_PAGE_PROGRAM; 1040 else 1041 /* Go for default supported write cmd */ 1042 flash->write_cmd = CMD_PAGE_PROGRAM; 1043 1044 /* Set the quad enable bit - only for quad commands */ 1045 if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) || 1046 (flash->read_cmd == CMD_READ_QUAD_IO_FAST) || 1047 (flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) { 1048 ret = spi_flash_set_qeb(flash, idcode[0]); 1049 if (ret) { 1050 debug("SF: Fail to set QEB for %02x\n", idcode[0]); 1051 return -EINVAL; 1052 } 1053 } 1054 1055 /* Read dummy_byte: dummy byte is determined based on the 1056 * dummy cycles of a particular command. 1057 * Fast commands - dummy_byte = dummy_cycles/8 1058 * I/O commands- dummy_byte = (dummy_cycles * no.of lines)/8 1059 * For I/O commands except cmd[0] everything goes on no.of lines 1060 * based on particular command but incase of fast commands except 1061 * data all go on single line irrespective of command. 1062 */ 1063 switch (flash->read_cmd) { 1064 case CMD_READ_QUAD_IO_FAST: 1065 flash->dummy_byte = 2; 1066 break; 1067 case CMD_READ_ARRAY_SLOW: 1068 flash->dummy_byte = 0; 1069 break; 1070 default: 1071 flash->dummy_byte = 1; 1072 } 1073 1074 #ifdef CONFIG_SPI_FLASH_STMICRO 1075 if (params->flags & E_FSR) 1076 flash->flags |= SNOR_F_USE_FSR; 1077 #endif 1078 1079 /* Configure the BAR - discover bank cmds and read current bank */ 1080 #ifdef CONFIG_SPI_FLASH_BAR 1081 ret = spi_flash_read_bar(flash, idcode[0]); 1082 if (ret < 0) 1083 return ret; 1084 #endif 1085 1086 #if CONFIG_IS_ENABLED(OF_CONTROL) 1087 ret = spi_flash_decode_fdt(gd->fdt_blob, flash); 1088 if (ret) { 1089 debug("SF: FDT decode error\n"); 1090 return -EINVAL; 1091 } 1092 #endif 1093 1094 #ifndef CONFIG_SPL_BUILD 1095 printf("SF: Detected %s with page size ", flash->name); 1096 print_size(flash->page_size, ", erase size "); 1097 print_size(flash->erase_size, ", total "); 1098 print_size(flash->size, ""); 1099 if (flash->memory_map) 1100 printf(", mapped at %p", flash->memory_map); 1101 puts("\n"); 1102 #endif 1103 1104 #ifndef CONFIG_SPI_FLASH_BAR 1105 if (((flash->dual_flash == SF_SINGLE_FLASH) && 1106 (flash->size > SPI_FLASH_16MB_BOUN)) || 1107 ((flash->dual_flash > SF_SINGLE_FLASH) && 1108 (flash->size > SPI_FLASH_16MB_BOUN << 1))) { 1109 puts("SF: Warning - Only lower 16MiB accessible,"); 1110 puts(" Full access #define CONFIG_SPI_FLASH_BAR\n"); 1111 } 1112 #endif 1113 1114 return ret; 1115 } 1116