1 /* 2 * SPI flash interface 3 * 4 * Copyright (C) 2008 Atmel Corporation 5 * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik 6 * 7 * Licensed under the GPL-2 or later. 8 */ 9 10 #include <common.h> 11 #include <fdtdec.h> 12 #include <malloc.h> 13 #include <spi.h> 14 #include <spi_flash.h> 15 #include <watchdog.h> 16 17 #include "spi_flash_internal.h" 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 static void spi_flash_addr(u32 addr, u8 *cmd) 22 { 23 /* cmd[0] is actual command */ 24 cmd[1] = addr >> 16; 25 cmd[2] = addr >> 8; 26 cmd[3] = addr >> 0; 27 } 28 29 static int spi_flash_read_write(struct spi_slave *spi, 30 const u8 *cmd, size_t cmd_len, 31 const u8 *data_out, u8 *data_in, 32 size_t data_len) 33 { 34 unsigned long flags = SPI_XFER_BEGIN; 35 int ret; 36 37 if (data_len == 0) 38 flags |= SPI_XFER_END; 39 40 ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags); 41 if (ret) { 42 debug("SF: Failed to send command (%zu bytes): %d\n", 43 cmd_len, ret); 44 } else if (data_len != 0) { 45 ret = spi_xfer(spi, data_len * 8, data_out, data_in, SPI_XFER_END); 46 if (ret) 47 debug("SF: Failed to transfer %zu bytes of data: %d\n", 48 data_len, ret); 49 } 50 51 return ret; 52 } 53 54 int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len) 55 { 56 return spi_flash_cmd_read(spi, &cmd, 1, response, len); 57 } 58 59 int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd, 60 size_t cmd_len, void *data, size_t data_len) 61 { 62 return spi_flash_read_write(spi, cmd, cmd_len, NULL, data, data_len); 63 } 64 65 int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, 66 const void *data, size_t data_len) 67 { 68 return spi_flash_read_write(spi, cmd, cmd_len, data, NULL, data_len); 69 } 70 71 int spi_flash_cmd_write_multi(struct spi_flash *flash, u32 offset, 72 size_t len, const void *buf) 73 { 74 unsigned long byte_addr, page_size; 75 size_t chunk_len, actual; 76 int ret; 77 u8 cmd[4]; 78 79 page_size = flash->page_size; 80 81 ret = spi_claim_bus(flash->spi); 82 if (ret) { 83 debug("SF: unable to claim SPI bus\n"); 84 return ret; 85 } 86 87 cmd[0] = CMD_PAGE_PROGRAM; 88 for (actual = 0; actual < len; actual += chunk_len) { 89 #ifdef CONFIG_SPI_FLASH_BAR 90 u8 bank_sel; 91 92 bank_sel = offset / SPI_FLASH_16MB_BOUN; 93 94 ret = spi_flash_cmd_bankaddr_write(flash, bank_sel); 95 if (ret) { 96 debug("SF: fail to set bank%d\n", bank_sel); 97 return ret; 98 } 99 #endif 100 byte_addr = offset % page_size; 101 chunk_len = min(len - actual, page_size - byte_addr); 102 103 if (flash->spi->max_write_size) 104 chunk_len = min(chunk_len, flash->spi->max_write_size); 105 106 spi_flash_addr(offset, cmd); 107 108 debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", 109 buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); 110 111 ret = spi_flash_cmd_write_enable(flash); 112 if (ret < 0) { 113 debug("SF: enabling write failed\n"); 114 break; 115 } 116 117 ret = spi_flash_cmd_write(flash->spi, cmd, 4, 118 buf + actual, chunk_len); 119 if (ret < 0) { 120 debug("SF: write failed\n"); 121 break; 122 } 123 124 ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); 125 if (ret) 126 break; 127 128 offset += chunk_len; 129 } 130 131 spi_release_bus(flash->spi); 132 return ret; 133 } 134 135 int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, 136 size_t cmd_len, void *data, size_t data_len) 137 { 138 struct spi_slave *spi = flash->spi; 139 int ret; 140 141 spi_claim_bus(spi); 142 ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len); 143 spi_release_bus(spi); 144 145 return ret; 146 } 147 148 int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset, 149 size_t len, void *data) 150 { 151 u8 cmd[5], bank_sel = 0; 152 u32 remain_len, read_len; 153 int ret = -1; 154 155 /* Handle memory-mapped SPI */ 156 if (flash->memory_map) { 157 memcpy(data, flash->memory_map + offset, len); 158 return 0; 159 } 160 161 cmd[0] = CMD_READ_ARRAY_FAST; 162 cmd[4] = 0x00; 163 164 while (len) { 165 #ifdef CONFIG_SPI_FLASH_BAR 166 bank_sel = offset / SPI_FLASH_16MB_BOUN; 167 168 ret = spi_flash_cmd_bankaddr_write(flash, bank_sel); 169 if (ret) { 170 debug("SF: fail to set bank%d\n", bank_sel); 171 return ret; 172 } 173 #endif 174 remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1) - offset); 175 if (len < remain_len) 176 read_len = len; 177 else 178 read_len = remain_len; 179 180 spi_flash_addr(offset, cmd); 181 182 ret = spi_flash_read_common(flash, cmd, sizeof(cmd), 183 data, read_len); 184 if (ret < 0) { 185 debug("SF: read failed\n"); 186 break; 187 } 188 189 offset += read_len; 190 len -= read_len; 191 data += read_len; 192 } 193 194 return ret; 195 } 196 197 int spi_flash_cmd_poll_bit(struct spi_flash *flash, unsigned long timeout, 198 u8 cmd, u8 poll_bit) 199 { 200 struct spi_slave *spi = flash->spi; 201 unsigned long timebase; 202 int ret; 203 u8 status; 204 205 ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN); 206 if (ret) { 207 debug("SF: Failed to send command %02x: %d\n", cmd, ret); 208 return ret; 209 } 210 211 timebase = get_timer(0); 212 do { 213 WATCHDOG_RESET(); 214 215 ret = spi_xfer(spi, 8, NULL, &status, 0); 216 if (ret) 217 return -1; 218 219 if ((status & poll_bit) == 0) 220 break; 221 222 } while (get_timer(timebase) < timeout); 223 224 spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END); 225 226 if ((status & poll_bit) == 0) 227 return 0; 228 229 /* Timed out */ 230 debug("SF: time out!\n"); 231 return -1; 232 } 233 234 int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout) 235 { 236 return spi_flash_cmd_poll_bit(flash, timeout, 237 CMD_READ_STATUS, STATUS_WIP); 238 } 239 240 int spi_flash_cmd_erase(struct spi_flash *flash, u32 offset, size_t len) 241 { 242 u32 erase_size; 243 int ret; 244 u8 cmd[4]; 245 246 erase_size = flash->sector_size; 247 if (offset % erase_size || len % erase_size) { 248 debug("SF: Erase offset/length not multiple of erase size\n"); 249 return -1; 250 } 251 252 ret = spi_claim_bus(flash->spi); 253 if (ret) { 254 debug("SF: Unable to claim SPI bus\n"); 255 return ret; 256 } 257 258 if (erase_size == 4096) 259 cmd[0] = CMD_ERASE_4K; 260 else 261 cmd[0] = CMD_ERASE_64K; 262 263 while (len) { 264 #ifdef CONFIG_SPI_FLASH_BAR 265 u8 bank_sel; 266 267 bank_sel = offset / SPI_FLASH_16MB_BOUN; 268 269 ret = spi_flash_cmd_bankaddr_write(flash, bank_sel); 270 if (ret) { 271 debug("SF: fail to set bank%d\n", bank_sel); 272 return ret; 273 } 274 #endif 275 spi_flash_addr(offset, cmd); 276 277 debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1], 278 cmd[2], cmd[3], offset); 279 280 ret = spi_flash_cmd_write_enable(flash); 281 if (ret) 282 goto out; 283 284 ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), NULL, 0); 285 if (ret) 286 goto out; 287 288 ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PAGE_ERASE_TIMEOUT); 289 if (ret) 290 goto out; 291 292 offset += erase_size; 293 len -= erase_size; 294 } 295 296 out: 297 spi_release_bus(flash->spi); 298 return ret; 299 } 300 301 int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr) 302 { 303 u8 cmd; 304 int ret; 305 306 ret = spi_flash_cmd_write_enable(flash); 307 if (ret < 0) { 308 debug("SF: enabling write failed\n"); 309 return ret; 310 } 311 312 cmd = CMD_WRITE_STATUS; 313 ret = spi_flash_cmd_write(flash->spi, &cmd, 1, &sr, 1); 314 if (ret) { 315 debug("SF: fail to write status register\n"); 316 return ret; 317 } 318 319 ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); 320 if (ret < 0) { 321 debug("SF: write status register timed out\n"); 322 return ret; 323 } 324 325 return 0; 326 } 327 328 #ifdef CONFIG_SPI_FLASH_BAR 329 int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel) 330 { 331 u8 cmd; 332 int ret; 333 334 if (flash->bank_curr == bank_sel) { 335 debug("SF: not require to enable bank%d\n", bank_sel); 336 return 0; 337 } 338 339 cmd = flash->bank_write_cmd; 340 ret = spi_flash_cmd_write_enable(flash); 341 if (ret < 0) { 342 debug("SF: enabling write failed\n"); 343 return ret; 344 } 345 346 ret = spi_flash_cmd_write(flash->spi, &cmd, 1, &bank_sel, 1); 347 if (ret) { 348 debug("SF: fail to write bank addr register\n"); 349 return ret; 350 } 351 flash->bank_curr = bank_sel; 352 353 ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); 354 if (ret < 0) { 355 debug("SF: write bank addr register timed out\n"); 356 return ret; 357 } 358 359 return 0; 360 } 361 362 int spi_flash_bank_config(struct spi_flash *flash, u8 idcode0) 363 { 364 u8 cmd; 365 u8 curr_bank = 0; 366 367 /* discover bank cmds */ 368 switch (idcode0) { 369 case SPI_FLASH_SPANSION_IDCODE0: 370 flash->bank_read_cmd = CMD_BANKADDR_BRRD; 371 flash->bank_write_cmd = CMD_BANKADDR_BRWR; 372 break; 373 case SPI_FLASH_STMICRO_IDCODE0: 374 case SPI_FLASH_WINBOND_IDCODE0: 375 flash->bank_read_cmd = CMD_EXTNADDR_RDEAR; 376 flash->bank_write_cmd = CMD_EXTNADDR_WREAR; 377 break; 378 default: 379 printf("SF: Unsupported bank commands %02x\n", idcode0); 380 return -1; 381 } 382 383 /* read the bank reg - on which bank the flash is in currently */ 384 cmd = flash->bank_read_cmd; 385 if (flash->size > SPI_FLASH_16MB_BOUN) { 386 if (spi_flash_read_common(flash, &cmd, 1, &curr_bank, 1)) { 387 debug("SF: fail to read bank addr register\n"); 388 return -1; 389 } 390 flash->bank_curr = curr_bank; 391 } else { 392 flash->bank_curr = curr_bank; 393 } 394 395 return 0; 396 } 397 #endif 398 399 #ifdef CONFIG_OF_CONTROL 400 int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash) 401 { 402 fdt_addr_t addr; 403 fdt_size_t size; 404 int node; 405 406 /* If there is no node, do nothing */ 407 node = fdtdec_next_compatible(blob, 0, COMPAT_GENERIC_SPI_FLASH); 408 if (node < 0) 409 return 0; 410 411 addr = fdtdec_get_addr_size(blob, node, "memory-map", &size); 412 if (addr == FDT_ADDR_T_NONE) { 413 debug("%s: Cannot decode address\n", __func__); 414 return 0; 415 } 416 417 if (flash->size != size) { 418 debug("%s: Memory map must cover entire device\n", __func__); 419 return -1; 420 } 421 flash->memory_map = (void *)addr; 422 423 return 0; 424 } 425 #endif /* CONFIG_OF_CONTROL */ 426 427 /* 428 * The following table holds all device probe functions 429 * 430 * shift: number of continuation bytes before the ID 431 * idcode: the expected IDCODE or 0xff for non JEDEC devices 432 * probe: the function to call 433 * 434 * Non JEDEC devices should be ordered in the table such that 435 * the probe functions with best detection algorithms come first. 436 * 437 * Several matching entries are permitted, they will be tried 438 * in sequence until a probe function returns non NULL. 439 * 440 * IDCODE_CONT_LEN may be redefined if a device needs to declare a 441 * larger "shift" value. IDCODE_PART_LEN generally shouldn't be 442 * changed. This is the max number of bytes probe functions may 443 * examine when looking up part-specific identification info. 444 * 445 * Probe functions will be given the idcode buffer starting at their 446 * manu id byte (the "idcode" in the table below). In other words, 447 * all of the continuation bytes will be skipped (the "shift" below). 448 */ 449 #define IDCODE_CONT_LEN 0 450 #define IDCODE_PART_LEN 5 451 static const struct { 452 const u8 shift; 453 const u8 idcode; 454 struct spi_flash *(*probe) (struct spi_slave *spi, u8 *idcode); 455 } flashes[] = { 456 /* Keep it sorted by define name */ 457 #ifdef CONFIG_SPI_FLASH_ATMEL 458 { 0, 0x1f, spi_flash_probe_atmel, }, 459 #endif 460 #ifdef CONFIG_SPI_FLASH_EON 461 { 0, 0x1c, spi_flash_probe_eon, }, 462 #endif 463 #ifdef CONFIG_SPI_FLASH_MACRONIX 464 { 0, 0xc2, spi_flash_probe_macronix, }, 465 #endif 466 #ifdef CONFIG_SPI_FLASH_SPANSION 467 { 0, 0x01, spi_flash_probe_spansion, }, 468 #endif 469 #ifdef CONFIG_SPI_FLASH_SST 470 { 0, 0xbf, spi_flash_probe_sst, }, 471 #endif 472 #ifdef CONFIG_SPI_FLASH_STMICRO 473 { 0, 0x20, spi_flash_probe_stmicro, }, 474 #endif 475 #ifdef CONFIG_SPI_FLASH_WINBOND 476 { 0, 0xef, spi_flash_probe_winbond, }, 477 #endif 478 #ifdef CONFIG_SPI_FRAM_RAMTRON 479 { 6, 0xc2, spi_fram_probe_ramtron, }, 480 # undef IDCODE_CONT_LEN 481 # define IDCODE_CONT_LEN 6 482 #endif 483 /* Keep it sorted by best detection */ 484 #ifdef CONFIG_SPI_FLASH_STMICRO 485 { 0, 0xff, spi_flash_probe_stmicro, }, 486 #endif 487 #ifdef CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC 488 { 0, 0xff, spi_fram_probe_ramtron, }, 489 #endif 490 }; 491 #define IDCODE_LEN (IDCODE_CONT_LEN + IDCODE_PART_LEN) 492 493 struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, 494 unsigned int max_hz, unsigned int spi_mode) 495 { 496 struct spi_slave *spi; 497 struct spi_flash *flash = NULL; 498 int ret, i, shift; 499 u8 idcode[IDCODE_LEN], *idp; 500 501 spi = spi_setup_slave(bus, cs, max_hz, spi_mode); 502 if (!spi) { 503 printf("SF: Failed to set up slave\n"); 504 return NULL; 505 } 506 507 ret = spi_claim_bus(spi); 508 if (ret) { 509 debug("SF: Failed to claim SPI bus: %d\n", ret); 510 goto err_claim_bus; 511 } 512 513 /* Read the ID codes */ 514 ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode)); 515 if (ret) 516 goto err_read_id; 517 518 #ifdef DEBUG 519 printf("SF: Got idcodes\n"); 520 print_buffer(0, idcode, 1, sizeof(idcode), 0); 521 #endif 522 523 /* count the number of continuation bytes */ 524 for (shift = 0, idp = idcode; 525 shift < IDCODE_CONT_LEN && *idp == 0x7f; 526 ++shift, ++idp) 527 continue; 528 529 /* search the table for matches in shift and id */ 530 for (i = 0; i < ARRAY_SIZE(flashes); ++i) 531 if (flashes[i].shift == shift && flashes[i].idcode == *idp) { 532 /* we have a match, call probe */ 533 flash = flashes[i].probe(spi, idp); 534 if (flash) 535 break; 536 } 537 538 if (!flash) { 539 printf("SF: Unsupported manufacturer %02x\n", *idp); 540 goto err_manufacturer_probe; 541 } 542 543 #ifdef CONFIG_SPI_FLASH_BAR 544 /* Configure the BAR - disover bank cmds and read current bank */ 545 ret = spi_flash_bank_config(flash, *idp); 546 if (ret < 0) 547 goto err_manufacturer_probe; 548 #endif 549 550 #ifdef CONFIG_OF_CONTROL 551 if (spi_flash_decode_fdt(gd->fdt_blob, flash)) { 552 debug("SF: FDT decode error\n"); 553 goto err_manufacturer_probe; 554 } 555 #endif 556 printf("SF: Detected %s with page size ", flash->name); 557 print_size(flash->sector_size, ", total "); 558 print_size(flash->size, ""); 559 if (flash->memory_map) 560 printf(", mapped at %p", flash->memory_map); 561 puts("\n"); 562 563 spi_release_bus(spi); 564 565 return flash; 566 567 err_manufacturer_probe: 568 err_read_id: 569 spi_release_bus(spi); 570 err_claim_bus: 571 spi_free_slave(spi); 572 return NULL; 573 } 574 575 void *spi_flash_do_alloc(int offset, int size, struct spi_slave *spi, 576 const char *name) 577 { 578 struct spi_flash *flash; 579 void *ptr; 580 581 ptr = malloc(size); 582 if (!ptr) { 583 debug("SF: Failed to allocate memory\n"); 584 return NULL; 585 } 586 memset(ptr, '\0', size); 587 flash = (struct spi_flash *)(ptr + offset); 588 589 /* Set up some basic fields - caller will sort out sizes */ 590 flash->spi = spi; 591 flash->name = name; 592 593 flash->read = spi_flash_cmd_read_fast; 594 flash->write = spi_flash_cmd_write_multi; 595 flash->erase = spi_flash_cmd_erase; 596 597 return flash; 598 } 599 600 void spi_flash_free(struct spi_flash *flash) 601 { 602 spi_free_slave(flash->spi); 603 free(flash); 604 } 605