1 /* 2 * SPI flash interface 3 * 4 * Copyright (C) 2008 Atmel Corporation 5 * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik 6 * 7 * Licensed under the GPL-2 or later. 8 */ 9 10 #include <common.h> 11 #include <fdtdec.h> 12 #include <malloc.h> 13 #include <spi.h> 14 #include <spi_flash.h> 15 #include <watchdog.h> 16 17 #include "spi_flash_internal.h" 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 static void spi_flash_addr(u32 addr, u8 *cmd) 22 { 23 /* cmd[0] is actual command */ 24 cmd[1] = addr >> 16; 25 cmd[2] = addr >> 8; 26 cmd[3] = addr >> 0; 27 } 28 29 static int spi_flash_read_write(struct spi_slave *spi, 30 const u8 *cmd, size_t cmd_len, 31 const u8 *data_out, u8 *data_in, 32 size_t data_len) 33 { 34 unsigned long flags = SPI_XFER_BEGIN; 35 int ret; 36 37 if (data_len == 0) 38 flags |= SPI_XFER_END; 39 40 ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags); 41 if (ret) { 42 debug("SF: Failed to send command (%zu bytes): %d\n", 43 cmd_len, ret); 44 } else if (data_len != 0) { 45 ret = spi_xfer(spi, data_len * 8, data_out, data_in, SPI_XFER_END); 46 if (ret) 47 debug("SF: Failed to transfer %zu bytes of data: %d\n", 48 data_len, ret); 49 } 50 51 return ret; 52 } 53 54 int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len) 55 { 56 return spi_flash_cmd_read(spi, &cmd, 1, response, len); 57 } 58 59 int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd, 60 size_t cmd_len, void *data, size_t data_len) 61 { 62 return spi_flash_read_write(spi, cmd, cmd_len, NULL, data, data_len); 63 } 64 65 int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, 66 const void *data, size_t data_len) 67 { 68 return spi_flash_read_write(spi, cmd, cmd_len, data, NULL, data_len); 69 } 70 71 int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout) 72 { 73 struct spi_slave *spi = flash->spi; 74 unsigned long timebase; 75 int ret; 76 u8 status; 77 u8 check_status = 0x0; 78 u8 poll_bit = STATUS_WIP; 79 u8 cmd = flash->poll_cmd; 80 81 if (cmd == CMD_FLAG_STATUS) { 82 poll_bit = STATUS_PEC; 83 check_status = poll_bit; 84 } 85 86 ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN); 87 if (ret) { 88 debug("SF: fail to read %s status register\n", 89 cmd == CMD_READ_STATUS ? "read" : "flag"); 90 return ret; 91 } 92 93 timebase = get_timer(0); 94 do { 95 WATCHDOG_RESET(); 96 97 ret = spi_xfer(spi, 8, NULL, &status, 0); 98 if (ret) 99 return -1; 100 101 if ((status & poll_bit) == check_status) 102 break; 103 104 } while (get_timer(timebase) < timeout); 105 106 spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END); 107 108 if ((status & poll_bit) == check_status) 109 return 0; 110 111 /* Timed out */ 112 debug("SF: time out!\n"); 113 return -1; 114 } 115 116 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, 117 size_t cmd_len, const void *buf, size_t buf_len) 118 { 119 struct spi_slave *spi = flash->spi; 120 unsigned long timeout = SPI_FLASH_PROG_TIMEOUT; 121 int ret; 122 123 if (buf == NULL) 124 timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT; 125 126 ret = spi_claim_bus(flash->spi); 127 if (ret) { 128 debug("SF: unable to claim SPI bus\n"); 129 return ret; 130 } 131 132 ret = spi_flash_cmd_write_enable(flash); 133 if (ret < 0) { 134 debug("SF: enabling write failed\n"); 135 return ret; 136 } 137 138 ret = spi_flash_cmd_write(spi, cmd, cmd_len, buf, buf_len); 139 if (ret < 0) { 140 debug("SF: write cmd failed\n"); 141 return ret; 142 } 143 144 ret = spi_flash_cmd_wait_ready(flash, timeout); 145 if (ret < 0) { 146 debug("SF: write %s timed out\n", 147 timeout == SPI_FLASH_PROG_TIMEOUT ? 148 "program" : "page erase"); 149 return ret; 150 } 151 152 spi_release_bus(spi); 153 154 return ret; 155 } 156 157 int spi_flash_cmd_erase(struct spi_flash *flash, u32 offset, size_t len) 158 { 159 u32 erase_size; 160 u8 cmd[4]; 161 int ret = -1; 162 163 erase_size = flash->sector_size; 164 if (offset % erase_size || len % erase_size) { 165 debug("SF: Erase offset/length not multiple of erase size\n"); 166 return -1; 167 } 168 169 if (erase_size == 4096) 170 cmd[0] = CMD_ERASE_4K; 171 else 172 cmd[0] = CMD_ERASE_64K; 173 174 while (len) { 175 #ifdef CONFIG_SPI_FLASH_BAR 176 u8 bank_sel; 177 178 bank_sel = offset / SPI_FLASH_16MB_BOUN; 179 180 ret = spi_flash_cmd_bankaddr_write(flash, bank_sel); 181 if (ret) { 182 debug("SF: fail to set bank%d\n", bank_sel); 183 return ret; 184 } 185 #endif 186 spi_flash_addr(offset, cmd); 187 188 debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1], 189 cmd[2], cmd[3], offset); 190 191 ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0); 192 if (ret < 0) { 193 debug("SF: erase failed\n"); 194 break; 195 } 196 197 offset += erase_size; 198 len -= erase_size; 199 } 200 201 return ret; 202 } 203 204 int spi_flash_cmd_write_multi(struct spi_flash *flash, u32 offset, 205 size_t len, const void *buf) 206 { 207 unsigned long byte_addr, page_size; 208 size_t chunk_len, actual; 209 u8 cmd[4]; 210 int ret = -1; 211 212 page_size = flash->page_size; 213 214 cmd[0] = CMD_PAGE_PROGRAM; 215 for (actual = 0; actual < len; actual += chunk_len) { 216 #ifdef CONFIG_SPI_FLASH_BAR 217 u8 bank_sel; 218 219 bank_sel = offset / SPI_FLASH_16MB_BOUN; 220 221 ret = spi_flash_cmd_bankaddr_write(flash, bank_sel); 222 if (ret) { 223 debug("SF: fail to set bank%d\n", bank_sel); 224 return ret; 225 } 226 #endif 227 byte_addr = offset % page_size; 228 chunk_len = min(len - actual, page_size - byte_addr); 229 230 if (flash->spi->max_write_size) 231 chunk_len = min(chunk_len, flash->spi->max_write_size); 232 233 spi_flash_addr(offset, cmd); 234 235 debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", 236 buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); 237 238 ret = spi_flash_write_common(flash, cmd, sizeof(cmd), 239 buf + actual, chunk_len); 240 if (ret < 0) { 241 debug("SF: write failed\n"); 242 break; 243 } 244 245 offset += chunk_len; 246 } 247 248 return ret; 249 } 250 251 int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, 252 size_t cmd_len, void *data, size_t data_len) 253 { 254 struct spi_slave *spi = flash->spi; 255 int ret; 256 257 ret = spi_claim_bus(flash->spi); 258 if (ret) { 259 debug("SF: unable to claim SPI bus\n"); 260 return ret; 261 } 262 263 ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len); 264 if (ret < 0) { 265 debug("SF: read cmd failed\n"); 266 return ret; 267 } 268 269 spi_release_bus(spi); 270 271 return ret; 272 } 273 274 int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset, 275 size_t len, void *data) 276 { 277 u8 cmd[5], bank_sel = 0; 278 u32 remain_len, read_len; 279 int ret = -1; 280 281 /* Handle memory-mapped SPI */ 282 if (flash->memory_map) { 283 memcpy(data, flash->memory_map + offset, len); 284 return 0; 285 } 286 287 cmd[0] = CMD_READ_ARRAY_FAST; 288 cmd[4] = 0x00; 289 290 while (len) { 291 #ifdef CONFIG_SPI_FLASH_BAR 292 bank_sel = offset / SPI_FLASH_16MB_BOUN; 293 294 ret = spi_flash_cmd_bankaddr_write(flash, bank_sel); 295 if (ret) { 296 debug("SF: fail to set bank%d\n", bank_sel); 297 return ret; 298 } 299 #endif 300 remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1) - offset); 301 if (len < remain_len) 302 read_len = len; 303 else 304 read_len = remain_len; 305 306 spi_flash_addr(offset, cmd); 307 308 ret = spi_flash_read_common(flash, cmd, sizeof(cmd), 309 data, read_len); 310 if (ret < 0) { 311 debug("SF: read failed\n"); 312 break; 313 } 314 315 offset += read_len; 316 len -= read_len; 317 data += read_len; 318 } 319 320 return ret; 321 } 322 323 int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr) 324 { 325 u8 cmd; 326 int ret; 327 328 cmd = CMD_WRITE_STATUS; 329 ret = spi_flash_write_common(flash, &cmd, 1, &sr, 1); 330 if (ret < 0) { 331 debug("SF: fail to write status register\n"); 332 return ret; 333 } 334 335 return 0; 336 } 337 338 #ifdef CONFIG_SPI_FLASH_BAR 339 int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel) 340 { 341 u8 cmd; 342 int ret; 343 344 if (flash->bank_curr == bank_sel) { 345 debug("SF: not require to enable bank%d\n", bank_sel); 346 return 0; 347 } 348 349 cmd = flash->bank_write_cmd; 350 ret = spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1); 351 if (ret < 0) { 352 debug("SF: fail to write bank register\n"); 353 return ret; 354 } 355 flash->bank_curr = bank_sel; 356 357 return 0; 358 } 359 360 int spi_flash_bank_config(struct spi_flash *flash, u8 idcode0) 361 { 362 u8 cmd; 363 u8 curr_bank = 0; 364 365 /* discover bank cmds */ 366 switch (idcode0) { 367 case SPI_FLASH_SPANSION_IDCODE0: 368 flash->bank_read_cmd = CMD_BANKADDR_BRRD; 369 flash->bank_write_cmd = CMD_BANKADDR_BRWR; 370 break; 371 case SPI_FLASH_STMICRO_IDCODE0: 372 case SPI_FLASH_WINBOND_IDCODE0: 373 flash->bank_read_cmd = CMD_EXTNADDR_RDEAR; 374 flash->bank_write_cmd = CMD_EXTNADDR_WREAR; 375 break; 376 default: 377 printf("SF: Unsupported bank commands %02x\n", idcode0); 378 return -1; 379 } 380 381 /* read the bank reg - on which bank the flash is in currently */ 382 cmd = flash->bank_read_cmd; 383 if (flash->size > SPI_FLASH_16MB_BOUN) { 384 if (spi_flash_read_common(flash, &cmd, 1, &curr_bank, 1)) { 385 debug("SF: fail to read bank addr register\n"); 386 return -1; 387 } 388 flash->bank_curr = curr_bank; 389 } else { 390 flash->bank_curr = curr_bank; 391 } 392 393 return 0; 394 } 395 #endif 396 397 #ifdef CONFIG_OF_CONTROL 398 int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash) 399 { 400 fdt_addr_t addr; 401 fdt_size_t size; 402 int node; 403 404 /* If there is no node, do nothing */ 405 node = fdtdec_next_compatible(blob, 0, COMPAT_GENERIC_SPI_FLASH); 406 if (node < 0) 407 return 0; 408 409 addr = fdtdec_get_addr_size(blob, node, "memory-map", &size); 410 if (addr == FDT_ADDR_T_NONE) { 411 debug("%s: Cannot decode address\n", __func__); 412 return 0; 413 } 414 415 if (flash->size != size) { 416 debug("%s: Memory map must cover entire device\n", __func__); 417 return -1; 418 } 419 flash->memory_map = (void *)addr; 420 421 return 0; 422 } 423 #endif /* CONFIG_OF_CONTROL */ 424 425 /* 426 * The following table holds all device probe functions 427 * 428 * shift: number of continuation bytes before the ID 429 * idcode: the expected IDCODE or 0xff for non JEDEC devices 430 * probe: the function to call 431 * 432 * Non JEDEC devices should be ordered in the table such that 433 * the probe functions with best detection algorithms come first. 434 * 435 * Several matching entries are permitted, they will be tried 436 * in sequence until a probe function returns non NULL. 437 * 438 * IDCODE_CONT_LEN may be redefined if a device needs to declare a 439 * larger "shift" value. IDCODE_PART_LEN generally shouldn't be 440 * changed. This is the max number of bytes probe functions may 441 * examine when looking up part-specific identification info. 442 * 443 * Probe functions will be given the idcode buffer starting at their 444 * manu id byte (the "idcode" in the table below). In other words, 445 * all of the continuation bytes will be skipped (the "shift" below). 446 */ 447 #define IDCODE_CONT_LEN 0 448 #define IDCODE_PART_LEN 5 449 static const struct { 450 const u8 shift; 451 const u8 idcode; 452 struct spi_flash *(*probe) (struct spi_slave *spi, u8 *idcode); 453 } flashes[] = { 454 /* Keep it sorted by define name */ 455 #ifdef CONFIG_SPI_FLASH_ATMEL 456 { 0, 0x1f, spi_flash_probe_atmel, }, 457 #endif 458 #ifdef CONFIG_SPI_FLASH_EON 459 { 0, 0x1c, spi_flash_probe_eon, }, 460 #endif 461 #ifdef CONFIG_SPI_FLASH_GIGADEVICE 462 { 0, 0xc8, spi_flash_probe_gigadevice, }, 463 #endif 464 #ifdef CONFIG_SPI_FLASH_MACRONIX 465 { 0, 0xc2, spi_flash_probe_macronix, }, 466 #endif 467 #ifdef CONFIG_SPI_FLASH_SPANSION 468 { 0, 0x01, spi_flash_probe_spansion, }, 469 #endif 470 #ifdef CONFIG_SPI_FLASH_SST 471 { 0, 0xbf, spi_flash_probe_sst, }, 472 #endif 473 #ifdef CONFIG_SPI_FLASH_STMICRO 474 { 0, 0x20, spi_flash_probe_stmicro, }, 475 #endif 476 #ifdef CONFIG_SPI_FLASH_WINBOND 477 { 0, 0xef, spi_flash_probe_winbond, }, 478 #endif 479 #ifdef CONFIG_SPI_FRAM_RAMTRON 480 { 6, 0xc2, spi_fram_probe_ramtron, }, 481 # undef IDCODE_CONT_LEN 482 # define IDCODE_CONT_LEN 6 483 #endif 484 /* Keep it sorted by best detection */ 485 #ifdef CONFIG_SPI_FLASH_STMICRO 486 { 0, 0xff, spi_flash_probe_stmicro, }, 487 #endif 488 #ifdef CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC 489 { 0, 0xff, spi_fram_probe_ramtron, }, 490 #endif 491 }; 492 #define IDCODE_LEN (IDCODE_CONT_LEN + IDCODE_PART_LEN) 493 494 struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, 495 unsigned int max_hz, unsigned int spi_mode) 496 { 497 struct spi_slave *spi; 498 struct spi_flash *flash = NULL; 499 int ret, i, shift; 500 u8 idcode[IDCODE_LEN], *idp; 501 502 spi = spi_setup_slave(bus, cs, max_hz, spi_mode); 503 if (!spi) { 504 printf("SF: Failed to set up slave\n"); 505 return NULL; 506 } 507 508 ret = spi_claim_bus(spi); 509 if (ret) { 510 debug("SF: Failed to claim SPI bus: %d\n", ret); 511 goto err_claim_bus; 512 } 513 514 /* Read the ID codes */ 515 ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode)); 516 if (ret) 517 goto err_read_id; 518 519 #ifdef DEBUG 520 printf("SF: Got idcodes\n"); 521 print_buffer(0, idcode, 1, sizeof(idcode), 0); 522 #endif 523 524 /* count the number of continuation bytes */ 525 for (shift = 0, idp = idcode; 526 shift < IDCODE_CONT_LEN && *idp == 0x7f; 527 ++shift, ++idp) 528 continue; 529 530 /* search the table for matches in shift and id */ 531 for (i = 0; i < ARRAY_SIZE(flashes); ++i) 532 if (flashes[i].shift == shift && flashes[i].idcode == *idp) { 533 /* we have a match, call probe */ 534 flash = flashes[i].probe(spi, idp); 535 if (flash) 536 break; 537 } 538 539 if (!flash) { 540 printf("SF: Unsupported manufacturer %02x\n", *idp); 541 goto err_manufacturer_probe; 542 } 543 544 #ifdef CONFIG_SPI_FLASH_BAR 545 /* Configure the BAR - disover bank cmds and read current bank */ 546 ret = spi_flash_bank_config(flash, *idp); 547 if (ret < 0) 548 goto err_manufacturer_probe; 549 #endif 550 551 #ifdef CONFIG_OF_CONTROL 552 if (spi_flash_decode_fdt(gd->fdt_blob, flash)) { 553 debug("SF: FDT decode error\n"); 554 goto err_manufacturer_probe; 555 } 556 #endif 557 printf("SF: Detected %s with page size ", flash->name); 558 print_size(flash->sector_size, ", total "); 559 print_size(flash->size, ""); 560 if (flash->memory_map) 561 printf(", mapped at %p", flash->memory_map); 562 puts("\n"); 563 #ifndef CONFIG_SPI_FLASH_BAR 564 if (flash->size > SPI_FLASH_16MB_BOUN) { 565 puts("SF: Warning - Only lower 16MiB accessible,"); 566 puts(" Full access #define CONFIG_SPI_FLASH_BAR\n"); 567 } 568 #endif 569 570 spi_release_bus(spi); 571 572 return flash; 573 574 err_manufacturer_probe: 575 err_read_id: 576 spi_release_bus(spi); 577 err_claim_bus: 578 spi_free_slave(spi); 579 return NULL; 580 } 581 582 void *spi_flash_do_alloc(int offset, int size, struct spi_slave *spi, 583 const char *name) 584 { 585 struct spi_flash *flash; 586 void *ptr; 587 588 ptr = malloc(size); 589 if (!ptr) { 590 debug("SF: Failed to allocate memory\n"); 591 return NULL; 592 } 593 memset(ptr, '\0', size); 594 flash = (struct spi_flash *)(ptr + offset); 595 596 /* Set up some basic fields - caller will sort out sizes */ 597 flash->spi = spi; 598 flash->name = name; 599 flash->poll_cmd = CMD_READ_STATUS; 600 601 flash->read = spi_flash_cmd_read_fast; 602 flash->write = spi_flash_cmd_write_multi; 603 flash->erase = spi_flash_cmd_erase; 604 605 return flash; 606 } 607 608 void spi_flash_free(struct spi_flash *flash) 609 { 610 spi_free_slave(flash->spi); 611 free(flash); 612 } 613