1 /* 2 * SPI Flash Core 3 * 4 * Copyright (C) 2015 Jagan Teki <jteki@openedev.com> 5 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. 6 * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik 7 * Copyright (C) 2008 Atmel Corporation 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <errno.h> 14 #include <malloc.h> 15 #include <mapmem.h> 16 #include <spi.h> 17 #include <spi_flash.h> 18 #include <linux/log2.h> 19 #include <dma.h> 20 21 #include "sf_internal.h" 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 static void spi_flash_addr(u32 addr, u8 *cmd) 26 { 27 /* cmd[0] is actual command */ 28 cmd[1] = addr >> 16; 29 cmd[2] = addr >> 8; 30 cmd[3] = addr >> 0; 31 } 32 33 static int read_sr(struct spi_flash *flash, u8 *rs) 34 { 35 int ret; 36 u8 cmd; 37 38 cmd = CMD_READ_STATUS; 39 ret = spi_flash_read_common(flash, &cmd, 1, rs, 1); 40 if (ret < 0) { 41 debug("SF: fail to read status register\n"); 42 return ret; 43 } 44 45 return 0; 46 } 47 48 static int read_fsr(struct spi_flash *flash, u8 *fsr) 49 { 50 int ret; 51 const u8 cmd = CMD_FLAG_STATUS; 52 53 ret = spi_flash_read_common(flash, &cmd, 1, fsr, 1); 54 if (ret < 0) { 55 debug("SF: fail to read flag status register\n"); 56 return ret; 57 } 58 59 return 0; 60 } 61 62 static int write_sr(struct spi_flash *flash, u8 ws) 63 { 64 u8 cmd; 65 int ret; 66 67 cmd = CMD_WRITE_STATUS; 68 ret = spi_flash_write_common(flash, &cmd, 1, &ws, 1); 69 if (ret < 0) { 70 debug("SF: fail to write status register\n"); 71 return ret; 72 } 73 74 return 0; 75 } 76 77 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 78 static int read_cr(struct spi_flash *flash, u8 *rc) 79 { 80 int ret; 81 u8 cmd; 82 83 cmd = CMD_READ_CONFIG; 84 ret = spi_flash_read_common(flash, &cmd, 1, rc, 1); 85 if (ret < 0) { 86 debug("SF: fail to read config register\n"); 87 return ret; 88 } 89 90 return 0; 91 } 92 93 static int write_cr(struct spi_flash *flash, u8 wc) 94 { 95 u8 data[2]; 96 u8 cmd; 97 int ret; 98 99 ret = read_sr(flash, &data[0]); 100 if (ret < 0) 101 return ret; 102 103 cmd = CMD_WRITE_STATUS; 104 data[1] = wc; 105 ret = spi_flash_write_common(flash, &cmd, 1, &data, 2); 106 if (ret) { 107 debug("SF: fail to write config register\n"); 108 return ret; 109 } 110 111 return 0; 112 } 113 #endif 114 115 #ifdef CONFIG_SPI_FLASH_STMICRO 116 static int read_evcr(struct spi_flash *flash, u8 *evcr) 117 { 118 int ret; 119 const u8 cmd = CMD_READ_EVCR; 120 121 ret = spi_flash_read_common(flash, &cmd, 1, evcr, 1); 122 if (ret < 0) { 123 debug("SF: error reading EVCR\n"); 124 return ret; 125 } 126 127 return 0; 128 } 129 130 static int write_evcr(struct spi_flash *flash, u8 evcr) 131 { 132 u8 cmd; 133 int ret; 134 135 cmd = CMD_WRITE_EVCR; 136 ret = spi_flash_write_common(flash, &cmd, 1, &evcr, 1); 137 if (ret < 0) { 138 debug("SF: error while writing EVCR register\n"); 139 return ret; 140 } 141 142 return 0; 143 } 144 #endif 145 146 #ifdef CONFIG_SPI_FLASH_BAR 147 static int spi_flash_write_bar(struct spi_flash *flash, u32 offset) 148 { 149 u8 cmd, bank_sel; 150 int ret; 151 152 bank_sel = offset / (SPI_FLASH_16MB_BOUN << flash->shift); 153 if (bank_sel == flash->bank_curr) 154 goto bar_end; 155 156 cmd = flash->bank_write_cmd; 157 ret = spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1); 158 if (ret < 0) { 159 debug("SF: fail to write bank register\n"); 160 return ret; 161 } 162 163 bar_end: 164 flash->bank_curr = bank_sel; 165 return flash->bank_curr; 166 } 167 168 static int spi_flash_read_bar(struct spi_flash *flash, u8 idcode0) 169 { 170 u8 curr_bank = 0; 171 int ret; 172 173 if (flash->size <= SPI_FLASH_16MB_BOUN) 174 goto bar_end; 175 176 switch (idcode0) { 177 case SPI_FLASH_CFI_MFR_SPANSION: 178 flash->bank_read_cmd = CMD_BANKADDR_BRRD; 179 flash->bank_write_cmd = CMD_BANKADDR_BRWR; 180 break; 181 default: 182 flash->bank_read_cmd = CMD_EXTNADDR_RDEAR; 183 flash->bank_write_cmd = CMD_EXTNADDR_WREAR; 184 } 185 186 ret = spi_flash_read_common(flash, &flash->bank_read_cmd, 1, 187 &curr_bank, 1); 188 if (ret) { 189 debug("SF: fail to read bank addr register\n"); 190 return ret; 191 } 192 193 bar_end: 194 flash->bank_curr = curr_bank; 195 return 0; 196 } 197 #endif 198 199 #ifdef CONFIG_SF_DUAL_FLASH 200 static void spi_flash_dual(struct spi_flash *flash, u32 *addr) 201 { 202 struct spi_slave *spi = flash->spi; 203 204 switch (flash->dual_flash) { 205 case SF_DUAL_STACKED_FLASH: 206 if (*addr >= (flash->size >> 1)) { 207 *addr -= flash->size >> 1; 208 spi->flags |= SPI_XFER_U_PAGE; 209 } else { 210 spi->flags &= ~SPI_XFER_U_PAGE; 211 } 212 break; 213 case SF_DUAL_PARALLEL_FLASH: 214 *addr >>= flash->shift; 215 break; 216 default: 217 debug("SF: Unsupported dual_flash=%d\n", flash->dual_flash); 218 break; 219 } 220 } 221 #endif 222 223 static int spi_flash_sr_ready(struct spi_flash *flash) 224 { 225 u8 sr; 226 int ret; 227 228 ret = read_sr(flash, &sr); 229 if (ret < 0) 230 return ret; 231 232 return !(sr & STATUS_WIP); 233 } 234 235 static int spi_flash_fsr_ready(struct spi_flash *flash) 236 { 237 u8 fsr; 238 int ret; 239 240 ret = read_fsr(flash, &fsr); 241 if (ret < 0) 242 return ret; 243 244 return fsr & STATUS_PEC; 245 } 246 247 static int spi_flash_ready(struct spi_flash *flash) 248 { 249 int sr, fsr; 250 251 sr = spi_flash_sr_ready(flash); 252 if (sr < 0) 253 return sr; 254 255 fsr = 1; 256 if (flash->flags & SNOR_F_USE_FSR) { 257 fsr = spi_flash_fsr_ready(flash); 258 if (fsr < 0) 259 return fsr; 260 } 261 262 return sr && fsr; 263 } 264 265 static int spi_flash_cmd_wait_ready(struct spi_flash *flash, 266 unsigned long timeout) 267 { 268 unsigned long timebase; 269 int ret; 270 271 timebase = get_timer(0); 272 273 while (get_timer(timebase) < timeout) { 274 ret = spi_flash_ready(flash); 275 if (ret < 0) 276 return ret; 277 if (ret) 278 return 0; 279 } 280 281 printf("SF: Timeout!\n"); 282 283 return -ETIMEDOUT; 284 } 285 286 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, 287 size_t cmd_len, const void *buf, size_t buf_len) 288 { 289 struct spi_slave *spi = flash->spi; 290 unsigned long timeout = SPI_FLASH_PROG_TIMEOUT; 291 int ret; 292 293 if (buf == NULL) 294 timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT; 295 296 ret = spi_claim_bus(spi); 297 if (ret) { 298 debug("SF: unable to claim SPI bus\n"); 299 return ret; 300 } 301 302 ret = spi_flash_cmd_write_enable(flash); 303 if (ret < 0) { 304 debug("SF: enabling write failed\n"); 305 return ret; 306 } 307 308 ret = spi_flash_cmd_write(spi, cmd, cmd_len, buf, buf_len); 309 if (ret < 0) { 310 debug("SF: write cmd failed\n"); 311 return ret; 312 } 313 314 ret = spi_flash_cmd_wait_ready(flash, timeout); 315 if (ret < 0) { 316 debug("SF: write %s timed out\n", 317 timeout == SPI_FLASH_PROG_TIMEOUT ? 318 "program" : "page erase"); 319 return ret; 320 } 321 322 spi_release_bus(spi); 323 324 return ret; 325 } 326 327 int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) 328 { 329 u32 erase_size, erase_addr; 330 u8 cmd[SPI_FLASH_CMD_LEN]; 331 int ret = -1; 332 333 erase_size = flash->erase_size; 334 if (offset % erase_size || len % erase_size) { 335 debug("SF: Erase offset/length not multiple of erase size\n"); 336 return -1; 337 } 338 339 if (flash->flash_is_locked) { 340 if (flash->flash_is_locked(flash, offset, len) > 0) { 341 printf("offset 0x%x is protected and cannot be erased\n", 342 offset); 343 return -EINVAL; 344 } 345 } 346 347 cmd[0] = flash->erase_cmd; 348 while (len) { 349 erase_addr = offset; 350 351 #ifdef CONFIG_SF_DUAL_FLASH 352 if (flash->dual_flash > SF_SINGLE_FLASH) 353 spi_flash_dual(flash, &erase_addr); 354 #endif 355 #ifdef CONFIG_SPI_FLASH_BAR 356 ret = spi_flash_write_bar(flash, erase_addr); 357 if (ret < 0) 358 return ret; 359 #endif 360 spi_flash_addr(erase_addr, cmd); 361 362 debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1], 363 cmd[2], cmd[3], erase_addr); 364 365 ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0); 366 if (ret < 0) { 367 debug("SF: erase failed\n"); 368 break; 369 } 370 371 offset += erase_size; 372 len -= erase_size; 373 } 374 375 return ret; 376 } 377 378 int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, 379 size_t len, const void *buf) 380 { 381 struct spi_slave *spi = flash->spi; 382 unsigned long byte_addr, page_size; 383 u32 write_addr; 384 size_t chunk_len, actual; 385 u8 cmd[SPI_FLASH_CMD_LEN]; 386 int ret = -1; 387 388 page_size = flash->page_size; 389 390 if (flash->flash_is_locked) { 391 if (flash->flash_is_locked(flash, offset, len) > 0) { 392 printf("offset 0x%x is protected and cannot be written\n", 393 offset); 394 return -EINVAL; 395 } 396 } 397 398 cmd[0] = flash->write_cmd; 399 for (actual = 0; actual < len; actual += chunk_len) { 400 write_addr = offset; 401 402 #ifdef CONFIG_SF_DUAL_FLASH 403 if (flash->dual_flash > SF_SINGLE_FLASH) 404 spi_flash_dual(flash, &write_addr); 405 #endif 406 #ifdef CONFIG_SPI_FLASH_BAR 407 ret = spi_flash_write_bar(flash, write_addr); 408 if (ret < 0) 409 return ret; 410 #endif 411 byte_addr = offset % page_size; 412 chunk_len = min(len - actual, (size_t)(page_size - byte_addr)); 413 414 if (spi->max_write_size) 415 chunk_len = min(chunk_len, 416 (size_t)spi->max_write_size); 417 418 spi_flash_addr(write_addr, cmd); 419 420 debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", 421 buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); 422 423 ret = spi_flash_write_common(flash, cmd, sizeof(cmd), 424 buf + actual, chunk_len); 425 if (ret < 0) { 426 debug("SF: write failed\n"); 427 break; 428 } 429 430 offset += chunk_len; 431 } 432 433 return ret; 434 } 435 436 int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, 437 size_t cmd_len, void *data, size_t data_len) 438 { 439 struct spi_slave *spi = flash->spi; 440 int ret; 441 442 ret = spi_claim_bus(spi); 443 if (ret) { 444 debug("SF: unable to claim SPI bus\n"); 445 return ret; 446 } 447 448 ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len); 449 if (ret < 0) { 450 debug("SF: read cmd failed\n"); 451 return ret; 452 } 453 454 spi_release_bus(spi); 455 456 return ret; 457 } 458 459 /* 460 * TODO: remove the weak after all the other spi_flash_copy_mmap 461 * implementations removed from drivers 462 */ 463 void __weak spi_flash_copy_mmap(void *data, void *offset, size_t len) 464 { 465 #ifdef CONFIG_DMA 466 if (!dma_memcpy(data, offset, len)) 467 return; 468 #endif 469 memcpy(data, offset, len); 470 } 471 472 int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, 473 size_t len, void *data) 474 { 475 struct spi_slave *spi = flash->spi; 476 u8 *cmd, cmdsz; 477 u32 remain_len, read_len, read_addr; 478 int bank_sel = 0; 479 int ret = -1; 480 481 /* Handle memory-mapped SPI */ 482 if (flash->memory_map) { 483 ret = spi_claim_bus(spi); 484 if (ret) { 485 debug("SF: unable to claim SPI bus\n"); 486 return ret; 487 } 488 spi_xfer(spi, 0, NULL, NULL, SPI_XFER_MMAP); 489 spi_flash_copy_mmap(data, flash->memory_map + offset, len); 490 spi_xfer(spi, 0, NULL, NULL, SPI_XFER_MMAP_END); 491 spi_release_bus(spi); 492 return 0; 493 } 494 495 cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte; 496 cmd = calloc(1, cmdsz); 497 if (!cmd) { 498 debug("SF: Failed to allocate cmd\n"); 499 return -ENOMEM; 500 } 501 502 cmd[0] = flash->read_cmd; 503 while (len) { 504 read_addr = offset; 505 506 #ifdef CONFIG_SF_DUAL_FLASH 507 if (flash->dual_flash > SF_SINGLE_FLASH) 508 spi_flash_dual(flash, &read_addr); 509 #endif 510 #ifdef CONFIG_SPI_FLASH_BAR 511 ret = spi_flash_write_bar(flash, read_addr); 512 if (ret < 0) 513 return ret; 514 bank_sel = flash->bank_curr; 515 #endif 516 remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) * 517 (bank_sel + 1)) - offset; 518 if (len < remain_len) 519 read_len = len; 520 else 521 read_len = remain_len; 522 523 spi_flash_addr(read_addr, cmd); 524 525 ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len); 526 if (ret < 0) { 527 debug("SF: read failed\n"); 528 break; 529 } 530 531 offset += read_len; 532 len -= read_len; 533 data += read_len; 534 } 535 536 free(cmd); 537 return ret; 538 } 539 540 #ifdef CONFIG_SPI_FLASH_SST 541 static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf) 542 { 543 struct spi_slave *spi = flash->spi; 544 int ret; 545 u8 cmd[4] = { 546 CMD_SST_BP, 547 offset >> 16, 548 offset >> 8, 549 offset, 550 }; 551 552 debug("BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", 553 spi_w8r8(spi, CMD_READ_STATUS), buf, cmd[0], offset); 554 555 ret = spi_flash_cmd_write_enable(flash); 556 if (ret) 557 return ret; 558 559 ret = spi_flash_cmd_write(spi, cmd, sizeof(cmd), buf, 1); 560 if (ret) 561 return ret; 562 563 return spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); 564 } 565 566 int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, 567 const void *buf) 568 { 569 struct spi_slave *spi = flash->spi; 570 size_t actual, cmd_len; 571 int ret; 572 u8 cmd[4]; 573 574 ret = spi_claim_bus(spi); 575 if (ret) { 576 debug("SF: Unable to claim SPI bus\n"); 577 return ret; 578 } 579 580 /* If the data is not word aligned, write out leading single byte */ 581 actual = offset % 2; 582 if (actual) { 583 ret = sst_byte_write(flash, offset, buf); 584 if (ret) 585 goto done; 586 } 587 offset += actual; 588 589 ret = spi_flash_cmd_write_enable(flash); 590 if (ret) 591 goto done; 592 593 cmd_len = 4; 594 cmd[0] = CMD_SST_AAI_WP; 595 cmd[1] = offset >> 16; 596 cmd[2] = offset >> 8; 597 cmd[3] = offset; 598 599 for (; actual < len - 1; actual += 2) { 600 debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", 601 spi_w8r8(spi, CMD_READ_STATUS), buf + actual, 602 cmd[0], offset); 603 604 ret = spi_flash_cmd_write(spi, cmd, cmd_len, 605 buf + actual, 2); 606 if (ret) { 607 debug("SF: sst word program failed\n"); 608 break; 609 } 610 611 ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); 612 if (ret) 613 break; 614 615 cmd_len = 1; 616 offset += 2; 617 } 618 619 if (!ret) 620 ret = spi_flash_cmd_write_disable(flash); 621 622 /* If there is a single trailing byte, write it out */ 623 if (!ret && actual != len) 624 ret = sst_byte_write(flash, offset, buf + actual); 625 626 done: 627 debug("SF: sst: program %s %zu bytes @ 0x%zx\n", 628 ret ? "failure" : "success", len, offset - actual); 629 630 spi_release_bus(spi); 631 return ret; 632 } 633 634 int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len, 635 const void *buf) 636 { 637 struct spi_slave *spi = flash->spi; 638 size_t actual; 639 int ret; 640 641 ret = spi_claim_bus(spi); 642 if (ret) { 643 debug("SF: Unable to claim SPI bus\n"); 644 return ret; 645 } 646 647 for (actual = 0; actual < len; actual++) { 648 ret = sst_byte_write(flash, offset, buf + actual); 649 if (ret) { 650 debug("SF: sst byte program failed\n"); 651 break; 652 } 653 offset++; 654 } 655 656 if (!ret) 657 ret = spi_flash_cmd_write_disable(flash); 658 659 debug("SF: sst: program %s %zu bytes @ 0x%zx\n", 660 ret ? "failure" : "success", len, offset - actual); 661 662 spi_release_bus(spi); 663 return ret; 664 } 665 #endif 666 667 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) 668 static void stm_get_locked_range(struct spi_flash *flash, u8 sr, loff_t *ofs, 669 u64 *len) 670 { 671 u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 672 int shift = ffs(mask) - 1; 673 int pow; 674 675 if (!(sr & mask)) { 676 /* No protection */ 677 *ofs = 0; 678 *len = 0; 679 } else { 680 pow = ((sr & mask) ^ mask) >> shift; 681 *len = flash->size >> pow; 682 *ofs = flash->size - *len; 683 } 684 } 685 686 /* 687 * Return 1 if the entire region is locked, 0 otherwise 688 */ 689 static int stm_is_locked_sr(struct spi_flash *flash, loff_t ofs, u64 len, 690 u8 sr) 691 { 692 loff_t lock_offs; 693 u64 lock_len; 694 695 stm_get_locked_range(flash, sr, &lock_offs, &lock_len); 696 697 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs); 698 } 699 700 /* 701 * Check if a region of the flash is (completely) locked. See stm_lock() for 702 * more info. 703 * 704 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and 705 * negative on errors. 706 */ 707 int stm_is_locked(struct spi_flash *flash, u32 ofs, size_t len) 708 { 709 int status; 710 u8 sr; 711 712 status = read_sr(flash, &sr); 713 if (status < 0) 714 return status; 715 716 return stm_is_locked_sr(flash, ofs, len, sr); 717 } 718 719 /* 720 * Lock a region of the flash. Compatible with ST Micro and similar flash. 721 * Supports only the block protection bits BP{0,1,2} in the status register 722 * (SR). Does not support these features found in newer SR bitfields: 723 * - TB: top/bottom protect - only handle TB=0 (top protect) 724 * - SEC: sector/block protect - only handle SEC=0 (block protect) 725 * - CMP: complement protect - only support CMP=0 (range is not complemented) 726 * 727 * Sample table portion for 8MB flash (Winbond w25q64fw): 728 * 729 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion 730 * -------------------------------------------------------------------------- 731 * X | X | 0 | 0 | 0 | NONE | NONE 732 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64 733 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32 734 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16 735 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8 736 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4 737 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2 738 * X | X | 1 | 1 | 1 | 8 MB | ALL 739 * 740 * Returns negative on errors, 0 on success. 741 */ 742 int stm_lock(struct spi_flash *flash, u32 ofs, size_t len) 743 { 744 u8 status_old, status_new; 745 u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 746 u8 shift = ffs(mask) - 1, pow, val; 747 int ret; 748 749 ret = read_sr(flash, &status_old); 750 if (ret < 0) 751 return ret; 752 753 /* SPI NOR always locks to the end */ 754 if (ofs + len != flash->size) { 755 /* Does combined region extend to end? */ 756 if (!stm_is_locked_sr(flash, ofs + len, flash->size - ofs - len, 757 status_old)) 758 return -EINVAL; 759 len = flash->size - ofs; 760 } 761 762 /* 763 * Need smallest pow such that: 764 * 765 * 1 / (2^pow) <= (len / size) 766 * 767 * so (assuming power-of-2 size) we do: 768 * 769 * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len)) 770 */ 771 pow = ilog2(flash->size) - ilog2(len); 772 val = mask - (pow << shift); 773 if (val & ~mask) 774 return -EINVAL; 775 776 /* Don't "lock" with no region! */ 777 if (!(val & mask)) 778 return -EINVAL; 779 780 status_new = (status_old & ~mask) | val; 781 782 /* Only modify protection if it will not unlock other areas */ 783 if ((status_new & mask) <= (status_old & mask)) 784 return -EINVAL; 785 786 write_sr(flash, status_new); 787 788 return 0; 789 } 790 791 /* 792 * Unlock a region of the flash. See stm_lock() for more info 793 * 794 * Returns negative on errors, 0 on success. 795 */ 796 int stm_unlock(struct spi_flash *flash, u32 ofs, size_t len) 797 { 798 uint8_t status_old, status_new; 799 u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 800 u8 shift = ffs(mask) - 1, pow, val; 801 int ret; 802 803 ret = read_sr(flash, &status_old); 804 if (ret < 0) 805 return ret; 806 807 /* Cannot unlock; would unlock larger region than requested */ 808 if (stm_is_locked_sr(flash, ofs - flash->erase_size, flash->erase_size, 809 status_old)) 810 return -EINVAL; 811 /* 812 * Need largest pow such that: 813 * 814 * 1 / (2^pow) >= (len / size) 815 * 816 * so (assuming power-of-2 size) we do: 817 * 818 * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len)) 819 */ 820 pow = ilog2(flash->size) - order_base_2(flash->size - (ofs + len)); 821 if (ofs + len == flash->size) { 822 val = 0; /* fully unlocked */ 823 } else { 824 val = mask - (pow << shift); 825 /* Some power-of-two sizes are not supported */ 826 if (val & ~mask) 827 return -EINVAL; 828 } 829 830 status_new = (status_old & ~mask) | val; 831 832 /* Only modify protection if it will not lock other areas */ 833 if ((status_new & mask) >= (status_old & mask)) 834 return -EINVAL; 835 836 write_sr(flash, status_new); 837 838 return 0; 839 } 840 #endif 841 842 843 #ifdef CONFIG_SPI_FLASH_MACRONIX 844 static int macronix_quad_enable(struct spi_flash *flash) 845 { 846 u8 qeb_status; 847 int ret; 848 849 ret = read_sr(flash, &qeb_status); 850 if (ret < 0) 851 return ret; 852 853 if (qeb_status & STATUS_QEB_MXIC) 854 return 0; 855 856 ret = write_sr(flash, qeb_status | STATUS_QEB_MXIC); 857 if (ret < 0) 858 return ret; 859 860 /* read SR and check it */ 861 ret = read_sr(flash, &qeb_status); 862 if (!(ret >= 0 && (qeb_status & STATUS_QEB_MXIC))) { 863 printf("SF: Macronix SR Quad bit not clear\n"); 864 return -EINVAL; 865 } 866 867 return ret; 868 } 869 #endif 870 871 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 872 static int spansion_quad_enable(struct spi_flash *flash) 873 { 874 u8 qeb_status; 875 int ret; 876 877 ret = read_cr(flash, &qeb_status); 878 if (ret < 0) 879 return ret; 880 881 if (qeb_status & STATUS_QEB_WINSPAN) 882 return 0; 883 884 ret = write_cr(flash, qeb_status | STATUS_QEB_WINSPAN); 885 if (ret < 0) 886 return ret; 887 888 /* read CR and check it */ 889 ret = read_cr(flash, &qeb_status); 890 if (!(ret >= 0 && (qeb_status & STATUS_QEB_WINSPAN))) { 891 printf("SF: Spansion CR Quad bit not clear\n"); 892 return -EINVAL; 893 } 894 895 return ret; 896 } 897 #endif 898 899 #ifdef CONFIG_SPI_FLASH_STMICRO 900 static int micron_quad_enable(struct spi_flash *flash) 901 { 902 u8 qeb_status; 903 int ret; 904 905 ret = read_evcr(flash, &qeb_status); 906 if (ret < 0) 907 return ret; 908 909 if (!(qeb_status & STATUS_QEB_MICRON)) 910 return 0; 911 912 ret = write_evcr(flash, qeb_status & ~STATUS_QEB_MICRON); 913 if (ret < 0) 914 return ret; 915 916 /* read EVCR and check it */ 917 ret = read_evcr(flash, &qeb_status); 918 if (!(ret >= 0 && !(qeb_status & STATUS_QEB_MICRON))) { 919 printf("SF: Micron EVCR Quad bit not clear\n"); 920 return -EINVAL; 921 } 922 923 return ret; 924 } 925 #endif 926 927 static int set_quad_mode(struct spi_flash *flash, u8 idcode0) 928 { 929 switch (idcode0) { 930 #ifdef CONFIG_SPI_FLASH_MACRONIX 931 case SPI_FLASH_CFI_MFR_MACRONIX: 932 return macronix_quad_enable(flash); 933 #endif 934 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 935 case SPI_FLASH_CFI_MFR_SPANSION: 936 case SPI_FLASH_CFI_MFR_WINBOND: 937 return spansion_quad_enable(flash); 938 #endif 939 #ifdef CONFIG_SPI_FLASH_STMICRO 940 case SPI_FLASH_CFI_MFR_STMICRO: 941 return micron_quad_enable(flash); 942 #endif 943 default: 944 printf("SF: Need set QEB func for %02x flash\n", idcode0); 945 return -1; 946 } 947 } 948 949 #if CONFIG_IS_ENABLED(OF_CONTROL) 950 int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash) 951 { 952 #ifdef CONFIG_DM_SPI_FLASH 953 fdt_addr_t addr; 954 fdt_size_t size; 955 int node = flash->dev->of_offset; 956 957 addr = fdtdec_get_addr_size(blob, node, "memory-map", &size); 958 if (addr == FDT_ADDR_T_NONE) { 959 debug("%s: Cannot decode address\n", __func__); 960 return 0; 961 } 962 963 if (flash->size != size) { 964 debug("%s: Memory map must cover entire device\n", __func__); 965 return -1; 966 } 967 flash->memory_map = map_sysmem(addr, size); 968 #endif 969 970 return 0; 971 } 972 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */ 973 974 #ifdef CONFIG_SPI_FLASH_SPANSION 975 static int spansion_s25fss_disable_4KB_erase(struct spi_slave *spi) 976 { 977 u8 cmd[4]; 978 u32 offset = 0x800004; /* CR3V register offset */ 979 u8 cr3v; 980 int ret; 981 982 cmd[0] = CMD_SPANSION_RDAR; 983 cmd[1] = offset >> 16; 984 cmd[2] = offset >> 8; 985 cmd[3] = offset >> 0; 986 987 ret = spi_flash_cmd_read(spi, cmd, 4, &cr3v, 1); 988 if (ret) 989 return -EIO; 990 /* CR3V bit3: 4-KB Erase */ 991 if (cr3v & 0x8) 992 return 0; 993 994 cmd[0] = CMD_SPANSION_WRAR; 995 cr3v |= 0x8; 996 ret = spi_flash_cmd_write(spi, cmd, 4, &cr3v, 1); 997 if (ret) 998 return -EIO; 999 1000 cmd[0] = CMD_SPANSION_RDAR; 1001 ret = spi_flash_cmd_read(spi, cmd, 4, &cr3v, 1); 1002 if (ret) 1003 return -EIO; 1004 if (!(cr3v & 0x8)) 1005 return -EFAULT; 1006 1007 return 0; 1008 } 1009 #endif 1010 1011 int spi_flash_scan(struct spi_flash *flash) 1012 { 1013 struct spi_slave *spi = flash->spi; 1014 const struct spi_flash_params *params; 1015 u16 jedec, ext_jedec; 1016 u8 cmd, idcode[5]; 1017 int ret; 1018 static u8 spi_read_cmds_array[] = { 1019 CMD_READ_ARRAY_SLOW, 1020 CMD_READ_ARRAY_FAST, 1021 CMD_READ_DUAL_OUTPUT_FAST, 1022 CMD_READ_QUAD_OUTPUT_FAST, 1023 CMD_READ_DUAL_IO_FAST, 1024 CMD_READ_QUAD_IO_FAST }; 1025 1026 /* Read the ID codes */ 1027 ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode)); 1028 if (ret) { 1029 printf("SF: Failed to get idcodes\n"); 1030 return ret; 1031 } 1032 1033 #ifdef DEBUG 1034 printf("SF: Got idcodes\n"); 1035 print_buffer(0, idcode, 1, sizeof(idcode), 0); 1036 #endif 1037 1038 jedec = idcode[1] << 8 | idcode[2]; 1039 ext_jedec = idcode[3] << 8 | idcode[4]; 1040 1041 /* Validate params from spi_flash_params table */ 1042 params = spi_flash_params_table; 1043 for (; params->name != NULL; params++) { 1044 if ((params->jedec >> 16) == idcode[0]) { 1045 if ((params->jedec & 0xFFFF) == jedec) { 1046 if (params->ext_jedec == 0) 1047 break; 1048 else if (params->ext_jedec == ext_jedec) 1049 break; 1050 } 1051 } 1052 } 1053 1054 if (!params->name) { 1055 printf("SF: Unsupported flash IDs: "); 1056 printf("manuf %02x, jedec %04x, ext_jedec %04x\n", 1057 idcode[0], jedec, ext_jedec); 1058 return -EPROTONOSUPPORT; 1059 } 1060 1061 #ifdef CONFIG_SPI_FLASH_SPANSION 1062 /* 1063 * The S25FS-S family physical sectors may be configured as a 1064 * hybrid combination of eight 4-kB parameter sectors 1065 * at the top or bottom of the address space with all 1066 * but one of the remaining sectors being uniform size. 1067 * The Parameter Sector Erase commands (20h or 21h) must 1068 * be used to erase the 4-kB parameter sectors individually. 1069 * The Sector (uniform sector) Erase commands (D8h or DCh) 1070 * must be used to erase any of the remaining 1071 * sectors, including the portion of highest or lowest address 1072 * sector that is not overlaid by the parameter sectors. 1073 * The uniform sector erase command has no effect on parameter sectors. 1074 */ 1075 if ((jedec == 0x0219 || (jedec == 0x0220)) && 1076 (ext_jedec & 0xff00) == 0x4d00) { 1077 int ret; 1078 u8 id[6]; 1079 1080 /* Read the ID codes again, 6 bytes */ 1081 ret = spi_flash_cmd(flash->spi, CMD_READ_ID, id, sizeof(id)); 1082 if (ret) 1083 return -EIO; 1084 1085 ret = memcmp(id, idcode, 5); 1086 if (ret) 1087 return -EIO; 1088 1089 /* 0x81: S25FS-S family 0x80: S25FL-S family */ 1090 if (id[5] == 0x81) { 1091 ret = spansion_s25fss_disable_4KB_erase(spi); 1092 if (ret) 1093 return ret; 1094 } 1095 } 1096 #endif 1097 /* Flash powers up read-only, so clear BP# bits */ 1098 if (idcode[0] == SPI_FLASH_CFI_MFR_ATMEL || 1099 idcode[0] == SPI_FLASH_CFI_MFR_MACRONIX || 1100 idcode[0] == SPI_FLASH_CFI_MFR_SST) 1101 write_sr(flash, 0); 1102 1103 /* Assign spi data */ 1104 flash->name = params->name; 1105 flash->memory_map = spi->memory_map; 1106 flash->dual_flash = spi->option; 1107 1108 /* Assign spi flash flags */ 1109 if (params->flags & SST_WR) 1110 flash->flags |= SNOR_F_SST_WR; 1111 1112 /* Assign spi_flash ops */ 1113 #ifndef CONFIG_DM_SPI_FLASH 1114 flash->write = spi_flash_cmd_write_ops; 1115 #if defined(CONFIG_SPI_FLASH_SST) 1116 if (flash->flags & SNOR_F_SST_WR) { 1117 if (spi->mode & SPI_TX_BYTE) 1118 flash->write = sst_write_bp; 1119 else 1120 flash->write = sst_write_wp; 1121 } 1122 #endif 1123 flash->erase = spi_flash_cmd_erase_ops; 1124 flash->read = spi_flash_cmd_read_ops; 1125 #endif 1126 1127 /* lock hooks are flash specific - assign them based on idcode0 */ 1128 switch (idcode[0]) { 1129 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) 1130 case SPI_FLASH_CFI_MFR_STMICRO: 1131 case SPI_FLASH_CFI_MFR_SST: 1132 flash->flash_lock = stm_lock; 1133 flash->flash_unlock = stm_unlock; 1134 flash->flash_is_locked = stm_is_locked; 1135 #endif 1136 break; 1137 default: 1138 debug("SF: Lock ops not supported for %02x flash\n", idcode[0]); 1139 } 1140 1141 /* Compute the flash size */ 1142 flash->shift = (flash->dual_flash & SF_DUAL_PARALLEL_FLASH) ? 1 : 0; 1143 /* 1144 * The Spansion S25FL032P and S25FL064P have 256b pages, yet use the 1145 * 0x4d00 Extended JEDEC code. The rest of the Spansion flashes with 1146 * the 0x4d00 Extended JEDEC code have 512b pages. All of the others 1147 * have 256b pages. 1148 */ 1149 if (ext_jedec == 0x4d00) { 1150 if ((jedec == 0x0215) || (jedec == 0x216) || (jedec == 0x220)) 1151 flash->page_size = 256; 1152 else 1153 flash->page_size = 512; 1154 } else { 1155 flash->page_size = 256; 1156 } 1157 flash->page_size <<= flash->shift; 1158 flash->sector_size = params->sector_size << flash->shift; 1159 flash->size = flash->sector_size * params->nr_sectors << flash->shift; 1160 #ifdef CONFIG_SF_DUAL_FLASH 1161 if (flash->dual_flash & SF_DUAL_STACKED_FLASH) 1162 flash->size <<= 1; 1163 #endif 1164 1165 /* Compute erase sector and command */ 1166 if (params->flags & SECT_4K) { 1167 flash->erase_cmd = CMD_ERASE_4K; 1168 flash->erase_size = 4096 << flash->shift; 1169 } else if (params->flags & SECT_32K) { 1170 flash->erase_cmd = CMD_ERASE_32K; 1171 flash->erase_size = 32768 << flash->shift; 1172 } else { 1173 flash->erase_cmd = CMD_ERASE_64K; 1174 flash->erase_size = flash->sector_size; 1175 } 1176 1177 /* Now erase size becomes valid sector size */ 1178 flash->sector_size = flash->erase_size; 1179 1180 /* Look for the fastest read cmd */ 1181 cmd = fls(params->e_rd_cmd & spi->mode_rx); 1182 if (cmd) { 1183 cmd = spi_read_cmds_array[cmd - 1]; 1184 flash->read_cmd = cmd; 1185 } else { 1186 /* Go for default supported read cmd */ 1187 flash->read_cmd = CMD_READ_ARRAY_FAST; 1188 } 1189 1190 /* Not require to look for fastest only two write cmds yet */ 1191 if (params->flags & WR_QPP && spi->mode & SPI_TX_QUAD) 1192 flash->write_cmd = CMD_QUAD_PAGE_PROGRAM; 1193 else 1194 /* Go for default supported write cmd */ 1195 flash->write_cmd = CMD_PAGE_PROGRAM; 1196 1197 /* Set the quad enable bit - only for quad commands */ 1198 if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) || 1199 (flash->read_cmd == CMD_READ_QUAD_IO_FAST) || 1200 (flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) { 1201 ret = set_quad_mode(flash, idcode[0]); 1202 if (ret) { 1203 debug("SF: Fail to set QEB for %02x\n", idcode[0]); 1204 return -EINVAL; 1205 } 1206 } 1207 1208 /* Read dummy_byte: dummy byte is determined based on the 1209 * dummy cycles of a particular command. 1210 * Fast commands - dummy_byte = dummy_cycles/8 1211 * I/O commands- dummy_byte = (dummy_cycles * no.of lines)/8 1212 * For I/O commands except cmd[0] everything goes on no.of lines 1213 * based on particular command but incase of fast commands except 1214 * data all go on single line irrespective of command. 1215 */ 1216 switch (flash->read_cmd) { 1217 case CMD_READ_QUAD_IO_FAST: 1218 flash->dummy_byte = 2; 1219 break; 1220 case CMD_READ_ARRAY_SLOW: 1221 flash->dummy_byte = 0; 1222 break; 1223 default: 1224 flash->dummy_byte = 1; 1225 } 1226 1227 #ifdef CONFIG_SPI_FLASH_STMICRO 1228 if (params->flags & E_FSR) 1229 flash->flags |= SNOR_F_USE_FSR; 1230 #endif 1231 1232 /* Configure the BAR - discover bank cmds and read current bank */ 1233 #ifdef CONFIG_SPI_FLASH_BAR 1234 ret = spi_flash_read_bar(flash, idcode[0]); 1235 if (ret < 0) 1236 return ret; 1237 #endif 1238 1239 #if CONFIG_IS_ENABLED(OF_CONTROL) 1240 ret = spi_flash_decode_fdt(gd->fdt_blob, flash); 1241 if (ret) { 1242 debug("SF: FDT decode error\n"); 1243 return -EINVAL; 1244 } 1245 #endif 1246 1247 #ifndef CONFIG_SPL_BUILD 1248 printf("SF: Detected %s with page size ", flash->name); 1249 print_size(flash->page_size, ", erase size "); 1250 print_size(flash->erase_size, ", total "); 1251 print_size(flash->size, ""); 1252 if (flash->memory_map) 1253 printf(", mapped at %p", flash->memory_map); 1254 puts("\n"); 1255 #endif 1256 1257 #ifndef CONFIG_SPI_FLASH_BAR 1258 if (((flash->dual_flash == SF_SINGLE_FLASH) && 1259 (flash->size > SPI_FLASH_16MB_BOUN)) || 1260 ((flash->dual_flash > SF_SINGLE_FLASH) && 1261 (flash->size > SPI_FLASH_16MB_BOUN << 1))) { 1262 puts("SF: Warning - Only lower 16MiB accessible,"); 1263 puts(" Full access #define CONFIG_SPI_FLASH_BAR\n"); 1264 } 1265 #endif 1266 1267 return ret; 1268 } 1269