1 /* 2 * SPI Flash Core 3 * 4 * Copyright (C) 2015 Jagan Teki <jteki@openedev.com> 5 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. 6 * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik 7 * Copyright (C) 2008 Atmel Corporation 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <errno.h> 14 #include <malloc.h> 15 #include <mapmem.h> 16 #include <spi.h> 17 #include <spi_flash.h> 18 #include <linux/log2.h> 19 20 #include "sf_internal.h" 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 static void spi_flash_addr(u32 addr, u8 *cmd) 25 { 26 /* cmd[0] is actual command */ 27 cmd[1] = addr >> 16; 28 cmd[2] = addr >> 8; 29 cmd[3] = addr >> 0; 30 } 31 32 static int read_sr(struct spi_flash *flash, u8 *rs) 33 { 34 int ret; 35 u8 cmd; 36 37 cmd = CMD_READ_STATUS; 38 ret = spi_flash_read_common(flash, &cmd, 1, rs, 1); 39 if (ret < 0) { 40 debug("SF: fail to read status register\n"); 41 return ret; 42 } 43 44 return 0; 45 } 46 47 static int read_fsr(struct spi_flash *flash, u8 *fsr) 48 { 49 int ret; 50 const u8 cmd = CMD_FLAG_STATUS; 51 52 ret = spi_flash_read_common(flash, &cmd, 1, fsr, 1); 53 if (ret < 0) { 54 debug("SF: fail to read flag status register\n"); 55 return ret; 56 } 57 58 return 0; 59 } 60 61 static int write_sr(struct spi_flash *flash, u8 ws) 62 { 63 u8 cmd; 64 int ret; 65 66 cmd = CMD_WRITE_STATUS; 67 ret = spi_flash_write_common(flash, &cmd, 1, &ws, 1); 68 if (ret < 0) { 69 debug("SF: fail to write status register\n"); 70 return ret; 71 } 72 73 return 0; 74 } 75 76 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 77 static int read_cr(struct spi_flash *flash, u8 *rc) 78 { 79 int ret; 80 u8 cmd; 81 82 cmd = CMD_READ_CONFIG; 83 ret = spi_flash_read_common(flash, &cmd, 1, rc, 1); 84 if (ret < 0) { 85 debug("SF: fail to read config register\n"); 86 return ret; 87 } 88 89 return 0; 90 } 91 92 static int write_cr(struct spi_flash *flash, u8 wc) 93 { 94 u8 data[2]; 95 u8 cmd; 96 int ret; 97 98 ret = read_sr(flash, &data[0]); 99 if (ret < 0) 100 return ret; 101 102 cmd = CMD_WRITE_STATUS; 103 data[1] = wc; 104 ret = spi_flash_write_common(flash, &cmd, 1, &data, 2); 105 if (ret) { 106 debug("SF: fail to write config register\n"); 107 return ret; 108 } 109 110 return 0; 111 } 112 #endif 113 114 #ifdef CONFIG_SPI_FLASH_BAR 115 static int spi_flash_write_bar(struct spi_flash *flash, u32 offset) 116 { 117 u8 cmd, bank_sel; 118 int ret; 119 120 bank_sel = offset / (SPI_FLASH_16MB_BOUN << flash->shift); 121 if (bank_sel == flash->bank_curr) 122 goto bar_end; 123 124 cmd = flash->bank_write_cmd; 125 ret = spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1); 126 if (ret < 0) { 127 debug("SF: fail to write bank register\n"); 128 return ret; 129 } 130 131 bar_end: 132 flash->bank_curr = bank_sel; 133 return flash->bank_curr; 134 } 135 136 static int spi_flash_read_bar(struct spi_flash *flash, u8 idcode0) 137 { 138 u8 curr_bank = 0; 139 int ret; 140 141 if (flash->size <= SPI_FLASH_16MB_BOUN) 142 goto bank_end; 143 144 switch (idcode0) { 145 case SPI_FLASH_CFI_MFR_SPANSION: 146 flash->bank_read_cmd = CMD_BANKADDR_BRRD; 147 flash->bank_write_cmd = CMD_BANKADDR_BRWR; 148 break; 149 default: 150 flash->bank_read_cmd = CMD_EXTNADDR_RDEAR; 151 flash->bank_write_cmd = CMD_EXTNADDR_WREAR; 152 } 153 154 ret = spi_flash_read_common(flash, &flash->bank_read_cmd, 1, 155 &curr_bank, 1); 156 if (ret) { 157 debug("SF: fail to read bank addr register\n"); 158 return ret; 159 } 160 161 bank_end: 162 flash->bank_curr = curr_bank; 163 return 0; 164 } 165 #endif 166 167 #ifdef CONFIG_SF_DUAL_FLASH 168 static void spi_flash_dual(struct spi_flash *flash, u32 *addr) 169 { 170 struct spi_slave *spi = flash->spi; 171 172 switch (flash->dual_flash) { 173 case SF_DUAL_STACKED_FLASH: 174 if (*addr >= (flash->size >> 1)) { 175 *addr -= flash->size >> 1; 176 spi->flags |= SPI_XFER_U_PAGE; 177 } else { 178 spi->flags &= ~SPI_XFER_U_PAGE; 179 } 180 break; 181 case SF_DUAL_PARALLEL_FLASH: 182 *addr >>= flash->shift; 183 break; 184 default: 185 debug("SF: Unsupported dual_flash=%d\n", flash->dual_flash); 186 break; 187 } 188 } 189 #endif 190 191 static int spi_flash_sr_ready(struct spi_flash *flash) 192 { 193 u8 sr; 194 int ret; 195 196 ret = read_sr(flash, &sr); 197 if (ret < 0) 198 return ret; 199 200 return !(sr & STATUS_WIP); 201 } 202 203 static int spi_flash_fsr_ready(struct spi_flash *flash) 204 { 205 u8 fsr; 206 int ret; 207 208 ret = read_fsr(flash, &fsr); 209 if (ret < 0) 210 return ret; 211 212 return fsr & STATUS_PEC; 213 } 214 215 static int spi_flash_ready(struct spi_flash *flash) 216 { 217 int sr, fsr; 218 219 sr = spi_flash_sr_ready(flash); 220 if (sr < 0) 221 return sr; 222 223 fsr = 1; 224 if (flash->flags & SNOR_F_USE_FSR) { 225 fsr = spi_flash_fsr_ready(flash); 226 if (fsr < 0) 227 return fsr; 228 } 229 230 return sr && fsr; 231 } 232 233 static int spi_flash_cmd_wait_ready(struct spi_flash *flash, 234 unsigned long timeout) 235 { 236 int timebase, ret; 237 238 timebase = get_timer(0); 239 240 while (get_timer(timebase) < timeout) { 241 ret = spi_flash_ready(flash); 242 if (ret < 0) 243 return ret; 244 if (ret) 245 return 0; 246 } 247 248 printf("SF: Timeout!\n"); 249 250 return -ETIMEDOUT; 251 } 252 253 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, 254 size_t cmd_len, const void *buf, size_t buf_len) 255 { 256 struct spi_slave *spi = flash->spi; 257 unsigned long timeout = SPI_FLASH_PROG_TIMEOUT; 258 int ret; 259 260 if (buf == NULL) 261 timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT; 262 263 ret = spi_claim_bus(spi); 264 if (ret) { 265 debug("SF: unable to claim SPI bus\n"); 266 return ret; 267 } 268 269 ret = spi_flash_cmd_write_enable(flash); 270 if (ret < 0) { 271 debug("SF: enabling write failed\n"); 272 return ret; 273 } 274 275 ret = spi_flash_cmd_write(spi, cmd, cmd_len, buf, buf_len); 276 if (ret < 0) { 277 debug("SF: write cmd failed\n"); 278 return ret; 279 } 280 281 ret = spi_flash_cmd_wait_ready(flash, timeout); 282 if (ret < 0) { 283 debug("SF: write %s timed out\n", 284 timeout == SPI_FLASH_PROG_TIMEOUT ? 285 "program" : "page erase"); 286 return ret; 287 } 288 289 spi_release_bus(spi); 290 291 return ret; 292 } 293 294 int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) 295 { 296 u32 erase_size, erase_addr; 297 u8 cmd[SPI_FLASH_CMD_LEN]; 298 int ret = -1; 299 300 erase_size = flash->erase_size; 301 if (offset % erase_size || len % erase_size) { 302 debug("SF: Erase offset/length not multiple of erase size\n"); 303 return -1; 304 } 305 306 if (flash->flash_is_locked) { 307 if (flash->flash_is_locked(flash, offset, len) > 0) { 308 printf("offset 0x%x is protected and cannot be erased\n", 309 offset); 310 return -EINVAL; 311 } 312 } 313 314 cmd[0] = flash->erase_cmd; 315 while (len) { 316 erase_addr = offset; 317 318 #ifdef CONFIG_SF_DUAL_FLASH 319 if (flash->dual_flash > SF_SINGLE_FLASH) 320 spi_flash_dual(flash, &erase_addr); 321 #endif 322 #ifdef CONFIG_SPI_FLASH_BAR 323 ret = spi_flash_write_bar(flash, erase_addr); 324 if (ret < 0) 325 return ret; 326 #endif 327 spi_flash_addr(erase_addr, cmd); 328 329 debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1], 330 cmd[2], cmd[3], erase_addr); 331 332 ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0); 333 if (ret < 0) { 334 debug("SF: erase failed\n"); 335 break; 336 } 337 338 offset += erase_size; 339 len -= erase_size; 340 } 341 342 return ret; 343 } 344 345 int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, 346 size_t len, const void *buf) 347 { 348 struct spi_slave *spi = flash->spi; 349 unsigned long byte_addr, page_size; 350 u32 write_addr; 351 size_t chunk_len, actual; 352 u8 cmd[SPI_FLASH_CMD_LEN]; 353 int ret = -1; 354 355 page_size = flash->page_size; 356 357 if (flash->flash_is_locked) { 358 if (flash->flash_is_locked(flash, offset, len) > 0) { 359 printf("offset 0x%x is protected and cannot be written\n", 360 offset); 361 return -EINVAL; 362 } 363 } 364 365 cmd[0] = flash->write_cmd; 366 for (actual = 0; actual < len; actual += chunk_len) { 367 write_addr = offset; 368 369 #ifdef CONFIG_SF_DUAL_FLASH 370 if (flash->dual_flash > SF_SINGLE_FLASH) 371 spi_flash_dual(flash, &write_addr); 372 #endif 373 #ifdef CONFIG_SPI_FLASH_BAR 374 ret = spi_flash_write_bar(flash, write_addr); 375 if (ret < 0) 376 return ret; 377 #endif 378 byte_addr = offset % page_size; 379 chunk_len = min(len - actual, (size_t)(page_size - byte_addr)); 380 381 if (spi->max_write_size) 382 chunk_len = min(chunk_len, 383 (size_t)spi->max_write_size); 384 385 spi_flash_addr(write_addr, cmd); 386 387 debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", 388 buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); 389 390 ret = spi_flash_write_common(flash, cmd, sizeof(cmd), 391 buf + actual, chunk_len); 392 if (ret < 0) { 393 debug("SF: write failed\n"); 394 break; 395 } 396 397 offset += chunk_len; 398 } 399 400 return ret; 401 } 402 403 int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, 404 size_t cmd_len, void *data, size_t data_len) 405 { 406 struct spi_slave *spi = flash->spi; 407 int ret; 408 409 ret = spi_claim_bus(spi); 410 if (ret) { 411 debug("SF: unable to claim SPI bus\n"); 412 return ret; 413 } 414 415 ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len); 416 if (ret < 0) { 417 debug("SF: read cmd failed\n"); 418 return ret; 419 } 420 421 spi_release_bus(spi); 422 423 return ret; 424 } 425 426 void __weak spi_flash_copy_mmap(void *data, void *offset, size_t len) 427 { 428 memcpy(data, offset, len); 429 } 430 431 int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, 432 size_t len, void *data) 433 { 434 struct spi_slave *spi = flash->spi; 435 u8 *cmd, cmdsz; 436 u32 remain_len, read_len, read_addr; 437 int bank_sel = 0; 438 int ret = -1; 439 440 /* Handle memory-mapped SPI */ 441 if (flash->memory_map) { 442 ret = spi_claim_bus(spi); 443 if (ret) { 444 debug("SF: unable to claim SPI bus\n"); 445 return ret; 446 } 447 spi_xfer(spi, 0, NULL, NULL, SPI_XFER_MMAP); 448 spi_flash_copy_mmap(data, flash->memory_map + offset, len); 449 spi_xfer(spi, 0, NULL, NULL, SPI_XFER_MMAP_END); 450 spi_release_bus(spi); 451 return 0; 452 } 453 454 cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte; 455 cmd = calloc(1, cmdsz); 456 if (!cmd) { 457 debug("SF: Failed to allocate cmd\n"); 458 return -ENOMEM; 459 } 460 461 cmd[0] = flash->read_cmd; 462 while (len) { 463 read_addr = offset; 464 465 #ifdef CONFIG_SF_DUAL_FLASH 466 if (flash->dual_flash > SF_SINGLE_FLASH) 467 spi_flash_dual(flash, &read_addr); 468 #endif 469 #ifdef CONFIG_SPI_FLASH_BAR 470 ret = spi_flash_write_bar(flash, read_addr); 471 if (ret < 0) 472 return ret; 473 bank_sel = flash->bank_curr; 474 #endif 475 remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) * 476 (bank_sel + 1)) - offset; 477 if (len < remain_len) 478 read_len = len; 479 else 480 read_len = remain_len; 481 482 spi_flash_addr(read_addr, cmd); 483 484 ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len); 485 if (ret < 0) { 486 debug("SF: read failed\n"); 487 break; 488 } 489 490 offset += read_len; 491 len -= read_len; 492 data += read_len; 493 } 494 495 free(cmd); 496 return ret; 497 } 498 499 #ifdef CONFIG_SPI_FLASH_SST 500 static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf) 501 { 502 struct spi_slave *spi = flash->spi; 503 int ret; 504 u8 cmd[4] = { 505 CMD_SST_BP, 506 offset >> 16, 507 offset >> 8, 508 offset, 509 }; 510 511 debug("BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", 512 spi_w8r8(spi, CMD_READ_STATUS), buf, cmd[0], offset); 513 514 ret = spi_flash_cmd_write_enable(flash); 515 if (ret) 516 return ret; 517 518 ret = spi_flash_cmd_write(spi, cmd, sizeof(cmd), buf, 1); 519 if (ret) 520 return ret; 521 522 return spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); 523 } 524 525 int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, 526 const void *buf) 527 { 528 struct spi_slave *spi = flash->spi; 529 size_t actual, cmd_len; 530 int ret; 531 u8 cmd[4]; 532 533 ret = spi_claim_bus(spi); 534 if (ret) { 535 debug("SF: Unable to claim SPI bus\n"); 536 return ret; 537 } 538 539 /* If the data is not word aligned, write out leading single byte */ 540 actual = offset % 2; 541 if (actual) { 542 ret = sst_byte_write(flash, offset, buf); 543 if (ret) 544 goto done; 545 } 546 offset += actual; 547 548 ret = spi_flash_cmd_write_enable(flash); 549 if (ret) 550 goto done; 551 552 cmd_len = 4; 553 cmd[0] = CMD_SST_AAI_WP; 554 cmd[1] = offset >> 16; 555 cmd[2] = offset >> 8; 556 cmd[3] = offset; 557 558 for (; actual < len - 1; actual += 2) { 559 debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", 560 spi_w8r8(spi, CMD_READ_STATUS), buf + actual, 561 cmd[0], offset); 562 563 ret = spi_flash_cmd_write(spi, cmd, cmd_len, 564 buf + actual, 2); 565 if (ret) { 566 debug("SF: sst word program failed\n"); 567 break; 568 } 569 570 ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); 571 if (ret) 572 break; 573 574 cmd_len = 1; 575 offset += 2; 576 } 577 578 if (!ret) 579 ret = spi_flash_cmd_write_disable(flash); 580 581 /* If there is a single trailing byte, write it out */ 582 if (!ret && actual != len) 583 ret = sst_byte_write(flash, offset, buf + actual); 584 585 done: 586 debug("SF: sst: program %s %zu bytes @ 0x%zx\n", 587 ret ? "failure" : "success", len, offset - actual); 588 589 spi_release_bus(spi); 590 return ret; 591 } 592 593 int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len, 594 const void *buf) 595 { 596 struct spi_slave *spi = flash->spi; 597 size_t actual; 598 int ret; 599 600 ret = spi_claim_bus(spi); 601 if (ret) { 602 debug("SF: Unable to claim SPI bus\n"); 603 return ret; 604 } 605 606 for (actual = 0; actual < len; actual++) { 607 ret = sst_byte_write(flash, offset, buf + actual); 608 if (ret) { 609 debug("SF: sst byte program failed\n"); 610 break; 611 } 612 offset++; 613 } 614 615 if (!ret) 616 ret = spi_flash_cmd_write_disable(flash); 617 618 debug("SF: sst: program %s %zu bytes @ 0x%zx\n", 619 ret ? "failure" : "success", len, offset - actual); 620 621 spi_release_bus(spi); 622 return ret; 623 } 624 #endif 625 626 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) 627 static void stm_get_locked_range(struct spi_flash *flash, u8 sr, loff_t *ofs, 628 u32 *len) 629 { 630 u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 631 int shift = ffs(mask) - 1; 632 int pow; 633 634 if (!(sr & mask)) { 635 /* No protection */ 636 *ofs = 0; 637 *len = 0; 638 } else { 639 pow = ((sr & mask) ^ mask) >> shift; 640 *len = flash->size >> pow; 641 *ofs = flash->size - *len; 642 } 643 } 644 645 /* 646 * Return 1 if the entire region is locked, 0 otherwise 647 */ 648 static int stm_is_locked_sr(struct spi_flash *flash, u32 ofs, u32 len, 649 u8 sr) 650 { 651 loff_t lock_offs; 652 u32 lock_len; 653 654 stm_get_locked_range(flash, sr, &lock_offs, &lock_len); 655 656 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs); 657 } 658 659 /* 660 * Check if a region of the flash is (completely) locked. See stm_lock() for 661 * more info. 662 * 663 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and 664 * negative on errors. 665 */ 666 int stm_is_locked(struct spi_flash *flash, u32 ofs, size_t len) 667 { 668 int status; 669 u8 sr; 670 671 status = read_sr(flash, &sr); 672 if (status < 0) 673 return status; 674 675 return stm_is_locked_sr(flash, ofs, len, sr); 676 } 677 678 /* 679 * Lock a region of the flash. Compatible with ST Micro and similar flash. 680 * Supports only the block protection bits BP{0,1,2} in the status register 681 * (SR). Does not support these features found in newer SR bitfields: 682 * - TB: top/bottom protect - only handle TB=0 (top protect) 683 * - SEC: sector/block protect - only handle SEC=0 (block protect) 684 * - CMP: complement protect - only support CMP=0 (range is not complemented) 685 * 686 * Sample table portion for 8MB flash (Winbond w25q64fw): 687 * 688 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion 689 * -------------------------------------------------------------------------- 690 * X | X | 0 | 0 | 0 | NONE | NONE 691 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64 692 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32 693 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16 694 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8 695 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4 696 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2 697 * X | X | 1 | 1 | 1 | 8 MB | ALL 698 * 699 * Returns negative on errors, 0 on success. 700 */ 701 int stm_lock(struct spi_flash *flash, u32 ofs, size_t len) 702 { 703 u8 status_old, status_new; 704 u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 705 u8 shift = ffs(mask) - 1, pow, val; 706 int ret; 707 708 ret = read_sr(flash, &status_old); 709 if (ret < 0) 710 return ret; 711 712 /* SPI NOR always locks to the end */ 713 if (ofs + len != flash->size) { 714 /* Does combined region extend to end? */ 715 if (!stm_is_locked_sr(flash, ofs + len, flash->size - ofs - len, 716 status_old)) 717 return -EINVAL; 718 len = flash->size - ofs; 719 } 720 721 /* 722 * Need smallest pow such that: 723 * 724 * 1 / (2^pow) <= (len / size) 725 * 726 * so (assuming power-of-2 size) we do: 727 * 728 * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len)) 729 */ 730 pow = ilog2(flash->size) - ilog2(len); 731 val = mask - (pow << shift); 732 if (val & ~mask) 733 return -EINVAL; 734 735 /* Don't "lock" with no region! */ 736 if (!(val & mask)) 737 return -EINVAL; 738 739 status_new = (status_old & ~mask) | val; 740 741 /* Only modify protection if it will not unlock other areas */ 742 if ((status_new & mask) <= (status_old & mask)) 743 return -EINVAL; 744 745 write_sr(flash, status_new); 746 747 return 0; 748 } 749 750 /* 751 * Unlock a region of the flash. See stm_lock() for more info 752 * 753 * Returns negative on errors, 0 on success. 754 */ 755 int stm_unlock(struct spi_flash *flash, u32 ofs, size_t len) 756 { 757 uint8_t status_old, status_new; 758 u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 759 u8 shift = ffs(mask) - 1, pow, val; 760 int ret; 761 762 ret = read_sr(flash, &status_old); 763 if (ret < 0) 764 return ret; 765 766 /* Cannot unlock; would unlock larger region than requested */ 767 if (stm_is_locked_sr(flash, ofs - flash->erase_size, flash->erase_size, 768 status_old)) 769 return -EINVAL; 770 /* 771 * Need largest pow such that: 772 * 773 * 1 / (2^pow) >= (len / size) 774 * 775 * so (assuming power-of-2 size) we do: 776 * 777 * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len)) 778 */ 779 pow = ilog2(flash->size) - order_base_2(flash->size - (ofs + len)); 780 if (ofs + len == flash->size) { 781 val = 0; /* fully unlocked */ 782 } else { 783 val = mask - (pow << shift); 784 /* Some power-of-two sizes are not supported */ 785 if (val & ~mask) 786 return -EINVAL; 787 } 788 789 status_new = (status_old & ~mask) | val; 790 791 /* Only modify protection if it will not lock other areas */ 792 if ((status_new & mask) >= (status_old & mask)) 793 return -EINVAL; 794 795 write_sr(flash, status_new); 796 797 return 0; 798 } 799 #endif 800 801 802 #ifdef CONFIG_SPI_FLASH_MACRONIX 803 static int spi_flash_set_qeb_mxic(struct spi_flash *flash) 804 { 805 u8 qeb_status; 806 int ret; 807 808 ret = read_sr(flash, &qeb_status); 809 if (ret < 0) 810 return ret; 811 812 if (qeb_status & STATUS_QEB_MXIC) { 813 debug("SF: mxic: QEB is already set\n"); 814 } else { 815 ret = write_sr(flash, STATUS_QEB_MXIC); 816 if (ret < 0) 817 return ret; 818 } 819 820 return ret; 821 } 822 #endif 823 824 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 825 static int spi_flash_set_qeb_winspan(struct spi_flash *flash) 826 { 827 u8 qeb_status; 828 int ret; 829 830 ret = read_cr(flash, &qeb_status); 831 if (ret < 0) 832 return ret; 833 834 if (qeb_status & STATUS_QEB_WINSPAN) { 835 debug("SF: winspan: QEB is already set\n"); 836 } else { 837 ret = write_cr(flash, STATUS_QEB_WINSPAN); 838 if (ret < 0) 839 return ret; 840 } 841 842 return ret; 843 } 844 #endif 845 846 static int spi_flash_set_qeb(struct spi_flash *flash, u8 idcode0) 847 { 848 switch (idcode0) { 849 #ifdef CONFIG_SPI_FLASH_MACRONIX 850 case SPI_FLASH_CFI_MFR_MACRONIX: 851 return spi_flash_set_qeb_mxic(flash); 852 #endif 853 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 854 case SPI_FLASH_CFI_MFR_SPANSION: 855 case SPI_FLASH_CFI_MFR_WINBOND: 856 return spi_flash_set_qeb_winspan(flash); 857 #endif 858 #ifdef CONFIG_SPI_FLASH_STMICRO 859 case SPI_FLASH_CFI_MFR_STMICRO: 860 debug("SF: QEB is volatile for %02x flash\n", idcode0); 861 return 0; 862 #endif 863 default: 864 printf("SF: Need set QEB func for %02x flash\n", idcode0); 865 return -1; 866 } 867 } 868 869 #if CONFIG_IS_ENABLED(OF_CONTROL) 870 int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash) 871 { 872 fdt_addr_t addr; 873 fdt_size_t size; 874 int node; 875 876 /* If there is no node, do nothing */ 877 node = fdtdec_next_compatible(blob, 0, COMPAT_GENERIC_SPI_FLASH); 878 if (node < 0) 879 return 0; 880 881 addr = fdtdec_get_addr_size(blob, node, "memory-map", &size); 882 if (addr == FDT_ADDR_T_NONE) { 883 debug("%s: Cannot decode address\n", __func__); 884 return 0; 885 } 886 887 if (flash->size != size) { 888 debug("%s: Memory map must cover entire device\n", __func__); 889 return -1; 890 } 891 flash->memory_map = map_sysmem(addr, size); 892 893 return 0; 894 } 895 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */ 896 897 int spi_flash_scan(struct spi_flash *flash) 898 { 899 struct spi_slave *spi = flash->spi; 900 const struct spi_flash_params *params; 901 u16 jedec, ext_jedec; 902 u8 cmd, idcode[5]; 903 int ret; 904 static u8 spi_read_cmds_array[] = { 905 CMD_READ_ARRAY_SLOW, 906 CMD_READ_ARRAY_FAST, 907 CMD_READ_DUAL_OUTPUT_FAST, 908 CMD_READ_DUAL_IO_FAST, 909 CMD_READ_QUAD_OUTPUT_FAST, 910 CMD_READ_QUAD_IO_FAST }; 911 912 /* Read the ID codes */ 913 ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode)); 914 if (ret) { 915 printf("SF: Failed to get idcodes\n"); 916 return -EINVAL; 917 } 918 919 #ifdef DEBUG 920 printf("SF: Got idcodes\n"); 921 print_buffer(0, idcode, 1, sizeof(idcode), 0); 922 #endif 923 924 jedec = idcode[1] << 8 | idcode[2]; 925 ext_jedec = idcode[3] << 8 | idcode[4]; 926 927 /* Validate params from spi_flash_params table */ 928 params = spi_flash_params_table; 929 for (; params->name != NULL; params++) { 930 if ((params->jedec >> 16) == idcode[0]) { 931 if ((params->jedec & 0xFFFF) == jedec) { 932 if (params->ext_jedec == 0) 933 break; 934 else if (params->ext_jedec == ext_jedec) 935 break; 936 } 937 } 938 } 939 940 if (!params->name) { 941 printf("SF: Unsupported flash IDs: "); 942 printf("manuf %02x, jedec %04x, ext_jedec %04x\n", 943 idcode[0], jedec, ext_jedec); 944 return -EPROTONOSUPPORT; 945 } 946 947 /* Flash powers up read-only, so clear BP# bits */ 948 if (idcode[0] == SPI_FLASH_CFI_MFR_ATMEL || 949 idcode[0] == SPI_FLASH_CFI_MFR_MACRONIX || 950 idcode[0] == SPI_FLASH_CFI_MFR_SST) 951 write_sr(flash, 0); 952 953 /* Assign spi data */ 954 flash->name = params->name; 955 flash->memory_map = spi->memory_map; 956 flash->dual_flash = spi->option; 957 958 /* Assign spi flash flags */ 959 if (params->flags & SST_WR) 960 flash->flags |= SNOR_F_SST_WR; 961 962 /* Assign spi_flash ops */ 963 #ifndef CONFIG_DM_SPI_FLASH 964 flash->write = spi_flash_cmd_write_ops; 965 #if defined(CONFIG_SPI_FLASH_SST) 966 if (flash->flags & SNOR_F_SST_WR) { 967 if (spi->mode & SPI_TX_BYTE) 968 flash->write = sst_write_bp; 969 else 970 flash->write = sst_write_wp; 971 } 972 #endif 973 flash->erase = spi_flash_cmd_erase_ops; 974 flash->read = spi_flash_cmd_read_ops; 975 #endif 976 977 /* lock hooks are flash specific - assign them based on idcode0 */ 978 switch (idcode[0]) { 979 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) 980 case SPI_FLASH_CFI_MFR_STMICRO: 981 case SPI_FLASH_CFI_MFR_SST: 982 flash->flash_lock = stm_lock; 983 flash->flash_unlock = stm_unlock; 984 flash->flash_is_locked = stm_is_locked; 985 #endif 986 break; 987 default: 988 debug("SF: Lock ops not supported for %02x flash\n", idcode[0]); 989 } 990 991 /* Compute the flash size */ 992 flash->shift = (flash->dual_flash & SF_DUAL_PARALLEL_FLASH) ? 1 : 0; 993 /* 994 * The Spansion S25FL032P and S25FL064P have 256b pages, yet use the 995 * 0x4d00 Extended JEDEC code. The rest of the Spansion flashes with 996 * the 0x4d00 Extended JEDEC code have 512b pages. All of the others 997 * have 256b pages. 998 */ 999 if (ext_jedec == 0x4d00) { 1000 if ((jedec == 0x0215) || (jedec == 0x216)) 1001 flash->page_size = 256; 1002 else 1003 flash->page_size = 512; 1004 } else { 1005 flash->page_size = 256; 1006 } 1007 flash->page_size <<= flash->shift; 1008 flash->sector_size = params->sector_size << flash->shift; 1009 flash->size = flash->sector_size * params->nr_sectors << flash->shift; 1010 #ifdef CONFIG_SF_DUAL_FLASH 1011 if (flash->dual_flash & SF_DUAL_STACKED_FLASH) 1012 flash->size <<= 1; 1013 #endif 1014 1015 /* Compute erase sector and command */ 1016 if (params->flags & SECT_4K) { 1017 flash->erase_cmd = CMD_ERASE_4K; 1018 flash->erase_size = 4096 << flash->shift; 1019 } else if (params->flags & SECT_32K) { 1020 flash->erase_cmd = CMD_ERASE_32K; 1021 flash->erase_size = 32768 << flash->shift; 1022 } else { 1023 flash->erase_cmd = CMD_ERASE_64K; 1024 flash->erase_size = flash->sector_size; 1025 } 1026 1027 /* Now erase size becomes valid sector size */ 1028 flash->sector_size = flash->erase_size; 1029 1030 /* Look for the fastest read cmd */ 1031 cmd = fls(params->e_rd_cmd & spi->op_mode_rx); 1032 if (cmd) { 1033 cmd = spi_read_cmds_array[cmd - 1]; 1034 flash->read_cmd = cmd; 1035 } else { 1036 /* Go for default supported read cmd */ 1037 flash->read_cmd = CMD_READ_ARRAY_FAST; 1038 } 1039 1040 /* Not require to look for fastest only two write cmds yet */ 1041 if (params->flags & WR_QPP && spi->mode & SPI_TX_QUAD) 1042 flash->write_cmd = CMD_QUAD_PAGE_PROGRAM; 1043 else 1044 /* Go for default supported write cmd */ 1045 flash->write_cmd = CMD_PAGE_PROGRAM; 1046 1047 /* Set the quad enable bit - only for quad commands */ 1048 if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) || 1049 (flash->read_cmd == CMD_READ_QUAD_IO_FAST) || 1050 (flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) { 1051 ret = spi_flash_set_qeb(flash, idcode[0]); 1052 if (ret) { 1053 debug("SF: Fail to set QEB for %02x\n", idcode[0]); 1054 return -EINVAL; 1055 } 1056 } 1057 1058 /* Read dummy_byte: dummy byte is determined based on the 1059 * dummy cycles of a particular command. 1060 * Fast commands - dummy_byte = dummy_cycles/8 1061 * I/O commands- dummy_byte = (dummy_cycles * no.of lines)/8 1062 * For I/O commands except cmd[0] everything goes on no.of lines 1063 * based on particular command but incase of fast commands except 1064 * data all go on single line irrespective of command. 1065 */ 1066 switch (flash->read_cmd) { 1067 case CMD_READ_QUAD_IO_FAST: 1068 flash->dummy_byte = 2; 1069 break; 1070 case CMD_READ_ARRAY_SLOW: 1071 flash->dummy_byte = 0; 1072 break; 1073 default: 1074 flash->dummy_byte = 1; 1075 } 1076 1077 #ifdef CONFIG_SPI_FLASH_STMICRO 1078 if (params->flags & E_FSR) 1079 flash->flags |= SNOR_F_USE_FSR; 1080 #endif 1081 1082 /* Configure the BAR - discover bank cmds and read current bank */ 1083 #ifdef CONFIG_SPI_FLASH_BAR 1084 ret = spi_flash_read_bar(flash, idcode[0]); 1085 if (ret < 0) 1086 return ret; 1087 #endif 1088 1089 #if CONFIG_IS_ENABLED(OF_CONTROL) 1090 ret = spi_flash_decode_fdt(gd->fdt_blob, flash); 1091 if (ret) { 1092 debug("SF: FDT decode error\n"); 1093 return -EINVAL; 1094 } 1095 #endif 1096 1097 #ifndef CONFIG_SPL_BUILD 1098 printf("SF: Detected %s with page size ", flash->name); 1099 print_size(flash->page_size, ", erase size "); 1100 print_size(flash->erase_size, ", total "); 1101 print_size(flash->size, ""); 1102 if (flash->memory_map) 1103 printf(", mapped at %p", flash->memory_map); 1104 puts("\n"); 1105 #endif 1106 1107 #ifndef CONFIG_SPI_FLASH_BAR 1108 if (((flash->dual_flash == SF_SINGLE_FLASH) && 1109 (flash->size > SPI_FLASH_16MB_BOUN)) || 1110 ((flash->dual_flash > SF_SINGLE_FLASH) && 1111 (flash->size > SPI_FLASH_16MB_BOUN << 1))) { 1112 puts("SF: Warning - Only lower 16MiB accessible,"); 1113 puts(" Full access #define CONFIG_SPI_FLASH_BAR\n"); 1114 } 1115 #endif 1116 1117 return ret; 1118 } 1119