1 /* 2 * SPI Flash Core 3 * 4 * Copyright (C) 2015 Jagan Teki <jteki@openedev.com> 5 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. 6 * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik 7 * Copyright (C) 2008 Atmel Corporation 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <errno.h> 14 #include <malloc.h> 15 #include <mapmem.h> 16 #include <spi.h> 17 #include <spi_flash.h> 18 #include <linux/log2.h> 19 #include <linux/sizes.h> 20 #include <dma.h> 21 22 #include "sf_internal.h" 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 static void spi_flash_addr(u32 addr, u8 *cmd) 27 { 28 /* cmd[0] is actual command */ 29 cmd[1] = addr >> 16; 30 cmd[2] = addr >> 8; 31 cmd[3] = addr >> 0; 32 } 33 34 static int read_sr(struct spi_flash *flash, u8 *rs) 35 { 36 int ret; 37 u8 cmd; 38 39 cmd = CMD_READ_STATUS; 40 ret = spi_flash_read_common(flash, &cmd, 1, rs, 1); 41 if (ret < 0) { 42 debug("SF: fail to read status register\n"); 43 return ret; 44 } 45 46 return 0; 47 } 48 49 static int read_fsr(struct spi_flash *flash, u8 *fsr) 50 { 51 int ret; 52 const u8 cmd = CMD_FLAG_STATUS; 53 54 ret = spi_flash_read_common(flash, &cmd, 1, fsr, 1); 55 if (ret < 0) { 56 debug("SF: fail to read flag status register\n"); 57 return ret; 58 } 59 60 return 0; 61 } 62 63 static int write_sr(struct spi_flash *flash, u8 ws) 64 { 65 u8 cmd; 66 int ret; 67 68 cmd = CMD_WRITE_STATUS; 69 ret = spi_flash_write_common(flash, &cmd, 1, &ws, 1); 70 if (ret < 0) { 71 debug("SF: fail to write status register\n"); 72 return ret; 73 } 74 75 return 0; 76 } 77 78 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 79 static int read_cr(struct spi_flash *flash, u8 *rc) 80 { 81 int ret; 82 u8 cmd; 83 84 cmd = CMD_READ_CONFIG; 85 ret = spi_flash_read_common(flash, &cmd, 1, rc, 1); 86 if (ret < 0) { 87 debug("SF: fail to read config register\n"); 88 return ret; 89 } 90 91 return 0; 92 } 93 94 static int write_cr(struct spi_flash *flash, u8 wc) 95 { 96 u8 data[2]; 97 u8 cmd; 98 int ret; 99 100 ret = read_sr(flash, &data[0]); 101 if (ret < 0) 102 return ret; 103 104 cmd = CMD_WRITE_STATUS; 105 data[1] = wc; 106 ret = spi_flash_write_common(flash, &cmd, 1, &data, 2); 107 if (ret) { 108 debug("SF: fail to write config register\n"); 109 return ret; 110 } 111 112 return 0; 113 } 114 #endif 115 116 int spi_flash_cmd_get_sw_write_prot(struct spi_flash *flash) 117 { 118 u8 status; 119 int ret; 120 121 ret = read_sr(flash, &status); 122 if (ret) 123 return ret; 124 125 return (status >> 2) & 7; 126 } 127 128 #ifdef CONFIG_SPI_FLASH_BAR 129 /* 130 * This "clean_bar" is necessary in a situation when one was accessing 131 * spi flash memory > 16 MiB by using Bank Address Register's BA24 bit. 132 * 133 * After it the BA24 bit shall be cleared to allow access to correct 134 * memory region after SW reset (by calling "reset" command). 135 * 136 * Otherwise, the BA24 bit may be left set and then after reset, the 137 * ROM would read/write/erase SPL from 16 MiB * bank_sel address. 138 */ 139 static int clean_bar(struct spi_flash *flash) 140 { 141 u8 cmd, bank_sel = 0; 142 143 if (flash->bank_curr == 0) 144 return 0; 145 cmd = flash->bank_write_cmd; 146 flash->bank_curr = 0; 147 148 return spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1); 149 } 150 151 static int write_bar(struct spi_flash *flash, u32 offset) 152 { 153 u8 cmd, bank_sel; 154 int ret; 155 156 bank_sel = offset / (SPI_FLASH_16MB_BOUN << flash->shift); 157 if (bank_sel == flash->bank_curr) 158 goto bar_end; 159 160 cmd = flash->bank_write_cmd; 161 ret = spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1); 162 if (ret < 0) { 163 debug("SF: fail to write bank register\n"); 164 return ret; 165 } 166 167 bar_end: 168 flash->bank_curr = bank_sel; 169 return flash->bank_curr; 170 } 171 172 static int read_bar(struct spi_flash *flash, const struct spi_flash_info *info) 173 { 174 u8 curr_bank = 0; 175 int ret; 176 177 if (flash->size <= SPI_FLASH_16MB_BOUN) 178 goto bar_end; 179 180 switch (JEDEC_MFR(info)) { 181 case SPI_FLASH_CFI_MFR_SPANSION: 182 flash->bank_read_cmd = CMD_BANKADDR_BRRD; 183 flash->bank_write_cmd = CMD_BANKADDR_BRWR; 184 break; 185 default: 186 flash->bank_read_cmd = CMD_EXTNADDR_RDEAR; 187 flash->bank_write_cmd = CMD_EXTNADDR_WREAR; 188 } 189 190 ret = spi_flash_read_common(flash, &flash->bank_read_cmd, 1, 191 &curr_bank, 1); 192 if (ret) { 193 debug("SF: fail to read bank addr register\n"); 194 return ret; 195 } 196 197 bar_end: 198 flash->bank_curr = curr_bank; 199 return 0; 200 } 201 #endif 202 203 #ifdef CONFIG_SF_DUAL_FLASH 204 static void spi_flash_dual(struct spi_flash *flash, u32 *addr) 205 { 206 switch (flash->dual_flash) { 207 case SF_DUAL_STACKED_FLASH: 208 if (*addr >= (flash->size >> 1)) { 209 *addr -= flash->size >> 1; 210 flash->flags |= SNOR_F_USE_UPAGE; 211 } else { 212 flash->flags &= ~SNOR_F_USE_UPAGE; 213 } 214 break; 215 case SF_DUAL_PARALLEL_FLASH: 216 *addr >>= flash->shift; 217 break; 218 default: 219 debug("SF: Unsupported dual_flash=%d\n", flash->dual_flash); 220 break; 221 } 222 } 223 #endif 224 225 static int spi_flash_sr_ready(struct spi_flash *flash) 226 { 227 u8 sr; 228 int ret; 229 230 ret = read_sr(flash, &sr); 231 if (ret < 0) 232 return ret; 233 234 return !(sr & STATUS_WIP); 235 } 236 237 static int spi_flash_fsr_ready(struct spi_flash *flash) 238 { 239 u8 fsr; 240 int ret; 241 242 ret = read_fsr(flash, &fsr); 243 if (ret < 0) 244 return ret; 245 246 return fsr & STATUS_PEC; 247 } 248 249 static int spi_flash_ready(struct spi_flash *flash) 250 { 251 int sr, fsr; 252 253 sr = spi_flash_sr_ready(flash); 254 if (sr < 0) 255 return sr; 256 257 fsr = 1; 258 if (flash->flags & SNOR_F_USE_FSR) { 259 fsr = spi_flash_fsr_ready(flash); 260 if (fsr < 0) 261 return fsr; 262 } 263 264 return sr && fsr; 265 } 266 267 static int spi_flash_wait_till_ready(struct spi_flash *flash, 268 unsigned long timeout) 269 { 270 unsigned long timebase; 271 int ret; 272 273 timebase = get_timer(0); 274 275 while (get_timer(timebase) < timeout) { 276 ret = spi_flash_ready(flash); 277 if (ret < 0) 278 return ret; 279 if (ret) 280 return 0; 281 } 282 283 printf("SF: Timeout!\n"); 284 285 return -ETIMEDOUT; 286 } 287 288 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, 289 size_t cmd_len, const void *buf, size_t buf_len) 290 { 291 struct spi_slave *spi = flash->spi; 292 unsigned long timeout = SPI_FLASH_PROG_TIMEOUT; 293 int ret; 294 295 if (buf == NULL) 296 timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT; 297 298 ret = spi_claim_bus(spi); 299 if (ret) { 300 debug("SF: unable to claim SPI bus\n"); 301 return ret; 302 } 303 304 ret = spi_flash_cmd_write_enable(flash); 305 if (ret < 0) { 306 debug("SF: enabling write failed\n"); 307 return ret; 308 } 309 310 ret = spi_flash_cmd_write(spi, cmd, cmd_len, buf, buf_len); 311 if (ret < 0) { 312 debug("SF: write cmd failed\n"); 313 return ret; 314 } 315 316 ret = spi_flash_wait_till_ready(flash, timeout); 317 if (ret < 0) { 318 debug("SF: write %s timed out\n", 319 timeout == SPI_FLASH_PROG_TIMEOUT ? 320 "program" : "page erase"); 321 return ret; 322 } 323 324 spi_release_bus(spi); 325 326 return ret; 327 } 328 329 int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) 330 { 331 u32 erase_size, erase_addr; 332 u8 cmd[SPI_FLASH_CMD_LEN]; 333 int ret = -1; 334 335 erase_size = flash->erase_size; 336 if (offset % erase_size || len % erase_size) { 337 printf("SF: Erase offset/length not multiple of erase size\n"); 338 return -1; 339 } 340 341 if (flash->flash_is_locked) { 342 if (flash->flash_is_locked(flash, offset, len) > 0) { 343 printf("offset 0x%x is protected and cannot be erased\n", 344 offset); 345 return -EINVAL; 346 } 347 } 348 349 cmd[0] = flash->erase_cmd; 350 while (len) { 351 erase_addr = offset; 352 353 #ifdef CONFIG_SF_DUAL_FLASH 354 if (flash->dual_flash > SF_SINGLE_FLASH) 355 spi_flash_dual(flash, &erase_addr); 356 #endif 357 #ifdef CONFIG_SPI_FLASH_BAR 358 ret = write_bar(flash, erase_addr); 359 if (ret < 0) 360 return ret; 361 #endif 362 spi_flash_addr(erase_addr, cmd); 363 364 debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1], 365 cmd[2], cmd[3], erase_addr); 366 367 ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0); 368 if (ret < 0) { 369 debug("SF: erase failed\n"); 370 break; 371 } 372 373 offset += erase_size; 374 len -= erase_size; 375 } 376 377 #ifdef CONFIG_SPI_FLASH_BAR 378 ret = clean_bar(flash); 379 #endif 380 381 return ret; 382 } 383 384 int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, 385 size_t len, const void *buf) 386 { 387 struct spi_slave *spi = flash->spi; 388 unsigned long byte_addr, page_size; 389 u32 write_addr; 390 size_t chunk_len, actual; 391 u8 cmd[SPI_FLASH_CMD_LEN]; 392 int ret = -1; 393 394 page_size = flash->page_size; 395 396 if (flash->flash_is_locked) { 397 if (flash->flash_is_locked(flash, offset, len) > 0) { 398 printf("offset 0x%x is protected and cannot be written\n", 399 offset); 400 return -EINVAL; 401 } 402 } 403 404 cmd[0] = flash->write_cmd; 405 for (actual = 0; actual < len; actual += chunk_len) { 406 write_addr = offset; 407 408 #ifdef CONFIG_SF_DUAL_FLASH 409 if (flash->dual_flash > SF_SINGLE_FLASH) 410 spi_flash_dual(flash, &write_addr); 411 #endif 412 #ifdef CONFIG_SPI_FLASH_BAR 413 ret = write_bar(flash, write_addr); 414 if (ret < 0) 415 return ret; 416 #endif 417 byte_addr = offset % page_size; 418 chunk_len = min(len - actual, (size_t)(page_size - byte_addr)); 419 420 if (spi->max_write_size) 421 chunk_len = min(chunk_len, 422 spi->max_write_size - sizeof(cmd)); 423 424 spi_flash_addr(write_addr, cmd); 425 426 debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", 427 buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); 428 429 ret = spi_flash_write_common(flash, cmd, sizeof(cmd), 430 buf + actual, chunk_len); 431 if (ret < 0) { 432 debug("SF: write failed\n"); 433 break; 434 } 435 436 offset += chunk_len; 437 } 438 439 #ifdef CONFIG_SPI_FLASH_BAR 440 ret = clean_bar(flash); 441 #endif 442 443 return ret; 444 } 445 446 int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, 447 size_t cmd_len, void *data, size_t data_len) 448 { 449 struct spi_slave *spi = flash->spi; 450 int ret; 451 452 ret = spi_claim_bus(spi); 453 if (ret) { 454 debug("SF: unable to claim SPI bus\n"); 455 return ret; 456 } 457 458 ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len); 459 if (ret < 0) { 460 debug("SF: read cmd failed\n"); 461 return ret; 462 } 463 464 spi_release_bus(spi); 465 466 return ret; 467 } 468 469 /* 470 * TODO: remove the weak after all the other spi_flash_copy_mmap 471 * implementations removed from drivers 472 */ 473 void __weak spi_flash_copy_mmap(void *data, void *offset, size_t len) 474 { 475 #ifdef CONFIG_DMA 476 if (!dma_memcpy(data, offset, len)) 477 return; 478 #endif 479 memcpy(data, offset, len); 480 } 481 482 int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, 483 size_t len, void *data) 484 { 485 struct spi_slave *spi = flash->spi; 486 u8 cmdsz; 487 u32 remain_len, read_len, read_addr; 488 int bank_sel = 0; 489 int ret = 0; 490 491 /* Handle memory-mapped SPI */ 492 if (flash->memory_map) { 493 ret = spi_claim_bus(spi); 494 if (ret) { 495 debug("SF: unable to claim SPI bus\n"); 496 return log_ret(ret); 497 } 498 spi_xfer(spi, 0, NULL, NULL, SPI_XFER_MMAP); 499 spi_flash_copy_mmap(data, flash->memory_map + offset, len); 500 spi_xfer(spi, 0, NULL, NULL, SPI_XFER_MMAP_END); 501 spi_release_bus(spi); 502 return 0; 503 } 504 505 cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte; 506 u8 cmd[cmdsz]; 507 508 cmd[0] = flash->read_cmd; 509 while (len) { 510 read_addr = offset; 511 512 #ifdef CONFIG_SF_DUAL_FLASH 513 if (flash->dual_flash > SF_SINGLE_FLASH) 514 spi_flash_dual(flash, &read_addr); 515 #endif 516 #ifdef CONFIG_SPI_FLASH_BAR 517 ret = write_bar(flash, read_addr); 518 if (ret < 0) 519 return log_ret(ret); 520 bank_sel = flash->bank_curr; 521 #endif 522 remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) * 523 (bank_sel + 1)) - offset; 524 if (len < remain_len) 525 read_len = len; 526 else 527 read_len = remain_len; 528 529 if (spi->max_read_size) 530 read_len = min(read_len, spi->max_read_size); 531 532 spi_flash_addr(read_addr, cmd); 533 534 ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len); 535 if (ret < 0) { 536 debug("SF: read failed\n"); 537 break; 538 } 539 540 offset += read_len; 541 len -= read_len; 542 data += read_len; 543 } 544 545 #ifdef CONFIG_SPI_FLASH_BAR 546 ret = clean_bar(flash); 547 #endif 548 549 return log_ret(ret); 550 } 551 552 #ifdef CONFIG_SPI_FLASH_SST 553 static bool sst26_process_bpr(u32 bpr_size, u8 *cmd, u32 bit, enum lock_ctl ctl) 554 { 555 switch (ctl) { 556 case SST26_CTL_LOCK: 557 cmd[bpr_size - (bit / 8) - 1] |= BIT(bit % 8); 558 break; 559 case SST26_CTL_UNLOCK: 560 cmd[bpr_size - (bit / 8) - 1] &= ~BIT(bit % 8); 561 break; 562 case SST26_CTL_CHECK: 563 return !!(cmd[bpr_size - (bit / 8) - 1] & BIT(bit % 8)); 564 } 565 566 return false; 567 } 568 569 /* 570 * sst26wf016/sst26wf032/sst26wf064 have next block protection: 571 * 4x - 8 KByte blocks - read & write protection bits - upper addresses 572 * 1x - 32 KByte blocks - write protection bits 573 * rest - 64 KByte blocks - write protection bits 574 * 1x - 32 KByte blocks - write protection bits 575 * 4x - 8 KByte blocks - read & write protection bits - lower addresses 576 * 577 * We'll support only per 64k lock/unlock so lower and upper 64 KByte region 578 * will be treated as single block. 579 */ 580 581 /* 582 * Lock, unlock or check lock status of the flash region of the flash (depending 583 * on the lock_ctl value) 584 */ 585 static int sst26_lock_ctl(struct spi_flash *flash, u32 ofs, size_t len, enum lock_ctl ctl) 586 { 587 u32 i, bpr_ptr, rptr_64k, lptr_64k, bpr_size; 588 bool lower_64k = false, upper_64k = false; 589 u8 cmd, bpr_buff[SST26_MAX_BPR_REG_LEN] = {}; 590 int ret; 591 592 /* Check length and offset for 64k alignment */ 593 if ((ofs & (SZ_64K - 1)) || (len & (SZ_64K - 1))) 594 return -EINVAL; 595 596 if (ofs + len > flash->size) 597 return -EINVAL; 598 599 /* SST26 family has only 16 Mbit, 32 Mbit and 64 Mbit IC */ 600 if (flash->size != SZ_2M && 601 flash->size != SZ_4M && 602 flash->size != SZ_8M) 603 return -EINVAL; 604 605 bpr_size = 2 + (flash->size / SZ_64K / 8); 606 607 cmd = SST26_CMD_READ_BPR; 608 ret = spi_flash_read_common(flash, &cmd, 1, bpr_buff, bpr_size); 609 if (ret < 0) { 610 printf("SF: fail to read block-protection register\n"); 611 return ret; 612 } 613 614 rptr_64k = min_t(u32, ofs + len , flash->size - SST26_BOUND_REG_SIZE); 615 lptr_64k = max_t(u32, ofs, SST26_BOUND_REG_SIZE); 616 617 upper_64k = ((ofs + len) > (flash->size - SST26_BOUND_REG_SIZE)); 618 lower_64k = (ofs < SST26_BOUND_REG_SIZE); 619 620 /* Lower bits in block-protection register are about 64k region */ 621 bpr_ptr = lptr_64k / SZ_64K - 1; 622 623 /* Process 64K blocks region */ 624 while (lptr_64k < rptr_64k) { 625 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl)) 626 return EACCES; 627 628 bpr_ptr++; 629 lptr_64k += SZ_64K; 630 } 631 632 /* 32K and 8K region bits in BPR are after 64k region bits */ 633 bpr_ptr = (flash->size - 2 * SST26_BOUND_REG_SIZE) / SZ_64K; 634 635 /* Process lower 32K block region */ 636 if (lower_64k) 637 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl)) 638 return EACCES; 639 640 bpr_ptr++; 641 642 /* Process upper 32K block region */ 643 if (upper_64k) 644 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl)) 645 return EACCES; 646 647 bpr_ptr++; 648 649 /* Process lower 8K block regions */ 650 for (i = 0; i < SST26_BPR_8K_NUM; i++) { 651 if (lower_64k) 652 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl)) 653 return EACCES; 654 655 /* In 8K area BPR has both read and write protection bits */ 656 bpr_ptr += 2; 657 } 658 659 /* Process upper 8K block regions */ 660 for (i = 0; i < SST26_BPR_8K_NUM; i++) { 661 if (upper_64k) 662 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl)) 663 return EACCES; 664 665 /* In 8K area BPR has both read and write protection bits */ 666 bpr_ptr += 2; 667 } 668 669 /* If we check region status we don't need to write BPR back */ 670 if (ctl == SST26_CTL_CHECK) 671 return 0; 672 673 cmd = SST26_CMD_WRITE_BPR; 674 ret = spi_flash_write_common(flash, &cmd, 1, bpr_buff, bpr_size); 675 if (ret < 0) { 676 printf("SF: fail to write block-protection register\n"); 677 return ret; 678 } 679 680 return 0; 681 } 682 683 static int sst26_unlock(struct spi_flash *flash, u32 ofs, size_t len) 684 { 685 return sst26_lock_ctl(flash, ofs, len, SST26_CTL_UNLOCK); 686 } 687 688 static int sst26_lock(struct spi_flash *flash, u32 ofs, size_t len) 689 { 690 return sst26_lock_ctl(flash, ofs, len, SST26_CTL_LOCK); 691 } 692 693 /* 694 * Returns EACCES (positive value) if region is locked, 0 if region is unlocked, 695 * and negative on errors. 696 */ 697 static int sst26_is_locked(struct spi_flash *flash, u32 ofs, size_t len) 698 { 699 /* 700 * is_locked function is used for check before reading or erasing flash 701 * region, so offset and length might be not 64k allighned, so adjust 702 * them to be 64k allighned as sst26_lock_ctl works only with 64k 703 * allighned regions. 704 */ 705 ofs -= ofs & (SZ_64K - 1); 706 len = len & (SZ_64K - 1) ? (len & ~(SZ_64K - 1)) + SZ_64K : len; 707 708 return sst26_lock_ctl(flash, ofs, len, SST26_CTL_CHECK); 709 } 710 711 static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf) 712 { 713 struct spi_slave *spi = flash->spi; 714 int ret; 715 u8 cmd[4] = { 716 CMD_SST_BP, 717 offset >> 16, 718 offset >> 8, 719 offset, 720 }; 721 722 debug("BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", 723 spi_w8r8(spi, CMD_READ_STATUS), buf, cmd[0], offset); 724 725 ret = spi_flash_cmd_write_enable(flash); 726 if (ret) 727 return ret; 728 729 ret = spi_flash_cmd_write(spi, cmd, sizeof(cmd), buf, 1); 730 if (ret) 731 return ret; 732 733 return spi_flash_wait_till_ready(flash, SPI_FLASH_PROG_TIMEOUT); 734 } 735 736 int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, 737 const void *buf) 738 { 739 struct spi_slave *spi = flash->spi; 740 size_t actual, cmd_len; 741 int ret; 742 u8 cmd[4]; 743 744 ret = spi_claim_bus(spi); 745 if (ret) { 746 debug("SF: Unable to claim SPI bus\n"); 747 return ret; 748 } 749 750 /* If the data is not word aligned, write out leading single byte */ 751 actual = offset % 2; 752 if (actual) { 753 ret = sst_byte_write(flash, offset, buf); 754 if (ret) 755 goto done; 756 } 757 offset += actual; 758 759 ret = spi_flash_cmd_write_enable(flash); 760 if (ret) 761 goto done; 762 763 cmd_len = 4; 764 cmd[0] = CMD_SST_AAI_WP; 765 cmd[1] = offset >> 16; 766 cmd[2] = offset >> 8; 767 cmd[3] = offset; 768 769 for (; actual < len - 1; actual += 2) { 770 debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", 771 spi_w8r8(spi, CMD_READ_STATUS), buf + actual, 772 cmd[0], offset); 773 774 ret = spi_flash_cmd_write(spi, cmd, cmd_len, 775 buf + actual, 2); 776 if (ret) { 777 debug("SF: sst word program failed\n"); 778 break; 779 } 780 781 ret = spi_flash_wait_till_ready(flash, SPI_FLASH_PROG_TIMEOUT); 782 if (ret) 783 break; 784 785 cmd_len = 1; 786 offset += 2; 787 } 788 789 if (!ret) 790 ret = spi_flash_cmd_write_disable(flash); 791 792 /* If there is a single trailing byte, write it out */ 793 if (!ret && actual != len) 794 ret = sst_byte_write(flash, offset, buf + actual); 795 796 done: 797 debug("SF: sst: program %s %zu bytes @ 0x%zx\n", 798 ret ? "failure" : "success", len, offset - actual); 799 800 spi_release_bus(spi); 801 return ret; 802 } 803 804 int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len, 805 const void *buf) 806 { 807 struct spi_slave *spi = flash->spi; 808 size_t actual; 809 int ret; 810 811 ret = spi_claim_bus(spi); 812 if (ret) { 813 debug("SF: Unable to claim SPI bus\n"); 814 return ret; 815 } 816 817 for (actual = 0; actual < len; actual++) { 818 ret = sst_byte_write(flash, offset, buf + actual); 819 if (ret) { 820 debug("SF: sst byte program failed\n"); 821 break; 822 } 823 offset++; 824 } 825 826 if (!ret) 827 ret = spi_flash_cmd_write_disable(flash); 828 829 debug("SF: sst: program %s %zu bytes @ 0x%zx\n", 830 ret ? "failure" : "success", len, offset - actual); 831 832 spi_release_bus(spi); 833 return ret; 834 } 835 #endif 836 837 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) 838 static void stm_get_locked_range(struct spi_flash *flash, u8 sr, loff_t *ofs, 839 u64 *len) 840 { 841 u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 842 int shift = ffs(mask) - 1; 843 int pow; 844 845 if (!(sr & mask)) { 846 /* No protection */ 847 *ofs = 0; 848 *len = 0; 849 } else { 850 pow = ((sr & mask) ^ mask) >> shift; 851 *len = flash->size >> pow; 852 *ofs = flash->size - *len; 853 } 854 } 855 856 /* 857 * Return 1 if the entire region is locked, 0 otherwise 858 */ 859 static int stm_is_locked_sr(struct spi_flash *flash, loff_t ofs, u64 len, 860 u8 sr) 861 { 862 loff_t lock_offs; 863 u64 lock_len; 864 865 stm_get_locked_range(flash, sr, &lock_offs, &lock_len); 866 867 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs); 868 } 869 870 /* 871 * Check if a region of the flash is (completely) locked. See stm_lock() for 872 * more info. 873 * 874 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and 875 * negative on errors. 876 */ 877 int stm_is_locked(struct spi_flash *flash, u32 ofs, size_t len) 878 { 879 int status; 880 u8 sr; 881 882 status = read_sr(flash, &sr); 883 if (status < 0) 884 return status; 885 886 return stm_is_locked_sr(flash, ofs, len, sr); 887 } 888 889 /* 890 * Lock a region of the flash. Compatible with ST Micro and similar flash. 891 * Supports only the block protection bits BP{0,1,2} in the status register 892 * (SR). Does not support these features found in newer SR bitfields: 893 * - TB: top/bottom protect - only handle TB=0 (top protect) 894 * - SEC: sector/block protect - only handle SEC=0 (block protect) 895 * - CMP: complement protect - only support CMP=0 (range is not complemented) 896 * 897 * Sample table portion for 8MB flash (Winbond w25q64fw): 898 * 899 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion 900 * -------------------------------------------------------------------------- 901 * X | X | 0 | 0 | 0 | NONE | NONE 902 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64 903 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32 904 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16 905 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8 906 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4 907 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2 908 * X | X | 1 | 1 | 1 | 8 MB | ALL 909 * 910 * Returns negative on errors, 0 on success. 911 */ 912 int stm_lock(struct spi_flash *flash, u32 ofs, size_t len) 913 { 914 u8 status_old, status_new; 915 u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 916 u8 shift = ffs(mask) - 1, pow, val; 917 int ret; 918 919 ret = read_sr(flash, &status_old); 920 if (ret < 0) 921 return ret; 922 923 /* SPI NOR always locks to the end */ 924 if (ofs + len != flash->size) { 925 /* Does combined region extend to end? */ 926 if (!stm_is_locked_sr(flash, ofs + len, flash->size - ofs - len, 927 status_old)) 928 return -EINVAL; 929 len = flash->size - ofs; 930 } 931 932 /* 933 * Need smallest pow such that: 934 * 935 * 1 / (2^pow) <= (len / size) 936 * 937 * so (assuming power-of-2 size) we do: 938 * 939 * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len)) 940 */ 941 pow = ilog2(flash->size) - ilog2(len); 942 val = mask - (pow << shift); 943 if (val & ~mask) 944 return -EINVAL; 945 946 /* Don't "lock" with no region! */ 947 if (!(val & mask)) 948 return -EINVAL; 949 950 status_new = (status_old & ~mask) | val; 951 952 /* Only modify protection if it will not unlock other areas */ 953 if ((status_new & mask) <= (status_old & mask)) 954 return -EINVAL; 955 956 write_sr(flash, status_new); 957 958 return 0; 959 } 960 961 /* 962 * Unlock a region of the flash. See stm_lock() for more info 963 * 964 * Returns negative on errors, 0 on success. 965 */ 966 int stm_unlock(struct spi_flash *flash, u32 ofs, size_t len) 967 { 968 uint8_t status_old, status_new; 969 u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 970 u8 shift = ffs(mask) - 1, pow, val; 971 int ret; 972 973 ret = read_sr(flash, &status_old); 974 if (ret < 0) 975 return ret; 976 977 /* Cannot unlock; would unlock larger region than requested */ 978 if (stm_is_locked_sr(flash, ofs - flash->erase_size, flash->erase_size, 979 status_old)) 980 return -EINVAL; 981 /* 982 * Need largest pow such that: 983 * 984 * 1 / (2^pow) >= (len / size) 985 * 986 * so (assuming power-of-2 size) we do: 987 * 988 * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len)) 989 */ 990 pow = ilog2(flash->size) - order_base_2(flash->size - (ofs + len)); 991 if (ofs + len == flash->size) { 992 val = 0; /* fully unlocked */ 993 } else { 994 val = mask - (pow << shift); 995 /* Some power-of-two sizes are not supported */ 996 if (val & ~mask) 997 return -EINVAL; 998 } 999 1000 status_new = (status_old & ~mask) | val; 1001 1002 /* Only modify protection if it will not lock other areas */ 1003 if ((status_new & mask) >= (status_old & mask)) 1004 return -EINVAL; 1005 1006 write_sr(flash, status_new); 1007 1008 return 0; 1009 } 1010 #endif 1011 1012 1013 #if defined(CONFIG_SPI_FLASH_MACRONIX) || defined(CONFIG_SPI_FLASH_GIGADEVICE) 1014 static int macronix_quad_enable(struct spi_flash *flash) 1015 { 1016 u8 qeb_status; 1017 int ret; 1018 1019 ret = read_sr(flash, &qeb_status); 1020 if (ret < 0) 1021 return ret; 1022 1023 if (qeb_status & STATUS_QEB_MXIC) 1024 return 0; 1025 1026 ret = write_sr(flash, qeb_status | STATUS_QEB_MXIC); 1027 if (ret < 0) 1028 return ret; 1029 1030 /* read SR and check it */ 1031 ret = read_sr(flash, &qeb_status); 1032 if (!(ret >= 0 && (qeb_status & STATUS_QEB_MXIC))) { 1033 printf("SF: Macronix SR Quad bit not clear\n"); 1034 return -EINVAL; 1035 } 1036 1037 return ret; 1038 } 1039 #endif 1040 1041 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 1042 static int spansion_quad_enable(struct spi_flash *flash) 1043 { 1044 u8 qeb_status; 1045 int ret; 1046 1047 ret = read_cr(flash, &qeb_status); 1048 if (ret < 0) 1049 return ret; 1050 1051 if (qeb_status & STATUS_QEB_WINSPAN) 1052 return 0; 1053 1054 ret = write_cr(flash, qeb_status | STATUS_QEB_WINSPAN); 1055 if (ret < 0) 1056 return ret; 1057 1058 /* read CR and check it */ 1059 ret = read_cr(flash, &qeb_status); 1060 if (!(ret >= 0 && (qeb_status & STATUS_QEB_WINSPAN))) { 1061 printf("SF: Spansion CR Quad bit not clear\n"); 1062 return -EINVAL; 1063 } 1064 1065 return ret; 1066 } 1067 #endif 1068 1069 static const struct spi_flash_info *spi_flash_read_id(struct spi_flash *flash) 1070 { 1071 int tmp; 1072 u8 id[SPI_FLASH_MAX_ID_LEN]; 1073 const struct spi_flash_info *info; 1074 1075 tmp = spi_flash_cmd(flash->spi, CMD_READ_ID, id, SPI_FLASH_MAX_ID_LEN); 1076 if (tmp < 0) { 1077 printf("SF: error %d reading JEDEC ID\n", tmp); 1078 return ERR_PTR(tmp); 1079 } 1080 1081 info = spi_flash_ids; 1082 for (; info->name != NULL; info++) { 1083 if (info->id_len) { 1084 if (!memcmp(info->id, id, info->id_len)) 1085 return info; 1086 } 1087 } 1088 1089 printf("SF: unrecognized JEDEC id bytes: %02x, %02x, %02x\n", 1090 id[0], id[1], id[2]); 1091 return ERR_PTR(-ENODEV); 1092 } 1093 1094 static int set_quad_mode(struct spi_flash *flash, 1095 const struct spi_flash_info *info) 1096 { 1097 switch (JEDEC_MFR(info)) { 1098 #if defined(CONFIG_SPI_FLASH_MACRONIX) || defined(CONFIG_SPI_FLASH_GIGADEVICE) 1099 case SPI_FLASH_CFI_MFR_MACRONIX: 1100 case SPI_FLASH_CIF_MFR_GIGADEVICE: 1101 return macronix_quad_enable(flash); 1102 #endif 1103 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 1104 case SPI_FLASH_CFI_MFR_SPANSION: 1105 case SPI_FLASH_CFI_MFR_WINBOND: 1106 return spansion_quad_enable(flash); 1107 #endif 1108 #ifdef CONFIG_SPI_FLASH_STMICRO 1109 case SPI_FLASH_CFI_MFR_STMICRO: 1110 case SPI_FLASH_CFI_MFR_MICRON: 1111 debug("SF: QEB is volatile for %02x flash\n", JEDEC_MFR(info)); 1112 return 0; 1113 #endif 1114 default: 1115 printf("SF: Need set QEB func for %02x flash\n", 1116 JEDEC_MFR(info)); 1117 return -1; 1118 } 1119 } 1120 1121 #if CONFIG_IS_ENABLED(OF_CONTROL) 1122 int spi_flash_decode_fdt(struct spi_flash *flash) 1123 { 1124 #ifdef CONFIG_DM_SPI_FLASH 1125 fdt_addr_t addr; 1126 fdt_size_t size; 1127 1128 addr = dev_read_addr_size(flash->dev, "memory-map", &size); 1129 if (addr == FDT_ADDR_T_NONE) { 1130 debug("%s: Cannot decode address\n", __func__); 1131 return 0; 1132 } 1133 1134 if (flash->size > size) { 1135 debug("%s: Memory map must cover entire device\n", __func__); 1136 return -1; 1137 } 1138 flash->memory_map = map_sysmem(addr, size); 1139 #endif 1140 1141 return 0; 1142 } 1143 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */ 1144 1145 int spi_flash_scan(struct spi_flash *flash) 1146 { 1147 struct spi_slave *spi = flash->spi; 1148 const struct spi_flash_info *info = NULL; 1149 int ret; 1150 1151 info = spi_flash_read_id(flash); 1152 if (IS_ERR_OR_NULL(info)) 1153 return -ENOENT; 1154 1155 /* 1156 * Flash powers up read-only, so clear BP# bits. 1157 * 1158 * Note on some flash (like Macronix), QE (quad enable) bit is in the 1159 * same status register as BP# bits, and we need preserve its original 1160 * value during a reboot cycle as this is required by some platforms 1161 * (like Intel ICH SPI controller working under descriptor mode). 1162 */ 1163 if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_ATMEL || 1164 (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) || 1165 (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX)) { 1166 u8 sr = 0; 1167 1168 if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX) { 1169 read_sr(flash, &sr); 1170 sr &= STATUS_QEB_MXIC; 1171 } 1172 write_sr(flash, sr); 1173 } 1174 1175 flash->name = info->name; 1176 flash->memory_map = spi->memory_map; 1177 1178 if (info->flags & SST_WR) 1179 flash->flags |= SNOR_F_SST_WR; 1180 1181 #ifndef CONFIG_DM_SPI_FLASH 1182 flash->write = spi_flash_cmd_write_ops; 1183 #if defined(CONFIG_SPI_FLASH_SST) 1184 if (flash->flags & SNOR_F_SST_WR) { 1185 if (spi->mode & SPI_TX_BYTE) 1186 flash->write = sst_write_bp; 1187 else 1188 flash->write = sst_write_wp; 1189 } 1190 #endif 1191 flash->erase = spi_flash_cmd_erase_ops; 1192 flash->read = spi_flash_cmd_read_ops; 1193 #endif 1194 1195 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) 1196 /* NOR protection support for STmicro/Micron chips and similar */ 1197 if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_STMICRO || 1198 JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MICRON || 1199 JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) { 1200 flash->flash_lock = stm_lock; 1201 flash->flash_unlock = stm_unlock; 1202 flash->flash_is_locked = stm_is_locked; 1203 } 1204 #endif 1205 1206 /* sst26wf series block protection implementation differs from other series */ 1207 #if defined(CONFIG_SPI_FLASH_SST) 1208 if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST && info->id[1] == 0x26) { 1209 flash->flash_lock = sst26_lock; 1210 flash->flash_unlock = sst26_unlock; 1211 flash->flash_is_locked = sst26_is_locked; 1212 } 1213 #endif 1214 1215 /* Compute the flash size */ 1216 flash->shift = (flash->dual_flash & SF_DUAL_PARALLEL_FLASH) ? 1 : 0; 1217 flash->page_size = info->page_size; 1218 /* 1219 * The Spansion S25FS512S, S25FL032P and S25FL064P have 256b pages, 1220 * yet use the 0x4d00 Extended JEDEC code. The rest of the Spansion 1221 * flashes with the 0x4d00 Extended JEDEC code have 512b pages. 1222 * All of the others have 256b pages. 1223 */ 1224 if (JEDEC_EXT(info) == 0x4d00) { 1225 if ((JEDEC_ID(info) != 0x0215) && 1226 (JEDEC_ID(info) != 0x0216) && 1227 (JEDEC_ID(info) != 0x0220)) 1228 flash->page_size = 512; 1229 } 1230 flash->page_size <<= flash->shift; 1231 flash->sector_size = info->sector_size << flash->shift; 1232 flash->size = flash->sector_size * info->n_sectors << flash->shift; 1233 #ifdef CONFIG_SF_DUAL_FLASH 1234 if (flash->dual_flash & SF_DUAL_STACKED_FLASH) 1235 flash->size <<= 1; 1236 #endif 1237 1238 #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS 1239 /* Compute erase sector and command */ 1240 if (info->flags & SECT_4K) { 1241 flash->erase_cmd = CMD_ERASE_4K; 1242 flash->erase_size = 4096 << flash->shift; 1243 } else 1244 #endif 1245 { 1246 flash->erase_cmd = CMD_ERASE_64K; 1247 flash->erase_size = flash->sector_size; 1248 } 1249 1250 /* Now erase size becomes valid sector size */ 1251 flash->sector_size = flash->erase_size; 1252 1253 /* Look for read commands */ 1254 flash->read_cmd = CMD_READ_ARRAY_FAST; 1255 if (spi->mode & SPI_RX_SLOW) 1256 flash->read_cmd = CMD_READ_ARRAY_SLOW; 1257 else if (spi->mode & SPI_RX_QUAD && info->flags & RD_QUAD) 1258 flash->read_cmd = CMD_READ_QUAD_OUTPUT_FAST; 1259 else if (spi->mode & SPI_RX_DUAL && info->flags & RD_DUAL) 1260 flash->read_cmd = CMD_READ_DUAL_OUTPUT_FAST; 1261 1262 /* Look for write commands */ 1263 if (info->flags & WR_QPP && spi->mode & SPI_TX_QUAD) 1264 flash->write_cmd = CMD_QUAD_PAGE_PROGRAM; 1265 else 1266 /* Go for default supported write cmd */ 1267 flash->write_cmd = CMD_PAGE_PROGRAM; 1268 1269 /* Set the quad enable bit - only for quad commands */ 1270 if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) || 1271 (flash->read_cmd == CMD_READ_QUAD_IO_FAST) || 1272 (flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) { 1273 ret = set_quad_mode(flash, info); 1274 if (ret) { 1275 debug("SF: Fail to set QEB for %02x\n", 1276 JEDEC_MFR(info)); 1277 return -EINVAL; 1278 } 1279 } 1280 1281 /* Read dummy_byte: dummy byte is determined based on the 1282 * dummy cycles of a particular command. 1283 * Fast commands - dummy_byte = dummy_cycles/8 1284 * I/O commands- dummy_byte = (dummy_cycles * no.of lines)/8 1285 * For I/O commands except cmd[0] everything goes on no.of lines 1286 * based on particular command but incase of fast commands except 1287 * data all go on single line irrespective of command. 1288 */ 1289 switch (flash->read_cmd) { 1290 case CMD_READ_QUAD_IO_FAST: 1291 flash->dummy_byte = 2; 1292 break; 1293 case CMD_READ_ARRAY_SLOW: 1294 flash->dummy_byte = 0; 1295 break; 1296 default: 1297 flash->dummy_byte = 1; 1298 } 1299 1300 #ifdef CONFIG_SPI_FLASH_STMICRO 1301 if (info->flags & E_FSR) 1302 flash->flags |= SNOR_F_USE_FSR; 1303 #endif 1304 1305 /* Configure the BAR - discover bank cmds and read current bank */ 1306 #ifdef CONFIG_SPI_FLASH_BAR 1307 ret = read_bar(flash, info); 1308 if (ret < 0) 1309 return ret; 1310 #endif 1311 1312 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 1313 ret = spi_flash_decode_fdt(flash); 1314 if (ret) { 1315 debug("SF: FDT decode error\n"); 1316 return -EINVAL; 1317 } 1318 #endif 1319 1320 #ifndef CONFIG_SPL_BUILD 1321 printf("SF: Detected %s with page size ", flash->name); 1322 print_size(flash->page_size, ", erase size "); 1323 print_size(flash->erase_size, ", total "); 1324 print_size(flash->size, ""); 1325 if (flash->memory_map) 1326 printf(", mapped at %p", flash->memory_map); 1327 puts("\n"); 1328 #endif 1329 1330 #ifndef CONFIG_SPI_FLASH_BAR 1331 if (((flash->dual_flash == SF_SINGLE_FLASH) && 1332 (flash->size > SPI_FLASH_16MB_BOUN)) || 1333 ((flash->dual_flash > SF_SINGLE_FLASH) && 1334 (flash->size > SPI_FLASH_16MB_BOUN << 1))) { 1335 puts("SF: Warning - Only lower 16MiB accessible,"); 1336 puts(" Full access #define CONFIG_SPI_FLASH_BAR\n"); 1337 } 1338 #endif 1339 1340 return 0; 1341 } 1342