xref: /rk3399_rockchip-uboot/drivers/mtd/spi/spi_flash.c (revision acc237544a0a6b5ebfd41fccf12a7731db209959)
1 /*
2  * SPI flash interface
3  *
4  * Copyright (C) 2008 Atmel Corporation
5  * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik
6  *
7  * Licensed under the GPL-2 or later.
8  */
9 
10 #include <common.h>
11 #include <fdtdec.h>
12 #include <malloc.h>
13 #include <spi.h>
14 #include <spi_flash.h>
15 #include <watchdog.h>
16 
17 #include "spi_flash_internal.h"
18 
19 DECLARE_GLOBAL_DATA_PTR;
20 
21 static void spi_flash_addr(u32 addr, u8 *cmd)
22 {
23 	/* cmd[0] is actual command */
24 	cmd[1] = addr >> 16;
25 	cmd[2] = addr >> 8;
26 	cmd[3] = addr >> 0;
27 }
28 
29 static int spi_flash_read_write(struct spi_slave *spi,
30 				const u8 *cmd, size_t cmd_len,
31 				const u8 *data_out, u8 *data_in,
32 				size_t data_len)
33 {
34 	unsigned long flags = SPI_XFER_BEGIN;
35 	int ret;
36 
37 	if (data_len == 0)
38 		flags |= SPI_XFER_END;
39 
40 	ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags);
41 	if (ret) {
42 		debug("SF: Failed to send command (%zu bytes): %d\n",
43 				cmd_len, ret);
44 	} else if (data_len != 0) {
45 		ret = spi_xfer(spi, data_len * 8, data_out, data_in, SPI_XFER_END);
46 		if (ret)
47 			debug("SF: Failed to transfer %zu bytes of data: %d\n",
48 					data_len, ret);
49 	}
50 
51 	return ret;
52 }
53 
54 int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len)
55 {
56 	return spi_flash_cmd_read(spi, &cmd, 1, response, len);
57 }
58 
59 int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd,
60 		size_t cmd_len, void *data, size_t data_len)
61 {
62 	return spi_flash_read_write(spi, cmd, cmd_len, NULL, data, data_len);
63 }
64 
65 int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len,
66 		const void *data, size_t data_len)
67 {
68 	return spi_flash_read_write(spi, cmd, cmd_len, data, NULL, data_len);
69 }
70 
71 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
72 		size_t cmd_len, const void *buf, size_t buf_len)
73 {
74 	struct spi_slave *spi = flash->spi;
75 	unsigned long timeout = SPI_FLASH_PROG_TIMEOUT;
76 	int ret;
77 
78 	if (buf == NULL)
79 		timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT;
80 
81 	ret = spi_claim_bus(flash->spi);
82 	if (ret) {
83 		debug("SF: unable to claim SPI bus\n");
84 		return ret;
85 	}
86 
87 	ret = spi_flash_cmd_write_enable(flash);
88 	if (ret < 0) {
89 		debug("SF: enabling write failed\n");
90 		return ret;
91 	}
92 
93 	ret = spi_flash_cmd_write(spi, cmd, cmd_len, buf, buf_len);
94 	if (ret < 0) {
95 		debug("SF: write cmd failed\n");
96 		return ret;
97 	}
98 
99 	ret = spi_flash_cmd_wait_ready(flash, timeout);
100 	if (ret < 0) {
101 		debug("SF: write %s timed out\n",
102 			timeout == SPI_FLASH_PROG_TIMEOUT ?
103 			"program" : "page erase");
104 		return ret;
105 	}
106 
107 	spi_release_bus(spi);
108 
109 	return ret;
110 }
111 
112 int spi_flash_cmd_write_multi(struct spi_flash *flash, u32 offset,
113 		size_t len, const void *buf)
114 {
115 	unsigned long byte_addr, page_size;
116 	size_t chunk_len, actual;
117 	u8 cmd[4];
118 	int ret = -1;
119 
120 	page_size = flash->page_size;
121 
122 	cmd[0] = CMD_PAGE_PROGRAM;
123 	for (actual = 0; actual < len; actual += chunk_len) {
124 #ifdef CONFIG_SPI_FLASH_BAR
125 		u8 bank_sel;
126 
127 		bank_sel = offset / SPI_FLASH_16MB_BOUN;
128 
129 		ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
130 		if (ret) {
131 			debug("SF: fail to set bank%d\n", bank_sel);
132 			return ret;
133 		}
134 #endif
135 		byte_addr = offset % page_size;
136 		chunk_len = min(len - actual, page_size - byte_addr);
137 
138 		if (flash->spi->max_write_size)
139 			chunk_len = min(chunk_len, flash->spi->max_write_size);
140 
141 		spi_flash_addr(offset, cmd);
142 
143 		debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
144 		      buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
145 
146 		ret = spi_flash_write_common(flash, cmd, sizeof(cmd),
147 					buf + actual, chunk_len);
148 		if (ret < 0) {
149 			debug("SF: write failed\n");
150 			break;
151 		}
152 
153 		offset += chunk_len;
154 	}
155 
156 	return ret;
157 }
158 
159 int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
160 		size_t cmd_len, void *data, size_t data_len)
161 {
162 	struct spi_slave *spi = flash->spi;
163 	int ret;
164 
165 	spi_claim_bus(spi);
166 	ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len);
167 	spi_release_bus(spi);
168 
169 	return ret;
170 }
171 
172 int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,
173 		size_t len, void *data)
174 {
175 	u8 cmd[5], bank_sel = 0;
176 	u32 remain_len, read_len;
177 	int ret = -1;
178 
179 	/* Handle memory-mapped SPI */
180 	if (flash->memory_map) {
181 		memcpy(data, flash->memory_map + offset, len);
182 		return 0;
183 	}
184 
185 	cmd[0] = CMD_READ_ARRAY_FAST;
186 	cmd[4] = 0x00;
187 
188 	while (len) {
189 #ifdef CONFIG_SPI_FLASH_BAR
190 		bank_sel = offset / SPI_FLASH_16MB_BOUN;
191 
192 		ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
193 		if (ret) {
194 			debug("SF: fail to set bank%d\n", bank_sel);
195 			return ret;
196 		}
197 #endif
198 		remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1) - offset);
199 		if (len < remain_len)
200 			read_len = len;
201 		else
202 			read_len = remain_len;
203 
204 		spi_flash_addr(offset, cmd);
205 
206 		ret = spi_flash_read_common(flash, cmd, sizeof(cmd),
207 							data, read_len);
208 		if (ret < 0) {
209 			debug("SF: read failed\n");
210 			break;
211 		}
212 
213 		offset += read_len;
214 		len -= read_len;
215 		data += read_len;
216 	}
217 
218 	return ret;
219 }
220 
221 int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout)
222 {
223 	struct spi_slave *spi = flash->spi;
224 	unsigned long timebase;
225 	int ret;
226 	u8 status;
227 	u8 check_status = 0x0;
228 	u8 poll_bit = STATUS_WIP;
229 	u8 cmd = flash->poll_cmd;
230 
231 	if (cmd == CMD_FLAG_STATUS) {
232 		poll_bit = STATUS_PEC;
233 		check_status = poll_bit;
234 	}
235 
236 	ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN);
237 	if (ret) {
238 		debug("SF: fail to read %s status register\n",
239 			cmd == CMD_READ_STATUS ? "read" : "flag");
240 		return ret;
241 	}
242 
243 	timebase = get_timer(0);
244 	do {
245 		WATCHDOG_RESET();
246 
247 		ret = spi_xfer(spi, 8, NULL, &status, 0);
248 		if (ret)
249 			return -1;
250 
251 		if ((status & poll_bit) == check_status)
252 			break;
253 
254 	} while (get_timer(timebase) < timeout);
255 
256 	spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);
257 
258 	if ((status & poll_bit) == check_status)
259 		return 0;
260 
261 	/* Timed out */
262 	debug("SF: time out!\n");
263 	return -1;
264 }
265 
266 int spi_flash_cmd_erase(struct spi_flash *flash, u32 offset, size_t len)
267 {
268 	u32 erase_size;
269 	u8 cmd[4];
270 	int ret = -1;
271 
272 	erase_size = flash->sector_size;
273 	if (offset % erase_size || len % erase_size) {
274 		debug("SF: Erase offset/length not multiple of erase size\n");
275 		return -1;
276 	}
277 
278 	if (erase_size == 4096)
279 		cmd[0] = CMD_ERASE_4K;
280 	else
281 		cmd[0] = CMD_ERASE_64K;
282 
283 	while (len) {
284 #ifdef CONFIG_SPI_FLASH_BAR
285 		u8 bank_sel;
286 
287 		bank_sel = offset / SPI_FLASH_16MB_BOUN;
288 
289 		ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
290 		if (ret) {
291 			debug("SF: fail to set bank%d\n", bank_sel);
292 			return ret;
293 		}
294 #endif
295 		spi_flash_addr(offset, cmd);
296 
297 		debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
298 		      cmd[2], cmd[3], offset);
299 
300 		ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0);
301 		if (ret < 0) {
302 			debug("SF: erase failed\n");
303 			break;
304 		}
305 
306 		offset += erase_size;
307 		len -= erase_size;
308 	}
309 
310 	return ret;
311 }
312 
313 int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
314 {
315 	u8 cmd;
316 	int ret;
317 
318 	cmd = CMD_WRITE_STATUS;
319 	ret = spi_flash_write_common(flash, &cmd, 1, &sr, 1);
320 	if (ret < 0) {
321 		debug("SF: fail to write status register\n");
322 		return ret;
323 	}
324 
325 	return 0;
326 }
327 
328 #ifdef CONFIG_SPI_FLASH_BAR
329 int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel)
330 {
331 	u8 cmd;
332 	int ret;
333 
334 	if (flash->bank_curr == bank_sel) {
335 		debug("SF: not require to enable bank%d\n", bank_sel);
336 		return 0;
337 	}
338 
339 	cmd = flash->bank_write_cmd;
340 	ret = spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1);
341 	if (ret < 0) {
342 		debug("SF: fail to write bank register\n");
343 		return ret;
344 	}
345 	flash->bank_curr = bank_sel;
346 
347 	return 0;
348 }
349 
350 int spi_flash_bank_config(struct spi_flash *flash, u8 idcode0)
351 {
352 	u8 cmd;
353 	u8 curr_bank = 0;
354 
355 	/* discover bank cmds */
356 	switch (idcode0) {
357 	case SPI_FLASH_SPANSION_IDCODE0:
358 		flash->bank_read_cmd = CMD_BANKADDR_BRRD;
359 		flash->bank_write_cmd = CMD_BANKADDR_BRWR;
360 		break;
361 	case SPI_FLASH_STMICRO_IDCODE0:
362 	case SPI_FLASH_WINBOND_IDCODE0:
363 		flash->bank_read_cmd = CMD_EXTNADDR_RDEAR;
364 		flash->bank_write_cmd = CMD_EXTNADDR_WREAR;
365 		break;
366 	default:
367 		printf("SF: Unsupported bank commands %02x\n", idcode0);
368 		return -1;
369 	}
370 
371 	/* read the bank reg - on which bank the flash is in currently */
372 	cmd = flash->bank_read_cmd;
373 	if (flash->size > SPI_FLASH_16MB_BOUN) {
374 		if (spi_flash_read_common(flash, &cmd, 1, &curr_bank, 1)) {
375 			debug("SF: fail to read bank addr register\n");
376 			return -1;
377 		}
378 		flash->bank_curr = curr_bank;
379 	} else {
380 		flash->bank_curr = curr_bank;
381 	}
382 
383 	return 0;
384 }
385 #endif
386 
387 #ifdef CONFIG_OF_CONTROL
388 int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
389 {
390 	fdt_addr_t addr;
391 	fdt_size_t size;
392 	int node;
393 
394 	/* If there is no node, do nothing */
395 	node = fdtdec_next_compatible(blob, 0, COMPAT_GENERIC_SPI_FLASH);
396 	if (node < 0)
397 		return 0;
398 
399 	addr = fdtdec_get_addr_size(blob, node, "memory-map", &size);
400 	if (addr == FDT_ADDR_T_NONE) {
401 		debug("%s: Cannot decode address\n", __func__);
402 		return 0;
403 	}
404 
405 	if (flash->size != size) {
406 		debug("%s: Memory map must cover entire device\n", __func__);
407 		return -1;
408 	}
409 	flash->memory_map = (void *)addr;
410 
411 	return 0;
412 }
413 #endif /* CONFIG_OF_CONTROL */
414 
415 /*
416  * The following table holds all device probe functions
417  *
418  * shift:  number of continuation bytes before the ID
419  * idcode: the expected IDCODE or 0xff for non JEDEC devices
420  * probe:  the function to call
421  *
422  * Non JEDEC devices should be ordered in the table such that
423  * the probe functions with best detection algorithms come first.
424  *
425  * Several matching entries are permitted, they will be tried
426  * in sequence until a probe function returns non NULL.
427  *
428  * IDCODE_CONT_LEN may be redefined if a device needs to declare a
429  * larger "shift" value.  IDCODE_PART_LEN generally shouldn't be
430  * changed.  This is the max number of bytes probe functions may
431  * examine when looking up part-specific identification info.
432  *
433  * Probe functions will be given the idcode buffer starting at their
434  * manu id byte (the "idcode" in the table below).  In other words,
435  * all of the continuation bytes will be skipped (the "shift" below).
436  */
437 #define IDCODE_CONT_LEN 0
438 #define IDCODE_PART_LEN 5
439 static const struct {
440 	const u8 shift;
441 	const u8 idcode;
442 	struct spi_flash *(*probe) (struct spi_slave *spi, u8 *idcode);
443 } flashes[] = {
444 	/* Keep it sorted by define name */
445 #ifdef CONFIG_SPI_FLASH_ATMEL
446 	{ 0, 0x1f, spi_flash_probe_atmel, },
447 #endif
448 #ifdef CONFIG_SPI_FLASH_EON
449 	{ 0, 0x1c, spi_flash_probe_eon, },
450 #endif
451 #ifdef CONFIG_SPI_FLASH_MACRONIX
452 	{ 0, 0xc2, spi_flash_probe_macronix, },
453 #endif
454 #ifdef CONFIG_SPI_FLASH_SPANSION
455 	{ 0, 0x01, spi_flash_probe_spansion, },
456 #endif
457 #ifdef CONFIG_SPI_FLASH_SST
458 	{ 0, 0xbf, spi_flash_probe_sst, },
459 #endif
460 #ifdef CONFIG_SPI_FLASH_STMICRO
461 	{ 0, 0x20, spi_flash_probe_stmicro, },
462 #endif
463 #ifdef CONFIG_SPI_FLASH_WINBOND
464 	{ 0, 0xef, spi_flash_probe_winbond, },
465 #endif
466 #ifdef CONFIG_SPI_FRAM_RAMTRON
467 	{ 6, 0xc2, spi_fram_probe_ramtron, },
468 # undef IDCODE_CONT_LEN
469 # define IDCODE_CONT_LEN 6
470 #endif
471 	/* Keep it sorted by best detection */
472 #ifdef CONFIG_SPI_FLASH_STMICRO
473 	{ 0, 0xff, spi_flash_probe_stmicro, },
474 #endif
475 #ifdef CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC
476 	{ 0, 0xff, spi_fram_probe_ramtron, },
477 #endif
478 };
479 #define IDCODE_LEN (IDCODE_CONT_LEN + IDCODE_PART_LEN)
480 
481 struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
482 		unsigned int max_hz, unsigned int spi_mode)
483 {
484 	struct spi_slave *spi;
485 	struct spi_flash *flash = NULL;
486 	int ret, i, shift;
487 	u8 idcode[IDCODE_LEN], *idp;
488 
489 	spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
490 	if (!spi) {
491 		printf("SF: Failed to set up slave\n");
492 		return NULL;
493 	}
494 
495 	ret = spi_claim_bus(spi);
496 	if (ret) {
497 		debug("SF: Failed to claim SPI bus: %d\n", ret);
498 		goto err_claim_bus;
499 	}
500 
501 	/* Read the ID codes */
502 	ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode));
503 	if (ret)
504 		goto err_read_id;
505 
506 #ifdef DEBUG
507 	printf("SF: Got idcodes\n");
508 	print_buffer(0, idcode, 1, sizeof(idcode), 0);
509 #endif
510 
511 	/* count the number of continuation bytes */
512 	for (shift = 0, idp = idcode;
513 	     shift < IDCODE_CONT_LEN && *idp == 0x7f;
514 	     ++shift, ++idp)
515 		continue;
516 
517 	/* search the table for matches in shift and id */
518 	for (i = 0; i < ARRAY_SIZE(flashes); ++i)
519 		if (flashes[i].shift == shift && flashes[i].idcode == *idp) {
520 			/* we have a match, call probe */
521 			flash = flashes[i].probe(spi, idp);
522 			if (flash)
523 				break;
524 		}
525 
526 	if (!flash) {
527 		printf("SF: Unsupported manufacturer %02x\n", *idp);
528 		goto err_manufacturer_probe;
529 	}
530 
531 #ifdef CONFIG_SPI_FLASH_BAR
532 	/* Configure the BAR - disover bank cmds and read current bank  */
533 	ret = spi_flash_bank_config(flash, *idp);
534 	if (ret < 0)
535 		goto err_manufacturer_probe;
536 #endif
537 
538 #ifdef CONFIG_OF_CONTROL
539 	if (spi_flash_decode_fdt(gd->fdt_blob, flash)) {
540 		debug("SF: FDT decode error\n");
541 		goto err_manufacturer_probe;
542 	}
543 #endif
544 	printf("SF: Detected %s with page size ", flash->name);
545 	print_size(flash->sector_size, ", total ");
546 	print_size(flash->size, "");
547 	if (flash->memory_map)
548 		printf(", mapped at %p", flash->memory_map);
549 	puts("\n");
550 
551 	spi_release_bus(spi);
552 
553 	return flash;
554 
555 err_manufacturer_probe:
556 err_read_id:
557 	spi_release_bus(spi);
558 err_claim_bus:
559 	spi_free_slave(spi);
560 	return NULL;
561 }
562 
563 void *spi_flash_do_alloc(int offset, int size, struct spi_slave *spi,
564 			 const char *name)
565 {
566 	struct spi_flash *flash;
567 	void *ptr;
568 
569 	ptr = malloc(size);
570 	if (!ptr) {
571 		debug("SF: Failed to allocate memory\n");
572 		return NULL;
573 	}
574 	memset(ptr, '\0', size);
575 	flash = (struct spi_flash *)(ptr + offset);
576 
577 	/* Set up some basic fields - caller will sort out sizes */
578 	flash->spi = spi;
579 	flash->name = name;
580 	flash->poll_cmd = CMD_READ_STATUS;
581 
582 	flash->read = spi_flash_cmd_read_fast;
583 	flash->write = spi_flash_cmd_write_multi;
584 	flash->erase = spi_flash_cmd_erase;
585 
586 	return flash;
587 }
588 
589 void spi_flash_free(struct spi_flash *flash)
590 {
591 	spi_free_slave(flash->spi);
592 	free(flash);
593 }
594