1 /* 2 * SPI flash interface 3 * 4 * Copyright (C) 2008 Atmel Corporation 5 * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik 6 * 7 * Licensed under the GPL-2 or later. 8 */ 9 10 #include <common.h> 11 #include <fdtdec.h> 12 #include <malloc.h> 13 #include <spi.h> 14 #include <spi_flash.h> 15 #include <watchdog.h> 16 17 #include "spi_flash_internal.h" 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 static void spi_flash_addr(u32 addr, u8 *cmd) 22 { 23 /* cmd[0] is actual command */ 24 cmd[1] = addr >> 16; 25 cmd[2] = addr >> 8; 26 cmd[3] = addr >> 0; 27 } 28 29 static int spi_flash_read_write(struct spi_slave *spi, 30 const u8 *cmd, size_t cmd_len, 31 const u8 *data_out, u8 *data_in, 32 size_t data_len) 33 { 34 unsigned long flags = SPI_XFER_BEGIN; 35 int ret; 36 37 if (data_len == 0) 38 flags |= SPI_XFER_END; 39 40 ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags); 41 if (ret) { 42 debug("SF: Failed to send command (%zu bytes): %d\n", 43 cmd_len, ret); 44 } else if (data_len != 0) { 45 ret = spi_xfer(spi, data_len * 8, data_out, data_in, 46 SPI_XFER_END); 47 if (ret) 48 debug("SF: Failed to transfer %zu bytes of data: %d\n", 49 data_len, ret); 50 } 51 52 return ret; 53 } 54 55 int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len) 56 { 57 return spi_flash_cmd_read(spi, &cmd, 1, response, len); 58 } 59 60 int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd, 61 size_t cmd_len, void *data, size_t data_len) 62 { 63 return spi_flash_read_write(spi, cmd, cmd_len, NULL, data, data_len); 64 } 65 66 int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, 67 const void *data, size_t data_len) 68 { 69 return spi_flash_read_write(spi, cmd, cmd_len, data, NULL, data_len); 70 } 71 72 int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout) 73 { 74 struct spi_slave *spi = flash->spi; 75 unsigned long timebase; 76 int ret; 77 u8 status; 78 u8 check_status = 0x0; 79 u8 poll_bit = STATUS_WIP; 80 u8 cmd = flash->poll_cmd; 81 82 if (cmd == CMD_FLAG_STATUS) { 83 poll_bit = STATUS_PEC; 84 check_status = poll_bit; 85 } 86 87 ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN); 88 if (ret) { 89 debug("SF: fail to read %s status register\n", 90 cmd == CMD_READ_STATUS ? "read" : "flag"); 91 return ret; 92 } 93 94 timebase = get_timer(0); 95 do { 96 WATCHDOG_RESET(); 97 98 ret = spi_xfer(spi, 8, NULL, &status, 0); 99 if (ret) 100 return -1; 101 102 if ((status & poll_bit) == check_status) 103 break; 104 105 } while (get_timer(timebase) < timeout); 106 107 spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END); 108 109 if ((status & poll_bit) == check_status) 110 return 0; 111 112 /* Timed out */ 113 debug("SF: time out!\n"); 114 return -1; 115 } 116 117 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, 118 size_t cmd_len, const void *buf, size_t buf_len) 119 { 120 struct spi_slave *spi = flash->spi; 121 unsigned long timeout = SPI_FLASH_PROG_TIMEOUT; 122 int ret; 123 124 if (buf == NULL) 125 timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT; 126 127 ret = spi_claim_bus(flash->spi); 128 if (ret) { 129 debug("SF: unable to claim SPI bus\n"); 130 return ret; 131 } 132 133 ret = spi_flash_cmd_write_enable(flash); 134 if (ret < 0) { 135 debug("SF: enabling write failed\n"); 136 return ret; 137 } 138 139 ret = spi_flash_cmd_write(spi, cmd, cmd_len, buf, buf_len); 140 if (ret < 0) { 141 debug("SF: write cmd failed\n"); 142 return ret; 143 } 144 145 ret = spi_flash_cmd_wait_ready(flash, timeout); 146 if (ret < 0) { 147 debug("SF: write %s timed out\n", 148 timeout == SPI_FLASH_PROG_TIMEOUT ? 149 "program" : "page erase"); 150 return ret; 151 } 152 153 spi_release_bus(spi); 154 155 return ret; 156 } 157 158 int spi_flash_cmd_erase(struct spi_flash *flash, u32 offset, size_t len) 159 { 160 u32 erase_size; 161 u8 cmd[4]; 162 int ret = -1; 163 164 erase_size = flash->sector_size; 165 if (offset % erase_size || len % erase_size) { 166 debug("SF: Erase offset/length not multiple of erase size\n"); 167 return -1; 168 } 169 170 if (erase_size == 4096) 171 cmd[0] = CMD_ERASE_4K; 172 else 173 cmd[0] = CMD_ERASE_64K; 174 175 while (len) { 176 #ifdef CONFIG_SPI_FLASH_BAR 177 u8 bank_sel; 178 179 bank_sel = offset / SPI_FLASH_16MB_BOUN; 180 181 ret = spi_flash_cmd_bankaddr_write(flash, bank_sel); 182 if (ret) { 183 debug("SF: fail to set bank%d\n", bank_sel); 184 return ret; 185 } 186 #endif 187 spi_flash_addr(offset, cmd); 188 189 debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1], 190 cmd[2], cmd[3], offset); 191 192 ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0); 193 if (ret < 0) { 194 debug("SF: erase failed\n"); 195 break; 196 } 197 198 offset += erase_size; 199 len -= erase_size; 200 } 201 202 return ret; 203 } 204 205 int spi_flash_cmd_write_multi(struct spi_flash *flash, u32 offset, 206 size_t len, const void *buf) 207 { 208 unsigned long byte_addr, page_size; 209 size_t chunk_len, actual; 210 u8 cmd[4]; 211 int ret = -1; 212 213 page_size = flash->page_size; 214 215 cmd[0] = CMD_PAGE_PROGRAM; 216 for (actual = 0; actual < len; actual += chunk_len) { 217 #ifdef CONFIG_SPI_FLASH_BAR 218 u8 bank_sel; 219 220 bank_sel = offset / SPI_FLASH_16MB_BOUN; 221 222 ret = spi_flash_cmd_bankaddr_write(flash, bank_sel); 223 if (ret) { 224 debug("SF: fail to set bank%d\n", bank_sel); 225 return ret; 226 } 227 #endif 228 byte_addr = offset % page_size; 229 chunk_len = min(len - actual, page_size - byte_addr); 230 231 if (flash->spi->max_write_size) 232 chunk_len = min(chunk_len, flash->spi->max_write_size); 233 234 spi_flash_addr(offset, cmd); 235 236 debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", 237 buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); 238 239 ret = spi_flash_write_common(flash, cmd, sizeof(cmd), 240 buf + actual, chunk_len); 241 if (ret < 0) { 242 debug("SF: write failed\n"); 243 break; 244 } 245 246 offset += chunk_len; 247 } 248 249 return ret; 250 } 251 252 int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, 253 size_t cmd_len, void *data, size_t data_len) 254 { 255 struct spi_slave *spi = flash->spi; 256 int ret; 257 258 ret = spi_claim_bus(flash->spi); 259 if (ret) { 260 debug("SF: unable to claim SPI bus\n"); 261 return ret; 262 } 263 264 ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len); 265 if (ret < 0) { 266 debug("SF: read cmd failed\n"); 267 return ret; 268 } 269 270 spi_release_bus(spi); 271 272 return ret; 273 } 274 275 int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset, 276 size_t len, void *data) 277 { 278 u8 cmd[5], bank_sel = 0; 279 u32 remain_len, read_len; 280 int ret = -1; 281 282 /* Handle memory-mapped SPI */ 283 if (flash->memory_map) { 284 memcpy(data, flash->memory_map + offset, len); 285 return 0; 286 } 287 288 cmd[0] = CMD_READ_ARRAY_FAST; 289 cmd[4] = 0x00; 290 291 while (len) { 292 #ifdef CONFIG_SPI_FLASH_BAR 293 bank_sel = offset / SPI_FLASH_16MB_BOUN; 294 295 ret = spi_flash_cmd_bankaddr_write(flash, bank_sel); 296 if (ret) { 297 debug("SF: fail to set bank%d\n", bank_sel); 298 return ret; 299 } 300 #endif 301 remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1) - offset); 302 if (len < remain_len) 303 read_len = len; 304 else 305 read_len = remain_len; 306 307 spi_flash_addr(offset, cmd); 308 309 ret = spi_flash_read_common(flash, cmd, sizeof(cmd), 310 data, read_len); 311 if (ret < 0) { 312 debug("SF: read failed\n"); 313 break; 314 } 315 316 offset += read_len; 317 len -= read_len; 318 data += read_len; 319 } 320 321 return ret; 322 } 323 324 int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr) 325 { 326 u8 cmd; 327 int ret; 328 329 cmd = CMD_WRITE_STATUS; 330 ret = spi_flash_write_common(flash, &cmd, 1, &sr, 1); 331 if (ret < 0) { 332 debug("SF: fail to write status register\n"); 333 return ret; 334 } 335 336 return 0; 337 } 338 339 #ifdef CONFIG_SPI_FLASH_BAR 340 int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel) 341 { 342 u8 cmd; 343 int ret; 344 345 if (flash->bank_curr == bank_sel) { 346 debug("SF: not require to enable bank%d\n", bank_sel); 347 return 0; 348 } 349 350 cmd = flash->bank_write_cmd; 351 ret = spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1); 352 if (ret < 0) { 353 debug("SF: fail to write bank register\n"); 354 return ret; 355 } 356 flash->bank_curr = bank_sel; 357 358 return 0; 359 } 360 361 int spi_flash_bank_config(struct spi_flash *flash, u8 idcode0) 362 { 363 u8 cmd; 364 u8 curr_bank = 0; 365 366 /* discover bank cmds */ 367 switch (idcode0) { 368 case SPI_FLASH_SPANSION_IDCODE0: 369 flash->bank_read_cmd = CMD_BANKADDR_BRRD; 370 flash->bank_write_cmd = CMD_BANKADDR_BRWR; 371 break; 372 case SPI_FLASH_STMICRO_IDCODE0: 373 case SPI_FLASH_WINBOND_IDCODE0: 374 flash->bank_read_cmd = CMD_EXTNADDR_RDEAR; 375 flash->bank_write_cmd = CMD_EXTNADDR_WREAR; 376 break; 377 default: 378 printf("SF: Unsupported bank commands %02x\n", idcode0); 379 return -1; 380 } 381 382 /* read the bank reg - on which bank the flash is in currently */ 383 cmd = flash->bank_read_cmd; 384 if (flash->size > SPI_FLASH_16MB_BOUN) { 385 if (spi_flash_read_common(flash, &cmd, 1, &curr_bank, 1)) { 386 debug("SF: fail to read bank addr register\n"); 387 return -1; 388 } 389 flash->bank_curr = curr_bank; 390 } else { 391 flash->bank_curr = curr_bank; 392 } 393 394 return 0; 395 } 396 #endif 397 398 #ifdef CONFIG_OF_CONTROL 399 int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash) 400 { 401 fdt_addr_t addr; 402 fdt_size_t size; 403 int node; 404 405 /* If there is no node, do nothing */ 406 node = fdtdec_next_compatible(blob, 0, COMPAT_GENERIC_SPI_FLASH); 407 if (node < 0) 408 return 0; 409 410 addr = fdtdec_get_addr_size(blob, node, "memory-map", &size); 411 if (addr == FDT_ADDR_T_NONE) { 412 debug("%s: Cannot decode address\n", __func__); 413 return 0; 414 } 415 416 if (flash->size != size) { 417 debug("%s: Memory map must cover entire device\n", __func__); 418 return -1; 419 } 420 flash->memory_map = (void *)addr; 421 422 return 0; 423 } 424 #endif /* CONFIG_OF_CONTROL */ 425 426 /* 427 * The following table holds all device probe functions 428 * 429 * shift: number of continuation bytes before the ID 430 * idcode: the expected IDCODE or 0xff for non JEDEC devices 431 * probe: the function to call 432 * 433 * Non JEDEC devices should be ordered in the table such that 434 * the probe functions with best detection algorithms come first. 435 * 436 * Several matching entries are permitted, they will be tried 437 * in sequence until a probe function returns non NULL. 438 * 439 * IDCODE_CONT_LEN may be redefined if a device needs to declare a 440 * larger "shift" value. IDCODE_PART_LEN generally shouldn't be 441 * changed. This is the max number of bytes probe functions may 442 * examine when looking up part-specific identification info. 443 * 444 * Probe functions will be given the idcode buffer starting at their 445 * manu id byte (the "idcode" in the table below). In other words, 446 * all of the continuation bytes will be skipped (the "shift" below). 447 */ 448 #define IDCODE_CONT_LEN 0 449 #define IDCODE_PART_LEN 5 450 static const struct { 451 const u8 shift; 452 const u8 idcode; 453 struct spi_flash *(*probe) (struct spi_slave *spi, u8 *idcode); 454 } flashes[] = { 455 /* Keep it sorted by define name */ 456 #ifdef CONFIG_SPI_FLASH_ATMEL 457 { 0, 0x1f, spi_flash_probe_atmel, }, 458 #endif 459 #ifdef CONFIG_SPI_FLASH_EON 460 { 0, 0x1c, spi_flash_probe_eon, }, 461 #endif 462 #ifdef CONFIG_SPI_FLASH_GIGADEVICE 463 { 0, 0xc8, spi_flash_probe_gigadevice, }, 464 #endif 465 #ifdef CONFIG_SPI_FLASH_MACRONIX 466 { 0, 0xc2, spi_flash_probe_macronix, }, 467 #endif 468 #ifdef CONFIG_SPI_FLASH_SPANSION 469 { 0, 0x01, spi_flash_probe_spansion, }, 470 #endif 471 #ifdef CONFIG_SPI_FLASH_SST 472 { 0, 0xbf, spi_flash_probe_sst, }, 473 #endif 474 #ifdef CONFIG_SPI_FLASH_STMICRO 475 { 0, 0x20, spi_flash_probe_stmicro, }, 476 #endif 477 #ifdef CONFIG_SPI_FLASH_WINBOND 478 { 0, 0xef, spi_flash_probe_winbond, }, 479 #endif 480 #ifdef CONFIG_SPI_FRAM_RAMTRON 481 { 6, 0xc2, spi_fram_probe_ramtron, }, 482 # undef IDCODE_CONT_LEN 483 # define IDCODE_CONT_LEN 6 484 #endif 485 /* Keep it sorted by best detection */ 486 #ifdef CONFIG_SPI_FLASH_STMICRO 487 { 0, 0xff, spi_flash_probe_stmicro, }, 488 #endif 489 #ifdef CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC 490 { 0, 0xff, spi_fram_probe_ramtron, }, 491 #endif 492 }; 493 #define IDCODE_LEN (IDCODE_CONT_LEN + IDCODE_PART_LEN) 494 495 struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, 496 unsigned int max_hz, unsigned int spi_mode) 497 { 498 struct spi_slave *spi; 499 struct spi_flash *flash = NULL; 500 int ret, i, shift; 501 u8 idcode[IDCODE_LEN], *idp; 502 503 spi = spi_setup_slave(bus, cs, max_hz, spi_mode); 504 if (!spi) { 505 printf("SF: Failed to set up slave\n"); 506 return NULL; 507 } 508 509 ret = spi_claim_bus(spi); 510 if (ret) { 511 debug("SF: Failed to claim SPI bus: %d\n", ret); 512 goto err_claim_bus; 513 } 514 515 /* Read the ID codes */ 516 ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode)); 517 if (ret) 518 goto err_read_id; 519 520 #ifdef DEBUG 521 printf("SF: Got idcodes\n"); 522 print_buffer(0, idcode, 1, sizeof(idcode), 0); 523 #endif 524 525 /* count the number of continuation bytes */ 526 for (shift = 0, idp = idcode; 527 shift < IDCODE_CONT_LEN && *idp == 0x7f; 528 ++shift, ++idp) 529 continue; 530 531 /* search the table for matches in shift and id */ 532 for (i = 0; i < ARRAY_SIZE(flashes); ++i) 533 if (flashes[i].shift == shift && flashes[i].idcode == *idp) { 534 /* we have a match, call probe */ 535 flash = flashes[i].probe(spi, idp); 536 if (flash) 537 break; 538 } 539 540 if (!flash) { 541 printf("SF: Unsupported manufacturer %02x\n", *idp); 542 goto err_manufacturer_probe; 543 } 544 545 #ifdef CONFIG_SPI_FLASH_BAR 546 /* Configure the BAR - disover bank cmds and read current bank */ 547 ret = spi_flash_bank_config(flash, *idp); 548 if (ret < 0) 549 goto err_manufacturer_probe; 550 #endif 551 552 #ifdef CONFIG_OF_CONTROL 553 if (spi_flash_decode_fdt(gd->fdt_blob, flash)) { 554 debug("SF: FDT decode error\n"); 555 goto err_manufacturer_probe; 556 } 557 #endif 558 printf("SF: Detected %s with page size ", flash->name); 559 print_size(flash->sector_size, ", total "); 560 print_size(flash->size, ""); 561 if (flash->memory_map) 562 printf(", mapped at %p", flash->memory_map); 563 puts("\n"); 564 #ifndef CONFIG_SPI_FLASH_BAR 565 if (flash->size > SPI_FLASH_16MB_BOUN) { 566 puts("SF: Warning - Only lower 16MiB accessible,"); 567 puts(" Full access #define CONFIG_SPI_FLASH_BAR\n"); 568 } 569 #endif 570 571 spi_release_bus(spi); 572 573 return flash; 574 575 err_manufacturer_probe: 576 err_read_id: 577 spi_release_bus(spi); 578 err_claim_bus: 579 spi_free_slave(spi); 580 return NULL; 581 } 582 583 void *spi_flash_do_alloc(int offset, int size, struct spi_slave *spi, 584 const char *name) 585 { 586 struct spi_flash *flash; 587 void *ptr; 588 589 ptr = malloc(size); 590 if (!ptr) { 591 debug("SF: Failed to allocate memory\n"); 592 return NULL; 593 } 594 memset(ptr, '\0', size); 595 flash = (struct spi_flash *)(ptr + offset); 596 597 /* Set up some basic fields - caller will sort out sizes */ 598 flash->spi = spi; 599 flash->name = name; 600 flash->poll_cmd = CMD_READ_STATUS; 601 602 flash->read = spi_flash_cmd_read_fast; 603 flash->write = spi_flash_cmd_write_multi; 604 flash->erase = spi_flash_cmd_erase; 605 606 return flash; 607 } 608 609 void spi_flash_free(struct spi_flash *flash) 610 { 611 spi_free_slave(flash->spi); 612 free(flash); 613 } 614