1 /* 2 * SPI Flash Core 3 * 4 * Copyright (C) 2015 Jagan Teki <jteki@openedev.com> 5 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. 6 * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik 7 * Copyright (C) 2008 Atmel Corporation 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <errno.h> 14 #include <malloc.h> 15 #include <mapmem.h> 16 #include <spi.h> 17 #include <spi_flash.h> 18 #include <linux/log2.h> 19 #include <linux/sizes.h> 20 #include <dma.h> 21 22 #include "sf_internal.h" 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 static void spi_flash_addr(u32 addr, u8 *cmd) 27 { 28 /* cmd[0] is actual command */ 29 cmd[1] = addr >> 16; 30 cmd[2] = addr >> 8; 31 cmd[3] = addr >> 0; 32 } 33 34 static int read_sr(struct spi_flash *flash, u8 *rs) 35 { 36 int ret; 37 u8 cmd; 38 39 cmd = CMD_READ_STATUS; 40 ret = spi_flash_read_common(flash, &cmd, 1, rs, 1); 41 if (ret < 0) { 42 debug("SF: fail to read status register\n"); 43 return ret; 44 } 45 46 return 0; 47 } 48 49 static int read_fsr(struct spi_flash *flash, u8 *fsr) 50 { 51 int ret; 52 const u8 cmd = CMD_FLAG_STATUS; 53 54 ret = spi_flash_read_common(flash, &cmd, 1, fsr, 1); 55 if (ret < 0) { 56 debug("SF: fail to read flag status register\n"); 57 return ret; 58 } 59 60 return 0; 61 } 62 63 static int write_sr(struct spi_flash *flash, u8 ws) 64 { 65 u8 cmd; 66 int ret; 67 68 cmd = CMD_WRITE_STATUS; 69 ret = spi_flash_write_common(flash, &cmd, 1, &ws, 1); 70 if (ret < 0) { 71 debug("SF: fail to write status register\n"); 72 return ret; 73 } 74 75 return 0; 76 } 77 78 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 79 static int read_cr(struct spi_flash *flash, u8 *rc) 80 { 81 int ret; 82 u8 cmd; 83 84 cmd = CMD_READ_CONFIG; 85 ret = spi_flash_read_common(flash, &cmd, 1, rc, 1); 86 if (ret < 0) { 87 debug("SF: fail to read config register\n"); 88 return ret; 89 } 90 91 return 0; 92 } 93 94 static int write_cr(struct spi_flash *flash, u8 wc) 95 { 96 u8 data[2]; 97 u8 cmd; 98 int ret; 99 100 ret = read_sr(flash, &data[0]); 101 if (ret < 0) 102 return ret; 103 104 cmd = CMD_WRITE_STATUS; 105 data[1] = wc; 106 ret = spi_flash_write_common(flash, &cmd, 1, &data, 2); 107 if (ret) { 108 debug("SF: fail to write config register\n"); 109 return ret; 110 } 111 112 return 0; 113 } 114 #endif 115 116 #ifdef CONFIG_SPI_FLASH_BAR 117 /* 118 * This "clean_bar" is necessary in a situation when one was accessing 119 * spi flash memory > 16 MiB by using Bank Address Register's BA24 bit. 120 * 121 * After it the BA24 bit shall be cleared to allow access to correct 122 * memory region after SW reset (by calling "reset" command). 123 * 124 * Otherwise, the BA24 bit may be left set and then after reset, the 125 * ROM would read/write/erase SPL from 16 MiB * bank_sel address. 126 */ 127 static int clean_bar(struct spi_flash *flash) 128 { 129 u8 cmd, bank_sel = 0; 130 131 if (flash->bank_curr == 0) 132 return 0; 133 cmd = flash->bank_write_cmd; 134 flash->bank_curr = 0; 135 136 return spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1); 137 } 138 139 static int write_bar(struct spi_flash *flash, u32 offset) 140 { 141 u8 cmd, bank_sel; 142 int ret; 143 144 bank_sel = offset / (SPI_FLASH_16MB_BOUN << flash->shift); 145 if (bank_sel == flash->bank_curr) 146 goto bar_end; 147 148 cmd = flash->bank_write_cmd; 149 ret = spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1); 150 if (ret < 0) { 151 debug("SF: fail to write bank register\n"); 152 return ret; 153 } 154 155 bar_end: 156 flash->bank_curr = bank_sel; 157 return flash->bank_curr; 158 } 159 160 static int read_bar(struct spi_flash *flash, const struct spi_flash_info *info) 161 { 162 u8 curr_bank = 0; 163 int ret; 164 165 if (flash->size <= SPI_FLASH_16MB_BOUN) 166 goto bar_end; 167 168 switch (JEDEC_MFR(info)) { 169 case SPI_FLASH_CFI_MFR_SPANSION: 170 flash->bank_read_cmd = CMD_BANKADDR_BRRD; 171 flash->bank_write_cmd = CMD_BANKADDR_BRWR; 172 break; 173 default: 174 flash->bank_read_cmd = CMD_EXTNADDR_RDEAR; 175 flash->bank_write_cmd = CMD_EXTNADDR_WREAR; 176 } 177 178 ret = spi_flash_read_common(flash, &flash->bank_read_cmd, 1, 179 &curr_bank, 1); 180 if (ret) { 181 debug("SF: fail to read bank addr register\n"); 182 return ret; 183 } 184 185 bar_end: 186 flash->bank_curr = curr_bank; 187 return 0; 188 } 189 #endif 190 191 #ifdef CONFIG_SF_DUAL_FLASH 192 static void spi_flash_dual(struct spi_flash *flash, u32 *addr) 193 { 194 switch (flash->dual_flash) { 195 case SF_DUAL_STACKED_FLASH: 196 if (*addr >= (flash->size >> 1)) { 197 *addr -= flash->size >> 1; 198 flash->flags |= SNOR_F_USE_UPAGE; 199 } else { 200 flash->flags &= ~SNOR_F_USE_UPAGE; 201 } 202 break; 203 case SF_DUAL_PARALLEL_FLASH: 204 *addr >>= flash->shift; 205 break; 206 default: 207 debug("SF: Unsupported dual_flash=%d\n", flash->dual_flash); 208 break; 209 } 210 } 211 #endif 212 213 static int spi_flash_sr_ready(struct spi_flash *flash) 214 { 215 u8 sr; 216 int ret; 217 218 ret = read_sr(flash, &sr); 219 if (ret < 0) 220 return ret; 221 222 return !(sr & STATUS_WIP); 223 } 224 225 static int spi_flash_fsr_ready(struct spi_flash *flash) 226 { 227 u8 fsr; 228 int ret; 229 230 ret = read_fsr(flash, &fsr); 231 if (ret < 0) 232 return ret; 233 234 return fsr & STATUS_PEC; 235 } 236 237 static int spi_flash_ready(struct spi_flash *flash) 238 { 239 int sr, fsr; 240 241 sr = spi_flash_sr_ready(flash); 242 if (sr < 0) 243 return sr; 244 245 fsr = 1; 246 if (flash->flags & SNOR_F_USE_FSR) { 247 fsr = spi_flash_fsr_ready(flash); 248 if (fsr < 0) 249 return fsr; 250 } 251 252 return sr && fsr; 253 } 254 255 static int spi_flash_wait_till_ready(struct spi_flash *flash, 256 unsigned long timeout) 257 { 258 unsigned long timebase; 259 int ret; 260 261 timebase = get_timer(0); 262 263 while (get_timer(timebase) < timeout) { 264 ret = spi_flash_ready(flash); 265 if (ret < 0) 266 return ret; 267 if (ret) 268 return 0; 269 } 270 271 printf("SF: Timeout!\n"); 272 273 return -ETIMEDOUT; 274 } 275 276 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, 277 size_t cmd_len, const void *buf, size_t buf_len) 278 { 279 struct spi_slave *spi = flash->spi; 280 unsigned long timeout = SPI_FLASH_PROG_TIMEOUT; 281 int ret; 282 283 if (buf == NULL) 284 timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT; 285 286 ret = spi_claim_bus(spi); 287 if (ret) { 288 debug("SF: unable to claim SPI bus\n"); 289 return ret; 290 } 291 292 ret = spi_flash_cmd_write_enable(flash); 293 if (ret < 0) { 294 debug("SF: enabling write failed\n"); 295 return ret; 296 } 297 298 ret = spi_flash_cmd_write(spi, cmd, cmd_len, buf, buf_len); 299 if (ret < 0) { 300 debug("SF: write cmd failed\n"); 301 return ret; 302 } 303 304 ret = spi_flash_wait_till_ready(flash, timeout); 305 if (ret < 0) { 306 debug("SF: write %s timed out\n", 307 timeout == SPI_FLASH_PROG_TIMEOUT ? 308 "program" : "page erase"); 309 return ret; 310 } 311 312 spi_release_bus(spi); 313 314 return ret; 315 } 316 317 int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) 318 { 319 u32 erase_size, erase_addr; 320 u8 cmd[SPI_FLASH_CMD_LEN]; 321 int ret = -1; 322 323 erase_size = flash->erase_size; 324 if (offset % erase_size || len % erase_size) { 325 printf("SF: Erase offset/length not multiple of erase size\n"); 326 return -1; 327 } 328 329 if (flash->flash_is_locked) { 330 if (flash->flash_is_locked(flash, offset, len) > 0) { 331 printf("offset 0x%x is protected and cannot be erased\n", 332 offset); 333 return -EINVAL; 334 } 335 } 336 337 cmd[0] = flash->erase_cmd; 338 while (len) { 339 erase_addr = offset; 340 341 #ifdef CONFIG_SF_DUAL_FLASH 342 if (flash->dual_flash > SF_SINGLE_FLASH) 343 spi_flash_dual(flash, &erase_addr); 344 #endif 345 #ifdef CONFIG_SPI_FLASH_BAR 346 ret = write_bar(flash, erase_addr); 347 if (ret < 0) 348 return ret; 349 #endif 350 spi_flash_addr(erase_addr, cmd); 351 352 debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1], 353 cmd[2], cmd[3], erase_addr); 354 355 ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0); 356 if (ret < 0) { 357 debug("SF: erase failed\n"); 358 break; 359 } 360 361 offset += erase_size; 362 len -= erase_size; 363 } 364 365 #ifdef CONFIG_SPI_FLASH_BAR 366 ret = clean_bar(flash); 367 #endif 368 369 return ret; 370 } 371 372 int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, 373 size_t len, const void *buf) 374 { 375 struct spi_slave *spi = flash->spi; 376 unsigned long byte_addr, page_size; 377 u32 write_addr; 378 size_t chunk_len, actual; 379 u8 cmd[SPI_FLASH_CMD_LEN]; 380 int ret = -1; 381 382 page_size = flash->page_size; 383 384 if (flash->flash_is_locked) { 385 if (flash->flash_is_locked(flash, offset, len) > 0) { 386 printf("offset 0x%x is protected and cannot be written\n", 387 offset); 388 return -EINVAL; 389 } 390 } 391 392 cmd[0] = flash->write_cmd; 393 for (actual = 0; actual < len; actual += chunk_len) { 394 write_addr = offset; 395 396 #ifdef CONFIG_SF_DUAL_FLASH 397 if (flash->dual_flash > SF_SINGLE_FLASH) 398 spi_flash_dual(flash, &write_addr); 399 #endif 400 #ifdef CONFIG_SPI_FLASH_BAR 401 ret = write_bar(flash, write_addr); 402 if (ret < 0) 403 return ret; 404 #endif 405 byte_addr = offset % page_size; 406 chunk_len = min(len - actual, (size_t)(page_size - byte_addr)); 407 408 if (spi->max_write_size) 409 chunk_len = min(chunk_len, 410 spi->max_write_size - sizeof(cmd)); 411 412 spi_flash_addr(write_addr, cmd); 413 414 debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", 415 buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); 416 417 ret = spi_flash_write_common(flash, cmd, sizeof(cmd), 418 buf + actual, chunk_len); 419 if (ret < 0) { 420 debug("SF: write failed\n"); 421 break; 422 } 423 424 offset += chunk_len; 425 } 426 427 #ifdef CONFIG_SPI_FLASH_BAR 428 ret = clean_bar(flash); 429 #endif 430 431 return ret; 432 } 433 434 int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, 435 size_t cmd_len, void *data, size_t data_len) 436 { 437 struct spi_slave *spi = flash->spi; 438 int ret; 439 440 ret = spi_claim_bus(spi); 441 if (ret) { 442 debug("SF: unable to claim SPI bus\n"); 443 return ret; 444 } 445 446 ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len); 447 if (ret < 0) { 448 debug("SF: read cmd failed\n"); 449 return ret; 450 } 451 452 spi_release_bus(spi); 453 454 return ret; 455 } 456 457 /* 458 * TODO: remove the weak after all the other spi_flash_copy_mmap 459 * implementations removed from drivers 460 */ 461 void __weak spi_flash_copy_mmap(void *data, void *offset, size_t len) 462 { 463 #ifdef CONFIG_DMA 464 if (!dma_memcpy(data, offset, len)) 465 return; 466 #endif 467 memcpy(data, offset, len); 468 } 469 470 int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, 471 size_t len, void *data) 472 { 473 struct spi_slave *spi = flash->spi; 474 u8 *cmd, cmdsz; 475 u32 remain_len, read_len, read_addr; 476 int bank_sel = 0; 477 int ret = -1; 478 479 /* Handle memory-mapped SPI */ 480 if (flash->memory_map) { 481 ret = spi_claim_bus(spi); 482 if (ret) { 483 debug("SF: unable to claim SPI bus\n"); 484 return ret; 485 } 486 spi_xfer(spi, 0, NULL, NULL, SPI_XFER_MMAP); 487 spi_flash_copy_mmap(data, flash->memory_map + offset, len); 488 spi_xfer(spi, 0, NULL, NULL, SPI_XFER_MMAP_END); 489 spi_release_bus(spi); 490 return 0; 491 } 492 493 cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte; 494 cmd = calloc(1, cmdsz); 495 if (!cmd) { 496 debug("SF: Failed to allocate cmd\n"); 497 return -ENOMEM; 498 } 499 500 cmd[0] = flash->read_cmd; 501 while (len) { 502 read_addr = offset; 503 504 #ifdef CONFIG_SF_DUAL_FLASH 505 if (flash->dual_flash > SF_SINGLE_FLASH) 506 spi_flash_dual(flash, &read_addr); 507 #endif 508 #ifdef CONFIG_SPI_FLASH_BAR 509 ret = write_bar(flash, read_addr); 510 if (ret < 0) 511 return ret; 512 bank_sel = flash->bank_curr; 513 #endif 514 remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) * 515 (bank_sel + 1)) - offset; 516 if (len < remain_len) 517 read_len = len; 518 else 519 read_len = remain_len; 520 521 if (spi->max_read_size) 522 read_len = min(read_len, spi->max_read_size); 523 524 spi_flash_addr(read_addr, cmd); 525 526 ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len); 527 if (ret < 0) { 528 debug("SF: read failed\n"); 529 break; 530 } 531 532 offset += read_len; 533 len -= read_len; 534 data += read_len; 535 } 536 537 #ifdef CONFIG_SPI_FLASH_BAR 538 ret = clean_bar(flash); 539 #endif 540 541 free(cmd); 542 return ret; 543 } 544 545 #ifdef CONFIG_SPI_FLASH_SST 546 static bool sst26_process_bpr(u32 bpr_size, u8 *cmd, u32 bit, enum lock_ctl ctl) 547 { 548 switch (ctl) { 549 case SST26_CTL_LOCK: 550 cmd[bpr_size - (bit / 8) - 1] |= BIT(bit % 8); 551 break; 552 case SST26_CTL_UNLOCK: 553 cmd[bpr_size - (bit / 8) - 1] &= ~BIT(bit % 8); 554 break; 555 case SST26_CTL_CHECK: 556 return !!(cmd[bpr_size - (bit / 8) - 1] & BIT(bit % 8)); 557 } 558 559 return false; 560 } 561 562 /* 563 * sst26wf016/sst26wf032/sst26wf064 have next block protection: 564 * 4x - 8 KByte blocks - read & write protection bits - upper addresses 565 * 1x - 32 KByte blocks - write protection bits 566 * rest - 64 KByte blocks - write protection bits 567 * 1x - 32 KByte blocks - write protection bits 568 * 4x - 8 KByte blocks - read & write protection bits - lower addresses 569 * 570 * We'll support only per 64k lock/unlock so lower and upper 64 KByte region 571 * will be treated as single block. 572 */ 573 574 /* 575 * Lock, unlock or check lock status of the flash region of the flash (depending 576 * on the lock_ctl value) 577 */ 578 static int sst26_lock_ctl(struct spi_flash *flash, u32 ofs, size_t len, enum lock_ctl ctl) 579 { 580 u32 i, bpr_ptr, rptr_64k, lptr_64k, bpr_size; 581 bool lower_64k = false, upper_64k = false; 582 u8 cmd, bpr_buff[SST26_MAX_BPR_REG_LEN] = {}; 583 int ret; 584 585 /* Check length and offset for 64k alignment */ 586 if ((ofs & (SZ_64K - 1)) || (len & (SZ_64K - 1))) 587 return -EINVAL; 588 589 if (ofs + len > flash->size) 590 return -EINVAL; 591 592 /* SST26 family has only 16 Mbit, 32 Mbit and 64 Mbit IC */ 593 if (flash->size != SZ_2M && 594 flash->size != SZ_4M && 595 flash->size != SZ_8M) 596 return -EINVAL; 597 598 bpr_size = 2 + (flash->size / SZ_64K / 8); 599 600 cmd = SST26_CMD_READ_BPR; 601 ret = spi_flash_read_common(flash, &cmd, 1, bpr_buff, bpr_size); 602 if (ret < 0) { 603 printf("SF: fail to read block-protection register\n"); 604 return ret; 605 } 606 607 rptr_64k = min_t(u32, ofs + len , flash->size - SST26_BOUND_REG_SIZE); 608 lptr_64k = max_t(u32, ofs, SST26_BOUND_REG_SIZE); 609 610 upper_64k = ((ofs + len) > (flash->size - SST26_BOUND_REG_SIZE)); 611 lower_64k = (ofs < SST26_BOUND_REG_SIZE); 612 613 /* Lower bits in block-protection register are about 64k region */ 614 bpr_ptr = lptr_64k / SZ_64K - 1; 615 616 /* Process 64K blocks region */ 617 while (lptr_64k < rptr_64k) { 618 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl)) 619 return EACCES; 620 621 bpr_ptr++; 622 lptr_64k += SZ_64K; 623 } 624 625 /* 32K and 8K region bits in BPR are after 64k region bits */ 626 bpr_ptr = (flash->size - 2 * SST26_BOUND_REG_SIZE) / SZ_64K; 627 628 /* Process lower 32K block region */ 629 if (lower_64k) 630 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl)) 631 return EACCES; 632 633 bpr_ptr++; 634 635 /* Process upper 32K block region */ 636 if (upper_64k) 637 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl)) 638 return EACCES; 639 640 bpr_ptr++; 641 642 /* Process lower 8K block regions */ 643 for (i = 0; i < SST26_BPR_8K_NUM; i++) { 644 if (lower_64k) 645 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl)) 646 return EACCES; 647 648 /* In 8K area BPR has both read and write protection bits */ 649 bpr_ptr += 2; 650 } 651 652 /* Process upper 8K block regions */ 653 for (i = 0; i < SST26_BPR_8K_NUM; i++) { 654 if (upper_64k) 655 if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl)) 656 return EACCES; 657 658 /* In 8K area BPR has both read and write protection bits */ 659 bpr_ptr += 2; 660 } 661 662 /* If we check region status we don't need to write BPR back */ 663 if (ctl == SST26_CTL_CHECK) 664 return 0; 665 666 cmd = SST26_CMD_WRITE_BPR; 667 ret = spi_flash_write_common(flash, &cmd, 1, bpr_buff, bpr_size); 668 if (ret < 0) { 669 printf("SF: fail to write block-protection register\n"); 670 return ret; 671 } 672 673 return 0; 674 } 675 676 static int sst26_unlock(struct spi_flash *flash, u32 ofs, size_t len) 677 { 678 return sst26_lock_ctl(flash, ofs, len, SST26_CTL_UNLOCK); 679 } 680 681 static int sst26_lock(struct spi_flash *flash, u32 ofs, size_t len) 682 { 683 return sst26_lock_ctl(flash, ofs, len, SST26_CTL_LOCK); 684 } 685 686 /* 687 * Returns EACCES (positive value) if region is locked, 0 if region is unlocked, 688 * and negative on errors. 689 */ 690 static int sst26_is_locked(struct spi_flash *flash, u32 ofs, size_t len) 691 { 692 /* 693 * is_locked function is used for check before reading or erasing flash 694 * region, so offset and length might be not 64k allighned, so adjust 695 * them to be 64k allighned as sst26_lock_ctl works only with 64k 696 * allighned regions. 697 */ 698 ofs -= ofs & (SZ_64K - 1); 699 len = len & (SZ_64K - 1) ? (len & ~(SZ_64K - 1)) + SZ_64K : len; 700 701 return sst26_lock_ctl(flash, ofs, len, SST26_CTL_CHECK); 702 } 703 704 static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf) 705 { 706 struct spi_slave *spi = flash->spi; 707 int ret; 708 u8 cmd[4] = { 709 CMD_SST_BP, 710 offset >> 16, 711 offset >> 8, 712 offset, 713 }; 714 715 debug("BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", 716 spi_w8r8(spi, CMD_READ_STATUS), buf, cmd[0], offset); 717 718 ret = spi_flash_cmd_write_enable(flash); 719 if (ret) 720 return ret; 721 722 ret = spi_flash_cmd_write(spi, cmd, sizeof(cmd), buf, 1); 723 if (ret) 724 return ret; 725 726 return spi_flash_wait_till_ready(flash, SPI_FLASH_PROG_TIMEOUT); 727 } 728 729 int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, 730 const void *buf) 731 { 732 struct spi_slave *spi = flash->spi; 733 size_t actual, cmd_len; 734 int ret; 735 u8 cmd[4]; 736 737 ret = spi_claim_bus(spi); 738 if (ret) { 739 debug("SF: Unable to claim SPI bus\n"); 740 return ret; 741 } 742 743 /* If the data is not word aligned, write out leading single byte */ 744 actual = offset % 2; 745 if (actual) { 746 ret = sst_byte_write(flash, offset, buf); 747 if (ret) 748 goto done; 749 } 750 offset += actual; 751 752 ret = spi_flash_cmd_write_enable(flash); 753 if (ret) 754 goto done; 755 756 cmd_len = 4; 757 cmd[0] = CMD_SST_AAI_WP; 758 cmd[1] = offset >> 16; 759 cmd[2] = offset >> 8; 760 cmd[3] = offset; 761 762 for (; actual < len - 1; actual += 2) { 763 debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", 764 spi_w8r8(spi, CMD_READ_STATUS), buf + actual, 765 cmd[0], offset); 766 767 ret = spi_flash_cmd_write(spi, cmd, cmd_len, 768 buf + actual, 2); 769 if (ret) { 770 debug("SF: sst word program failed\n"); 771 break; 772 } 773 774 ret = spi_flash_wait_till_ready(flash, SPI_FLASH_PROG_TIMEOUT); 775 if (ret) 776 break; 777 778 cmd_len = 1; 779 offset += 2; 780 } 781 782 if (!ret) 783 ret = spi_flash_cmd_write_disable(flash); 784 785 /* If there is a single trailing byte, write it out */ 786 if (!ret && actual != len) 787 ret = sst_byte_write(flash, offset, buf + actual); 788 789 done: 790 debug("SF: sst: program %s %zu bytes @ 0x%zx\n", 791 ret ? "failure" : "success", len, offset - actual); 792 793 spi_release_bus(spi); 794 return ret; 795 } 796 797 int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len, 798 const void *buf) 799 { 800 struct spi_slave *spi = flash->spi; 801 size_t actual; 802 int ret; 803 804 ret = spi_claim_bus(spi); 805 if (ret) { 806 debug("SF: Unable to claim SPI bus\n"); 807 return ret; 808 } 809 810 for (actual = 0; actual < len; actual++) { 811 ret = sst_byte_write(flash, offset, buf + actual); 812 if (ret) { 813 debug("SF: sst byte program failed\n"); 814 break; 815 } 816 offset++; 817 } 818 819 if (!ret) 820 ret = spi_flash_cmd_write_disable(flash); 821 822 debug("SF: sst: program %s %zu bytes @ 0x%zx\n", 823 ret ? "failure" : "success", len, offset - actual); 824 825 spi_release_bus(spi); 826 return ret; 827 } 828 #endif 829 830 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) 831 static void stm_get_locked_range(struct spi_flash *flash, u8 sr, loff_t *ofs, 832 u64 *len) 833 { 834 u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 835 int shift = ffs(mask) - 1; 836 int pow; 837 838 if (!(sr & mask)) { 839 /* No protection */ 840 *ofs = 0; 841 *len = 0; 842 } else { 843 pow = ((sr & mask) ^ mask) >> shift; 844 *len = flash->size >> pow; 845 *ofs = flash->size - *len; 846 } 847 } 848 849 /* 850 * Return 1 if the entire region is locked, 0 otherwise 851 */ 852 static int stm_is_locked_sr(struct spi_flash *flash, loff_t ofs, u64 len, 853 u8 sr) 854 { 855 loff_t lock_offs; 856 u64 lock_len; 857 858 stm_get_locked_range(flash, sr, &lock_offs, &lock_len); 859 860 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs); 861 } 862 863 /* 864 * Check if a region of the flash is (completely) locked. See stm_lock() for 865 * more info. 866 * 867 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and 868 * negative on errors. 869 */ 870 int stm_is_locked(struct spi_flash *flash, u32 ofs, size_t len) 871 { 872 int status; 873 u8 sr; 874 875 status = read_sr(flash, &sr); 876 if (status < 0) 877 return status; 878 879 return stm_is_locked_sr(flash, ofs, len, sr); 880 } 881 882 /* 883 * Lock a region of the flash. Compatible with ST Micro and similar flash. 884 * Supports only the block protection bits BP{0,1,2} in the status register 885 * (SR). Does not support these features found in newer SR bitfields: 886 * - TB: top/bottom protect - only handle TB=0 (top protect) 887 * - SEC: sector/block protect - only handle SEC=0 (block protect) 888 * - CMP: complement protect - only support CMP=0 (range is not complemented) 889 * 890 * Sample table portion for 8MB flash (Winbond w25q64fw): 891 * 892 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion 893 * -------------------------------------------------------------------------- 894 * X | X | 0 | 0 | 0 | NONE | NONE 895 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64 896 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32 897 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16 898 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8 899 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4 900 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2 901 * X | X | 1 | 1 | 1 | 8 MB | ALL 902 * 903 * Returns negative on errors, 0 on success. 904 */ 905 int stm_lock(struct spi_flash *flash, u32 ofs, size_t len) 906 { 907 u8 status_old, status_new; 908 u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 909 u8 shift = ffs(mask) - 1, pow, val; 910 int ret; 911 912 ret = read_sr(flash, &status_old); 913 if (ret < 0) 914 return ret; 915 916 /* SPI NOR always locks to the end */ 917 if (ofs + len != flash->size) { 918 /* Does combined region extend to end? */ 919 if (!stm_is_locked_sr(flash, ofs + len, flash->size - ofs - len, 920 status_old)) 921 return -EINVAL; 922 len = flash->size - ofs; 923 } 924 925 /* 926 * Need smallest pow such that: 927 * 928 * 1 / (2^pow) <= (len / size) 929 * 930 * so (assuming power-of-2 size) we do: 931 * 932 * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len)) 933 */ 934 pow = ilog2(flash->size) - ilog2(len); 935 val = mask - (pow << shift); 936 if (val & ~mask) 937 return -EINVAL; 938 939 /* Don't "lock" with no region! */ 940 if (!(val & mask)) 941 return -EINVAL; 942 943 status_new = (status_old & ~mask) | val; 944 945 /* Only modify protection if it will not unlock other areas */ 946 if ((status_new & mask) <= (status_old & mask)) 947 return -EINVAL; 948 949 write_sr(flash, status_new); 950 951 return 0; 952 } 953 954 /* 955 * Unlock a region of the flash. See stm_lock() for more info 956 * 957 * Returns negative on errors, 0 on success. 958 */ 959 int stm_unlock(struct spi_flash *flash, u32 ofs, size_t len) 960 { 961 uint8_t status_old, status_new; 962 u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 963 u8 shift = ffs(mask) - 1, pow, val; 964 int ret; 965 966 ret = read_sr(flash, &status_old); 967 if (ret < 0) 968 return ret; 969 970 /* Cannot unlock; would unlock larger region than requested */ 971 if (stm_is_locked_sr(flash, ofs - flash->erase_size, flash->erase_size, 972 status_old)) 973 return -EINVAL; 974 /* 975 * Need largest pow such that: 976 * 977 * 1 / (2^pow) >= (len / size) 978 * 979 * so (assuming power-of-2 size) we do: 980 * 981 * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len)) 982 */ 983 pow = ilog2(flash->size) - order_base_2(flash->size - (ofs + len)); 984 if (ofs + len == flash->size) { 985 val = 0; /* fully unlocked */ 986 } else { 987 val = mask - (pow << shift); 988 /* Some power-of-two sizes are not supported */ 989 if (val & ~mask) 990 return -EINVAL; 991 } 992 993 status_new = (status_old & ~mask) | val; 994 995 /* Only modify protection if it will not lock other areas */ 996 if ((status_new & mask) >= (status_old & mask)) 997 return -EINVAL; 998 999 write_sr(flash, status_new); 1000 1001 return 0; 1002 } 1003 #endif 1004 1005 1006 #if defined(CONFIG_SPI_FLASH_MACRONIX) || defined(CONFIG_SPI_FLASH_GIGADEVICE) 1007 static int macronix_quad_enable(struct spi_flash *flash) 1008 { 1009 u8 qeb_status; 1010 int ret; 1011 1012 ret = read_sr(flash, &qeb_status); 1013 if (ret < 0) 1014 return ret; 1015 1016 if (qeb_status & STATUS_QEB_MXIC) 1017 return 0; 1018 1019 ret = write_sr(flash, qeb_status | STATUS_QEB_MXIC); 1020 if (ret < 0) 1021 return ret; 1022 1023 /* read SR and check it */ 1024 ret = read_sr(flash, &qeb_status); 1025 if (!(ret >= 0 && (qeb_status & STATUS_QEB_MXIC))) { 1026 printf("SF: Macronix SR Quad bit not clear\n"); 1027 return -EINVAL; 1028 } 1029 1030 return ret; 1031 } 1032 #endif 1033 1034 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 1035 static int spansion_quad_enable(struct spi_flash *flash) 1036 { 1037 u8 qeb_status; 1038 int ret; 1039 1040 ret = read_cr(flash, &qeb_status); 1041 if (ret < 0) 1042 return ret; 1043 1044 if (qeb_status & STATUS_QEB_WINSPAN) 1045 return 0; 1046 1047 ret = write_cr(flash, qeb_status | STATUS_QEB_WINSPAN); 1048 if (ret < 0) 1049 return ret; 1050 1051 /* read CR and check it */ 1052 ret = read_cr(flash, &qeb_status); 1053 if (!(ret >= 0 && (qeb_status & STATUS_QEB_WINSPAN))) { 1054 printf("SF: Spansion CR Quad bit not clear\n"); 1055 return -EINVAL; 1056 } 1057 1058 return ret; 1059 } 1060 #endif 1061 1062 static const struct spi_flash_info *spi_flash_read_id(struct spi_flash *flash) 1063 { 1064 int tmp; 1065 u8 id[SPI_FLASH_MAX_ID_LEN]; 1066 const struct spi_flash_info *info; 1067 1068 tmp = spi_flash_cmd(flash->spi, CMD_READ_ID, id, SPI_FLASH_MAX_ID_LEN); 1069 if (tmp < 0) { 1070 printf("SF: error %d reading JEDEC ID\n", tmp); 1071 return ERR_PTR(tmp); 1072 } 1073 1074 info = spi_flash_ids; 1075 for (; info->name != NULL; info++) { 1076 if (info->id_len) { 1077 if (!memcmp(info->id, id, info->id_len)) 1078 return info; 1079 } 1080 } 1081 1082 printf("SF: unrecognized JEDEC id bytes: %02x, %02x, %02x\n", 1083 id[0], id[1], id[2]); 1084 return ERR_PTR(-ENODEV); 1085 } 1086 1087 static int set_quad_mode(struct spi_flash *flash, 1088 const struct spi_flash_info *info) 1089 { 1090 switch (JEDEC_MFR(info)) { 1091 #if defined(CONFIG_SPI_FLASH_MACRONIX) || defined(CONFIG_SPI_FLASH_GIGADEVICE) 1092 case SPI_FLASH_CFI_MFR_MACRONIX: 1093 case SPI_FLASH_CIF_MFR_GIGADEVICE: 1094 return macronix_quad_enable(flash); 1095 #endif 1096 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 1097 case SPI_FLASH_CFI_MFR_SPANSION: 1098 case SPI_FLASH_CFI_MFR_WINBOND: 1099 return spansion_quad_enable(flash); 1100 #endif 1101 #ifdef CONFIG_SPI_FLASH_STMICRO 1102 case SPI_FLASH_CFI_MFR_STMICRO: 1103 debug("SF: QEB is volatile for %02x flash\n", JEDEC_MFR(info)); 1104 return 0; 1105 #endif 1106 default: 1107 printf("SF: Need set QEB func for %02x flash\n", 1108 JEDEC_MFR(info)); 1109 return -1; 1110 } 1111 } 1112 1113 #if CONFIG_IS_ENABLED(OF_CONTROL) 1114 int spi_flash_decode_fdt(struct spi_flash *flash) 1115 { 1116 #ifdef CONFIG_DM_SPI_FLASH 1117 fdt_addr_t addr; 1118 fdt_size_t size; 1119 1120 addr = dev_read_addr_size(flash->dev, "memory-map", &size); 1121 if (addr == FDT_ADDR_T_NONE) { 1122 debug("%s: Cannot decode address\n", __func__); 1123 return 0; 1124 } 1125 1126 if (flash->size > size) { 1127 debug("%s: Memory map must cover entire device\n", __func__); 1128 return -1; 1129 } 1130 flash->memory_map = map_sysmem(addr, size); 1131 #endif 1132 1133 return 0; 1134 } 1135 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */ 1136 1137 int spi_flash_scan(struct spi_flash *flash) 1138 { 1139 struct spi_slave *spi = flash->spi; 1140 const struct spi_flash_info *info = NULL; 1141 int ret; 1142 1143 info = spi_flash_read_id(flash); 1144 if (IS_ERR_OR_NULL(info)) 1145 return -ENOENT; 1146 1147 /* 1148 * Flash powers up read-only, so clear BP# bits. 1149 * 1150 * Note on some flash (like Macronix), QE (quad enable) bit is in the 1151 * same status register as BP# bits, and we need preserve its original 1152 * value during a reboot cycle as this is required by some platforms 1153 * (like Intel ICH SPI controller working under descriptor mode). 1154 */ 1155 if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_ATMEL || 1156 (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) || 1157 (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX)) { 1158 u8 sr = 0; 1159 1160 if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX) { 1161 read_sr(flash, &sr); 1162 sr &= STATUS_QEB_MXIC; 1163 } 1164 write_sr(flash, sr); 1165 } 1166 1167 flash->name = info->name; 1168 flash->memory_map = spi->memory_map; 1169 1170 if (info->flags & SST_WR) 1171 flash->flags |= SNOR_F_SST_WR; 1172 1173 #ifndef CONFIG_DM_SPI_FLASH 1174 flash->write = spi_flash_cmd_write_ops; 1175 #if defined(CONFIG_SPI_FLASH_SST) 1176 if (flash->flags & SNOR_F_SST_WR) { 1177 if (spi->mode & SPI_TX_BYTE) 1178 flash->write = sst_write_bp; 1179 else 1180 flash->write = sst_write_wp; 1181 } 1182 #endif 1183 flash->erase = spi_flash_cmd_erase_ops; 1184 flash->read = spi_flash_cmd_read_ops; 1185 #endif 1186 1187 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) 1188 /* NOR protection support for STmicro/Micron chips and similar */ 1189 if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_STMICRO || 1190 JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) { 1191 flash->flash_lock = stm_lock; 1192 flash->flash_unlock = stm_unlock; 1193 flash->flash_is_locked = stm_is_locked; 1194 } 1195 #endif 1196 1197 /* sst26wf series block protection implementation differs from other series */ 1198 #if defined(CONFIG_SPI_FLASH_SST) 1199 if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST && info->id[1] == 0x26) { 1200 flash->flash_lock = sst26_lock; 1201 flash->flash_unlock = sst26_unlock; 1202 flash->flash_is_locked = sst26_is_locked; 1203 } 1204 #endif 1205 1206 /* Compute the flash size */ 1207 flash->shift = (flash->dual_flash & SF_DUAL_PARALLEL_FLASH) ? 1 : 0; 1208 flash->page_size = info->page_size; 1209 /* 1210 * The Spansion S25FS512S, S25FL032P and S25FL064P have 256b pages, 1211 * yet use the 0x4d00 Extended JEDEC code. The rest of the Spansion 1212 * flashes with the 0x4d00 Extended JEDEC code have 512b pages. 1213 * All of the others have 256b pages. 1214 */ 1215 if (JEDEC_EXT(info) == 0x4d00) { 1216 if ((JEDEC_ID(info) != 0x0215) && 1217 (JEDEC_ID(info) != 0x0216) && 1218 (JEDEC_ID(info) != 0x0220)) 1219 flash->page_size = 512; 1220 } 1221 flash->page_size <<= flash->shift; 1222 flash->sector_size = info->sector_size << flash->shift; 1223 flash->size = flash->sector_size * info->n_sectors << flash->shift; 1224 #ifdef CONFIG_SF_DUAL_FLASH 1225 if (flash->dual_flash & SF_DUAL_STACKED_FLASH) 1226 flash->size <<= 1; 1227 #endif 1228 1229 #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS 1230 /* Compute erase sector and command */ 1231 if (info->flags & SECT_4K) { 1232 flash->erase_cmd = CMD_ERASE_4K; 1233 flash->erase_size = 4096 << flash->shift; 1234 } else 1235 #endif 1236 { 1237 flash->erase_cmd = CMD_ERASE_64K; 1238 flash->erase_size = flash->sector_size; 1239 } 1240 1241 /* Now erase size becomes valid sector size */ 1242 flash->sector_size = flash->erase_size; 1243 1244 /* Look for read commands */ 1245 flash->read_cmd = CMD_READ_ARRAY_FAST; 1246 if (spi->mode & SPI_RX_SLOW) 1247 flash->read_cmd = CMD_READ_ARRAY_SLOW; 1248 else if (spi->mode & SPI_RX_QUAD && info->flags & RD_QUAD) 1249 flash->read_cmd = CMD_READ_QUAD_OUTPUT_FAST; 1250 else if (spi->mode & SPI_RX_DUAL && info->flags & RD_DUAL) 1251 flash->read_cmd = CMD_READ_DUAL_OUTPUT_FAST; 1252 1253 /* Look for write commands */ 1254 if (info->flags & WR_QPP && spi->mode & SPI_TX_QUAD) 1255 flash->write_cmd = CMD_QUAD_PAGE_PROGRAM; 1256 else 1257 /* Go for default supported write cmd */ 1258 flash->write_cmd = CMD_PAGE_PROGRAM; 1259 1260 /* Set the quad enable bit - only for quad commands */ 1261 if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) || 1262 (flash->read_cmd == CMD_READ_QUAD_IO_FAST) || 1263 (flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) { 1264 ret = set_quad_mode(flash, info); 1265 if (ret) { 1266 debug("SF: Fail to set QEB for %02x\n", 1267 JEDEC_MFR(info)); 1268 return -EINVAL; 1269 } 1270 } 1271 1272 /* Read dummy_byte: dummy byte is determined based on the 1273 * dummy cycles of a particular command. 1274 * Fast commands - dummy_byte = dummy_cycles/8 1275 * I/O commands- dummy_byte = (dummy_cycles * no.of lines)/8 1276 * For I/O commands except cmd[0] everything goes on no.of lines 1277 * based on particular command but incase of fast commands except 1278 * data all go on single line irrespective of command. 1279 */ 1280 switch (flash->read_cmd) { 1281 case CMD_READ_QUAD_IO_FAST: 1282 flash->dummy_byte = 2; 1283 break; 1284 case CMD_READ_ARRAY_SLOW: 1285 flash->dummy_byte = 0; 1286 break; 1287 default: 1288 flash->dummy_byte = 1; 1289 } 1290 1291 #ifdef CONFIG_SPI_FLASH_STMICRO 1292 if (info->flags & E_FSR) 1293 flash->flags |= SNOR_F_USE_FSR; 1294 #endif 1295 1296 /* Configure the BAR - discover bank cmds and read current bank */ 1297 #ifdef CONFIG_SPI_FLASH_BAR 1298 ret = read_bar(flash, info); 1299 if (ret < 0) 1300 return ret; 1301 #endif 1302 1303 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 1304 ret = spi_flash_decode_fdt(flash); 1305 if (ret) { 1306 debug("SF: FDT decode error\n"); 1307 return -EINVAL; 1308 } 1309 #endif 1310 1311 #ifndef CONFIG_SPL_BUILD 1312 printf("SF: Detected %s with page size ", flash->name); 1313 print_size(flash->page_size, ", erase size "); 1314 print_size(flash->erase_size, ", total "); 1315 print_size(flash->size, ""); 1316 if (flash->memory_map) 1317 printf(", mapped at %p", flash->memory_map); 1318 puts("\n"); 1319 #endif 1320 1321 #ifndef CONFIG_SPI_FLASH_BAR 1322 if (((flash->dual_flash == SF_SINGLE_FLASH) && 1323 (flash->size > SPI_FLASH_16MB_BOUN)) || 1324 ((flash->dual_flash > SF_SINGLE_FLASH) && 1325 (flash->size > SPI_FLASH_16MB_BOUN << 1))) { 1326 puts("SF: Warning - Only lower 16MiB accessible,"); 1327 puts(" Full access #define CONFIG_SPI_FLASH_BAR\n"); 1328 } 1329 #endif 1330 1331 return 0; 1332 } 1333