1 /* 2 * SPI Flash Core 3 * 4 * Copyright (C) 2015 Jagan Teki <jteki@openedev.com> 5 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. 6 * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik 7 * Copyright (C) 2008 Atmel Corporation 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <errno.h> 14 #include <malloc.h> 15 #include <mapmem.h> 16 #include <spi.h> 17 #include <spi_flash.h> 18 #include <linux/log2.h> 19 20 #include "sf_internal.h" 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 static void spi_flash_addr(u32 addr, u8 *cmd) 25 { 26 /* cmd[0] is actual command */ 27 cmd[1] = addr >> 16; 28 cmd[2] = addr >> 8; 29 cmd[3] = addr >> 0; 30 } 31 32 /* Read commands array */ 33 static u8 spi_read_cmds_array[] = { 34 CMD_READ_ARRAY_SLOW, 35 CMD_READ_ARRAY_FAST, 36 CMD_READ_DUAL_OUTPUT_FAST, 37 CMD_READ_DUAL_IO_FAST, 38 CMD_READ_QUAD_OUTPUT_FAST, 39 CMD_READ_QUAD_IO_FAST, 40 }; 41 42 static int read_sr(struct spi_flash *flash, u8 *rs) 43 { 44 int ret; 45 u8 cmd; 46 47 cmd = CMD_READ_STATUS; 48 ret = spi_flash_read_common(flash, &cmd, 1, rs, 1); 49 if (ret < 0) { 50 debug("SF: fail to read status register\n"); 51 return ret; 52 } 53 54 return 0; 55 } 56 57 static int read_fsr(struct spi_flash *flash, u8 *fsr) 58 { 59 int ret; 60 const u8 cmd = CMD_FLAG_STATUS; 61 62 ret = spi_flash_read_common(flash, &cmd, 1, fsr, 1); 63 if (ret < 0) { 64 debug("SF: fail to read flag status register\n"); 65 return ret; 66 } 67 68 return 0; 69 } 70 71 static int write_sr(struct spi_flash *flash, u8 ws) 72 { 73 u8 cmd; 74 int ret; 75 76 cmd = CMD_WRITE_STATUS; 77 ret = spi_flash_write_common(flash, &cmd, 1, &ws, 1); 78 if (ret < 0) { 79 debug("SF: fail to write status register\n"); 80 return ret; 81 } 82 83 return 0; 84 } 85 86 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 87 static int read_cr(struct spi_flash *flash, u8 *rc) 88 { 89 int ret; 90 u8 cmd; 91 92 cmd = CMD_READ_CONFIG; 93 ret = spi_flash_read_common(flash, &cmd, 1, rc, 1); 94 if (ret < 0) { 95 debug("SF: fail to read config register\n"); 96 return ret; 97 } 98 99 return 0; 100 } 101 102 static int write_cr(struct spi_flash *flash, u8 wc) 103 { 104 u8 data[2]; 105 u8 cmd; 106 int ret; 107 108 ret = read_sr(flash, &data[0]); 109 if (ret < 0) 110 return ret; 111 112 cmd = CMD_WRITE_STATUS; 113 data[1] = wc; 114 ret = spi_flash_write_common(flash, &cmd, 1, &data, 2); 115 if (ret) { 116 debug("SF: fail to write config register\n"); 117 return ret; 118 } 119 120 return 0; 121 } 122 #endif 123 124 #ifdef CONFIG_SPI_FLASH_BAR 125 static int spi_flash_write_bar(struct spi_flash *flash, u32 offset) 126 { 127 u8 cmd, bank_sel; 128 int ret; 129 130 bank_sel = offset / (SPI_FLASH_16MB_BOUN << flash->shift); 131 if (bank_sel == flash->bank_curr) 132 goto bar_end; 133 134 cmd = flash->bank_write_cmd; 135 ret = spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1); 136 if (ret < 0) { 137 debug("SF: fail to write bank register\n"); 138 return ret; 139 } 140 141 bar_end: 142 flash->bank_curr = bank_sel; 143 return flash->bank_curr; 144 } 145 146 static int spi_flash_read_bar(struct spi_flash *flash, u8 idcode0) 147 { 148 u8 curr_bank = 0; 149 int ret; 150 151 if (flash->size <= SPI_FLASH_16MB_BOUN) 152 goto bank_end; 153 154 switch (idcode0) { 155 case SPI_FLASH_CFI_MFR_SPANSION: 156 flash->bank_read_cmd = CMD_BANKADDR_BRRD; 157 flash->bank_write_cmd = CMD_BANKADDR_BRWR; 158 break; 159 default: 160 flash->bank_read_cmd = CMD_EXTNADDR_RDEAR; 161 flash->bank_write_cmd = CMD_EXTNADDR_WREAR; 162 } 163 164 ret = spi_flash_read_common(flash, &flash->bank_read_cmd, 1, 165 &curr_bank, 1); 166 if (ret) { 167 debug("SF: fail to read bank addr register\n"); 168 return ret; 169 } 170 171 bank_end: 172 flash->bank_curr = curr_bank; 173 return 0; 174 } 175 #endif 176 177 #ifdef CONFIG_SF_DUAL_FLASH 178 static void spi_flash_dual(struct spi_flash *flash, u32 *addr) 179 { 180 struct spi_slave *spi = flash->spi; 181 182 switch (flash->dual_flash) { 183 case SF_DUAL_STACKED_FLASH: 184 if (*addr >= (flash->size >> 1)) { 185 *addr -= flash->size >> 1; 186 spi->flags |= SPI_XFER_U_PAGE; 187 } else { 188 spi->flags &= ~SPI_XFER_U_PAGE; 189 } 190 break; 191 case SF_DUAL_PARALLEL_FLASH: 192 *addr >>= flash->shift; 193 break; 194 default: 195 debug("SF: Unsupported dual_flash=%d\n", flash->dual_flash); 196 break; 197 } 198 } 199 #endif 200 201 static int spi_flash_sr_ready(struct spi_flash *flash) 202 { 203 u8 sr; 204 int ret; 205 206 ret = read_sr(flash, &sr); 207 if (ret < 0) 208 return ret; 209 210 return !(sr & STATUS_WIP); 211 } 212 213 static int spi_flash_fsr_ready(struct spi_flash *flash) 214 { 215 u8 fsr; 216 int ret; 217 218 ret = read_fsr(flash, &fsr); 219 if (ret < 0) 220 return ret; 221 222 return fsr & STATUS_PEC; 223 } 224 225 static int spi_flash_ready(struct spi_flash *flash) 226 { 227 int sr, fsr; 228 229 sr = spi_flash_sr_ready(flash); 230 if (sr < 0) 231 return sr; 232 233 fsr = 1; 234 if (flash->flags & SNOR_F_USE_FSR) { 235 fsr = spi_flash_fsr_ready(flash); 236 if (fsr < 0) 237 return fsr; 238 } 239 240 return sr && fsr; 241 } 242 243 static int spi_flash_cmd_wait_ready(struct spi_flash *flash, 244 unsigned long timeout) 245 { 246 int timebase, ret; 247 248 timebase = get_timer(0); 249 250 while (get_timer(timebase) < timeout) { 251 ret = spi_flash_ready(flash); 252 if (ret < 0) 253 return ret; 254 if (ret) 255 return 0; 256 } 257 258 printf("SF: Timeout!\n"); 259 260 return -ETIMEDOUT; 261 } 262 263 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, 264 size_t cmd_len, const void *buf, size_t buf_len) 265 { 266 struct spi_slave *spi = flash->spi; 267 unsigned long timeout = SPI_FLASH_PROG_TIMEOUT; 268 int ret; 269 270 if (buf == NULL) 271 timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT; 272 273 ret = spi_claim_bus(spi); 274 if (ret) { 275 debug("SF: unable to claim SPI bus\n"); 276 return ret; 277 } 278 279 ret = spi_flash_cmd_write_enable(flash); 280 if (ret < 0) { 281 debug("SF: enabling write failed\n"); 282 return ret; 283 } 284 285 ret = spi_flash_cmd_write(spi, cmd, cmd_len, buf, buf_len); 286 if (ret < 0) { 287 debug("SF: write cmd failed\n"); 288 return ret; 289 } 290 291 ret = spi_flash_cmd_wait_ready(flash, timeout); 292 if (ret < 0) { 293 debug("SF: write %s timed out\n", 294 timeout == SPI_FLASH_PROG_TIMEOUT ? 295 "program" : "page erase"); 296 return ret; 297 } 298 299 spi_release_bus(spi); 300 301 return ret; 302 } 303 304 int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) 305 { 306 u32 erase_size, erase_addr; 307 u8 cmd[SPI_FLASH_CMD_LEN]; 308 int ret = -1; 309 310 erase_size = flash->erase_size; 311 if (offset % erase_size || len % erase_size) { 312 debug("SF: Erase offset/length not multiple of erase size\n"); 313 return -1; 314 } 315 316 if (flash->flash_is_locked) { 317 if (flash->flash_is_locked(flash, offset, len) > 0) { 318 printf("offset 0x%x is protected and cannot be erased\n", 319 offset); 320 return -EINVAL; 321 } 322 } 323 324 cmd[0] = flash->erase_cmd; 325 while (len) { 326 erase_addr = offset; 327 328 #ifdef CONFIG_SF_DUAL_FLASH 329 if (flash->dual_flash > SF_SINGLE_FLASH) 330 spi_flash_dual(flash, &erase_addr); 331 #endif 332 #ifdef CONFIG_SPI_FLASH_BAR 333 ret = spi_flash_write_bar(flash, erase_addr); 334 if (ret < 0) 335 return ret; 336 #endif 337 spi_flash_addr(erase_addr, cmd); 338 339 debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1], 340 cmd[2], cmd[3], erase_addr); 341 342 ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0); 343 if (ret < 0) { 344 debug("SF: erase failed\n"); 345 break; 346 } 347 348 offset += erase_size; 349 len -= erase_size; 350 } 351 352 return ret; 353 } 354 355 int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, 356 size_t len, const void *buf) 357 { 358 struct spi_slave *spi = flash->spi; 359 unsigned long byte_addr, page_size; 360 u32 write_addr; 361 size_t chunk_len, actual; 362 u8 cmd[SPI_FLASH_CMD_LEN]; 363 int ret = -1; 364 365 page_size = flash->page_size; 366 367 if (flash->flash_is_locked) { 368 if (flash->flash_is_locked(flash, offset, len) > 0) { 369 printf("offset 0x%x is protected and cannot be written\n", 370 offset); 371 return -EINVAL; 372 } 373 } 374 375 cmd[0] = flash->write_cmd; 376 for (actual = 0; actual < len; actual += chunk_len) { 377 write_addr = offset; 378 379 #ifdef CONFIG_SF_DUAL_FLASH 380 if (flash->dual_flash > SF_SINGLE_FLASH) 381 spi_flash_dual(flash, &write_addr); 382 #endif 383 #ifdef CONFIG_SPI_FLASH_BAR 384 ret = spi_flash_write_bar(flash, write_addr); 385 if (ret < 0) 386 return ret; 387 #endif 388 byte_addr = offset % page_size; 389 chunk_len = min(len - actual, (size_t)(page_size - byte_addr)); 390 391 if (spi->max_write_size) 392 chunk_len = min(chunk_len, 393 (size_t)spi->max_write_size); 394 395 spi_flash_addr(write_addr, cmd); 396 397 debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", 398 buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); 399 400 ret = spi_flash_write_common(flash, cmd, sizeof(cmd), 401 buf + actual, chunk_len); 402 if (ret < 0) { 403 debug("SF: write failed\n"); 404 break; 405 } 406 407 offset += chunk_len; 408 } 409 410 return ret; 411 } 412 413 int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, 414 size_t cmd_len, void *data, size_t data_len) 415 { 416 struct spi_slave *spi = flash->spi; 417 int ret; 418 419 ret = spi_claim_bus(spi); 420 if (ret) { 421 debug("SF: unable to claim SPI bus\n"); 422 return ret; 423 } 424 425 ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len); 426 if (ret < 0) { 427 debug("SF: read cmd failed\n"); 428 return ret; 429 } 430 431 spi_release_bus(spi); 432 433 return ret; 434 } 435 436 void __weak spi_flash_copy_mmap(void *data, void *offset, size_t len) 437 { 438 memcpy(data, offset, len); 439 } 440 441 int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, 442 size_t len, void *data) 443 { 444 struct spi_slave *spi = flash->spi; 445 u8 *cmd, cmdsz; 446 u32 remain_len, read_len, read_addr; 447 int bank_sel = 0; 448 int ret = -1; 449 450 /* Handle memory-mapped SPI */ 451 if (flash->memory_map) { 452 ret = spi_claim_bus(spi); 453 if (ret) { 454 debug("SF: unable to claim SPI bus\n"); 455 return ret; 456 } 457 spi_xfer(spi, 0, NULL, NULL, SPI_XFER_MMAP); 458 spi_flash_copy_mmap(data, flash->memory_map + offset, len); 459 spi_xfer(spi, 0, NULL, NULL, SPI_XFER_MMAP_END); 460 spi_release_bus(spi); 461 return 0; 462 } 463 464 cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte; 465 cmd = calloc(1, cmdsz); 466 if (!cmd) { 467 debug("SF: Failed to allocate cmd\n"); 468 return -ENOMEM; 469 } 470 471 cmd[0] = flash->read_cmd; 472 while (len) { 473 read_addr = offset; 474 475 #ifdef CONFIG_SF_DUAL_FLASH 476 if (flash->dual_flash > SF_SINGLE_FLASH) 477 spi_flash_dual(flash, &read_addr); 478 #endif 479 #ifdef CONFIG_SPI_FLASH_BAR 480 ret = spi_flash_write_bar(flash, read_addr); 481 if (ret < 0) 482 return ret; 483 bank_sel = flash->bank_curr; 484 #endif 485 remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) * 486 (bank_sel + 1)) - offset; 487 if (len < remain_len) 488 read_len = len; 489 else 490 read_len = remain_len; 491 492 spi_flash_addr(read_addr, cmd); 493 494 ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len); 495 if (ret < 0) { 496 debug("SF: read failed\n"); 497 break; 498 } 499 500 offset += read_len; 501 len -= read_len; 502 data += read_len; 503 } 504 505 free(cmd); 506 return ret; 507 } 508 509 #ifdef CONFIG_SPI_FLASH_SST 510 static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf) 511 { 512 struct spi_slave *spi = flash->spi; 513 int ret; 514 u8 cmd[4] = { 515 CMD_SST_BP, 516 offset >> 16, 517 offset >> 8, 518 offset, 519 }; 520 521 debug("BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", 522 spi_w8r8(spi, CMD_READ_STATUS), buf, cmd[0], offset); 523 524 ret = spi_flash_cmd_write_enable(flash); 525 if (ret) 526 return ret; 527 528 ret = spi_flash_cmd_write(spi, cmd, sizeof(cmd), buf, 1); 529 if (ret) 530 return ret; 531 532 return spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); 533 } 534 535 int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, 536 const void *buf) 537 { 538 struct spi_slave *spi = flash->spi; 539 size_t actual, cmd_len; 540 int ret; 541 u8 cmd[4]; 542 543 ret = spi_claim_bus(spi); 544 if (ret) { 545 debug("SF: Unable to claim SPI bus\n"); 546 return ret; 547 } 548 549 /* If the data is not word aligned, write out leading single byte */ 550 actual = offset % 2; 551 if (actual) { 552 ret = sst_byte_write(flash, offset, buf); 553 if (ret) 554 goto done; 555 } 556 offset += actual; 557 558 ret = spi_flash_cmd_write_enable(flash); 559 if (ret) 560 goto done; 561 562 cmd_len = 4; 563 cmd[0] = CMD_SST_AAI_WP; 564 cmd[1] = offset >> 16; 565 cmd[2] = offset >> 8; 566 cmd[3] = offset; 567 568 for (; actual < len - 1; actual += 2) { 569 debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", 570 spi_w8r8(spi, CMD_READ_STATUS), buf + actual, 571 cmd[0], offset); 572 573 ret = spi_flash_cmd_write(spi, cmd, cmd_len, 574 buf + actual, 2); 575 if (ret) { 576 debug("SF: sst word program failed\n"); 577 break; 578 } 579 580 ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); 581 if (ret) 582 break; 583 584 cmd_len = 1; 585 offset += 2; 586 } 587 588 if (!ret) 589 ret = spi_flash_cmd_write_disable(flash); 590 591 /* If there is a single trailing byte, write it out */ 592 if (!ret && actual != len) 593 ret = sst_byte_write(flash, offset, buf + actual); 594 595 done: 596 debug("SF: sst: program %s %zu bytes @ 0x%zx\n", 597 ret ? "failure" : "success", len, offset - actual); 598 599 spi_release_bus(spi); 600 return ret; 601 } 602 603 int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len, 604 const void *buf) 605 { 606 struct spi_slave *spi = flash->spi; 607 size_t actual; 608 int ret; 609 610 ret = spi_claim_bus(spi); 611 if (ret) { 612 debug("SF: Unable to claim SPI bus\n"); 613 return ret; 614 } 615 616 for (actual = 0; actual < len; actual++) { 617 ret = sst_byte_write(flash, offset, buf + actual); 618 if (ret) { 619 debug("SF: sst byte program failed\n"); 620 break; 621 } 622 offset++; 623 } 624 625 if (!ret) 626 ret = spi_flash_cmd_write_disable(flash); 627 628 debug("SF: sst: program %s %zu bytes @ 0x%zx\n", 629 ret ? "failure" : "success", len, offset - actual); 630 631 spi_release_bus(spi); 632 return ret; 633 } 634 #endif 635 636 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) 637 static void stm_get_locked_range(struct spi_flash *flash, u8 sr, loff_t *ofs, 638 u32 *len) 639 { 640 u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 641 int shift = ffs(mask) - 1; 642 int pow; 643 644 if (!(sr & mask)) { 645 /* No protection */ 646 *ofs = 0; 647 *len = 0; 648 } else { 649 pow = ((sr & mask) ^ mask) >> shift; 650 *len = flash->size >> pow; 651 *ofs = flash->size - *len; 652 } 653 } 654 655 /* 656 * Return 1 if the entire region is locked, 0 otherwise 657 */ 658 static int stm_is_locked_sr(struct spi_flash *flash, u32 ofs, u32 len, 659 u8 sr) 660 { 661 loff_t lock_offs; 662 u32 lock_len; 663 664 stm_get_locked_range(flash, sr, &lock_offs, &lock_len); 665 666 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs); 667 } 668 669 /* 670 * Check if a region of the flash is (completely) locked. See stm_lock() for 671 * more info. 672 * 673 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and 674 * negative on errors. 675 */ 676 int stm_is_locked(struct spi_flash *flash, u32 ofs, size_t len) 677 { 678 int status; 679 u8 sr; 680 681 status = read_sr(flash, &sr); 682 if (status < 0) 683 return status; 684 685 return stm_is_locked_sr(flash, ofs, len, sr); 686 } 687 688 /* 689 * Lock a region of the flash. Compatible with ST Micro and similar flash. 690 * Supports only the block protection bits BP{0,1,2} in the status register 691 * (SR). Does not support these features found in newer SR bitfields: 692 * - TB: top/bottom protect - only handle TB=0 (top protect) 693 * - SEC: sector/block protect - only handle SEC=0 (block protect) 694 * - CMP: complement protect - only support CMP=0 (range is not complemented) 695 * 696 * Sample table portion for 8MB flash (Winbond w25q64fw): 697 * 698 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion 699 * -------------------------------------------------------------------------- 700 * X | X | 0 | 0 | 0 | NONE | NONE 701 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64 702 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32 703 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16 704 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8 705 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4 706 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2 707 * X | X | 1 | 1 | 1 | 8 MB | ALL 708 * 709 * Returns negative on errors, 0 on success. 710 */ 711 int stm_lock(struct spi_flash *flash, u32 ofs, size_t len) 712 { 713 u8 status_old, status_new; 714 u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 715 u8 shift = ffs(mask) - 1, pow, val; 716 int ret; 717 718 ret = read_sr(flash, &status_old); 719 if (ret < 0) 720 return ret; 721 722 /* SPI NOR always locks to the end */ 723 if (ofs + len != flash->size) { 724 /* Does combined region extend to end? */ 725 if (!stm_is_locked_sr(flash, ofs + len, flash->size - ofs - len, 726 status_old)) 727 return -EINVAL; 728 len = flash->size - ofs; 729 } 730 731 /* 732 * Need smallest pow such that: 733 * 734 * 1 / (2^pow) <= (len / size) 735 * 736 * so (assuming power-of-2 size) we do: 737 * 738 * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len)) 739 */ 740 pow = ilog2(flash->size) - ilog2(len); 741 val = mask - (pow << shift); 742 if (val & ~mask) 743 return -EINVAL; 744 745 /* Don't "lock" with no region! */ 746 if (!(val & mask)) 747 return -EINVAL; 748 749 status_new = (status_old & ~mask) | val; 750 751 /* Only modify protection if it will not unlock other areas */ 752 if ((status_new & mask) <= (status_old & mask)) 753 return -EINVAL; 754 755 write_sr(flash, status_new); 756 757 return 0; 758 } 759 760 /* 761 * Unlock a region of the flash. See stm_lock() for more info 762 * 763 * Returns negative on errors, 0 on success. 764 */ 765 int stm_unlock(struct spi_flash *flash, u32 ofs, size_t len) 766 { 767 uint8_t status_old, status_new; 768 u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 769 u8 shift = ffs(mask) - 1, pow, val; 770 int ret; 771 772 ret = read_sr(flash, &status_old); 773 if (ret < 0) 774 return ret; 775 776 /* Cannot unlock; would unlock larger region than requested */ 777 if (stm_is_locked_sr(flash, ofs - flash->erase_size, flash->erase_size, 778 status_old)) 779 return -EINVAL; 780 /* 781 * Need largest pow such that: 782 * 783 * 1 / (2^pow) >= (len / size) 784 * 785 * so (assuming power-of-2 size) we do: 786 * 787 * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len)) 788 */ 789 pow = ilog2(flash->size) - order_base_2(flash->size - (ofs + len)); 790 if (ofs + len == flash->size) { 791 val = 0; /* fully unlocked */ 792 } else { 793 val = mask - (pow << shift); 794 /* Some power-of-two sizes are not supported */ 795 if (val & ~mask) 796 return -EINVAL; 797 } 798 799 status_new = (status_old & ~mask) | val; 800 801 /* Only modify protection if it will not lock other areas */ 802 if ((status_new & mask) >= (status_old & mask)) 803 return -EINVAL; 804 805 write_sr(flash, status_new); 806 807 return 0; 808 } 809 #endif 810 811 812 #ifdef CONFIG_SPI_FLASH_MACRONIX 813 static int spi_flash_set_qeb_mxic(struct spi_flash *flash) 814 { 815 u8 qeb_status; 816 int ret; 817 818 ret = read_sr(flash, &qeb_status); 819 if (ret < 0) 820 return ret; 821 822 if (qeb_status & STATUS_QEB_MXIC) { 823 debug("SF: mxic: QEB is already set\n"); 824 } else { 825 ret = write_sr(flash, STATUS_QEB_MXIC); 826 if (ret < 0) 827 return ret; 828 } 829 830 return ret; 831 } 832 #endif 833 834 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 835 static int spi_flash_set_qeb_winspan(struct spi_flash *flash) 836 { 837 u8 qeb_status; 838 int ret; 839 840 ret = read_cr(flash, &qeb_status); 841 if (ret < 0) 842 return ret; 843 844 if (qeb_status & STATUS_QEB_WINSPAN) { 845 debug("SF: winspan: QEB is already set\n"); 846 } else { 847 ret = write_cr(flash, STATUS_QEB_WINSPAN); 848 if (ret < 0) 849 return ret; 850 } 851 852 return ret; 853 } 854 #endif 855 856 static int spi_flash_set_qeb(struct spi_flash *flash, u8 idcode0) 857 { 858 switch (idcode0) { 859 #ifdef CONFIG_SPI_FLASH_MACRONIX 860 case SPI_FLASH_CFI_MFR_MACRONIX: 861 return spi_flash_set_qeb_mxic(flash); 862 #endif 863 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 864 case SPI_FLASH_CFI_MFR_SPANSION: 865 case SPI_FLASH_CFI_MFR_WINBOND: 866 return spi_flash_set_qeb_winspan(flash); 867 #endif 868 #ifdef CONFIG_SPI_FLASH_STMICRO 869 case SPI_FLASH_CFI_MFR_STMICRO: 870 debug("SF: QEB is volatile for %02x flash\n", idcode0); 871 return 0; 872 #endif 873 default: 874 printf("SF: Need set QEB func for %02x flash\n", idcode0); 875 return -1; 876 } 877 } 878 879 #if CONFIG_IS_ENABLED(OF_CONTROL) 880 int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash) 881 { 882 fdt_addr_t addr; 883 fdt_size_t size; 884 int node; 885 886 /* If there is no node, do nothing */ 887 node = fdtdec_next_compatible(blob, 0, COMPAT_GENERIC_SPI_FLASH); 888 if (node < 0) 889 return 0; 890 891 addr = fdtdec_get_addr_size(blob, node, "memory-map", &size); 892 if (addr == FDT_ADDR_T_NONE) { 893 debug("%s: Cannot decode address\n", __func__); 894 return 0; 895 } 896 897 if (flash->size != size) { 898 debug("%s: Memory map must cover entire device\n", __func__); 899 return -1; 900 } 901 flash->memory_map = map_sysmem(addr, size); 902 903 return 0; 904 } 905 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */ 906 907 int spi_flash_scan(struct spi_flash *flash) 908 { 909 struct spi_slave *spi = flash->spi; 910 const struct spi_flash_params *params; 911 u16 jedec, ext_jedec; 912 u8 idcode[5]; 913 u8 cmd; 914 int ret; 915 916 /* Read the ID codes */ 917 ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode)); 918 if (ret) { 919 printf("SF: Failed to get idcodes\n"); 920 return -EINVAL; 921 } 922 923 #ifdef DEBUG 924 printf("SF: Got idcodes\n"); 925 print_buffer(0, idcode, 1, sizeof(idcode), 0); 926 #endif 927 928 jedec = idcode[1] << 8 | idcode[2]; 929 ext_jedec = idcode[3] << 8 | idcode[4]; 930 931 /* Validate params from spi_flash_params table */ 932 params = spi_flash_params_table; 933 for (; params->name != NULL; params++) { 934 if ((params->jedec >> 16) == idcode[0]) { 935 if ((params->jedec & 0xFFFF) == jedec) { 936 if (params->ext_jedec == 0) 937 break; 938 else if (params->ext_jedec == ext_jedec) 939 break; 940 } 941 } 942 } 943 944 if (!params->name) { 945 printf("SF: Unsupported flash IDs: "); 946 printf("manuf %02x, jedec %04x, ext_jedec %04x\n", 947 idcode[0], jedec, ext_jedec); 948 return -EPROTONOSUPPORT; 949 } 950 951 /* Flash powers up read-only, so clear BP# bits */ 952 if (idcode[0] == SPI_FLASH_CFI_MFR_ATMEL || 953 idcode[0] == SPI_FLASH_CFI_MFR_MACRONIX || 954 idcode[0] == SPI_FLASH_CFI_MFR_SST) 955 write_sr(flash, 0); 956 957 /* Assign spi data */ 958 flash->name = params->name; 959 flash->memory_map = spi->memory_map; 960 flash->dual_flash = spi->option; 961 962 /* Assign spi flash flags */ 963 if (params->flags & SST_WR) 964 flash->flags |= SNOR_F_SST_WR; 965 966 /* Assign spi_flash ops */ 967 #ifndef CONFIG_DM_SPI_FLASH 968 flash->write = spi_flash_cmd_write_ops; 969 #if defined(CONFIG_SPI_FLASH_SST) 970 if (flash->flags & SNOR_F_SST_WR) { 971 if (spi->mode & SPI_TX_BP) 972 flash->write = sst_write_bp; 973 else 974 flash->write = sst_write_wp; 975 } 976 #endif 977 flash->erase = spi_flash_cmd_erase_ops; 978 flash->read = spi_flash_cmd_read_ops; 979 #endif 980 981 /* lock hooks are flash specific - assign them based on idcode0 */ 982 switch (idcode[0]) { 983 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) 984 case SPI_FLASH_CFI_MFR_STMICRO: 985 case SPI_FLASH_CFI_MFR_SST: 986 flash->flash_lock = stm_lock; 987 flash->flash_unlock = stm_unlock; 988 flash->flash_is_locked = stm_is_locked; 989 #endif 990 break; 991 default: 992 debug("SF: Lock ops not supported for %02x flash\n", idcode[0]); 993 } 994 995 /* Compute the flash size */ 996 flash->shift = (flash->dual_flash & SF_DUAL_PARALLEL_FLASH) ? 1 : 0; 997 /* 998 * The Spansion S25FL032P and S25FL064P have 256b pages, yet use the 999 * 0x4d00 Extended JEDEC code. The rest of the Spansion flashes with 1000 * the 0x4d00 Extended JEDEC code have 512b pages. All of the others 1001 * have 256b pages. 1002 */ 1003 if (ext_jedec == 0x4d00) { 1004 if ((jedec == 0x0215) || (jedec == 0x216)) 1005 flash->page_size = 256; 1006 else 1007 flash->page_size = 512; 1008 } else { 1009 flash->page_size = 256; 1010 } 1011 flash->page_size <<= flash->shift; 1012 flash->sector_size = params->sector_size << flash->shift; 1013 flash->size = flash->sector_size * params->nr_sectors << flash->shift; 1014 #ifdef CONFIG_SF_DUAL_FLASH 1015 if (flash->dual_flash & SF_DUAL_STACKED_FLASH) 1016 flash->size <<= 1; 1017 #endif 1018 1019 /* Compute erase sector and command */ 1020 if (params->flags & SECT_4K) { 1021 flash->erase_cmd = CMD_ERASE_4K; 1022 flash->erase_size = 4096 << flash->shift; 1023 } else if (params->flags & SECT_32K) { 1024 flash->erase_cmd = CMD_ERASE_32K; 1025 flash->erase_size = 32768 << flash->shift; 1026 } else { 1027 flash->erase_cmd = CMD_ERASE_64K; 1028 flash->erase_size = flash->sector_size; 1029 } 1030 1031 /* Now erase size becomes valid sector size */ 1032 flash->sector_size = flash->erase_size; 1033 1034 /* Look for the fastest read cmd */ 1035 cmd = fls(params->e_rd_cmd & spi->op_mode_rx); 1036 if (cmd) { 1037 cmd = spi_read_cmds_array[cmd - 1]; 1038 flash->read_cmd = cmd; 1039 } else { 1040 /* Go for default supported read cmd */ 1041 flash->read_cmd = CMD_READ_ARRAY_FAST; 1042 } 1043 1044 /* Not require to look for fastest only two write cmds yet */ 1045 if (params->flags & WR_QPP && spi->mode & SPI_TX_QPP) 1046 flash->write_cmd = CMD_QUAD_PAGE_PROGRAM; 1047 else 1048 /* Go for default supported write cmd */ 1049 flash->write_cmd = CMD_PAGE_PROGRAM; 1050 1051 /* Set the quad enable bit - only for quad commands */ 1052 if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) || 1053 (flash->read_cmd == CMD_READ_QUAD_IO_FAST) || 1054 (flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) { 1055 ret = spi_flash_set_qeb(flash, idcode[0]); 1056 if (ret) { 1057 debug("SF: Fail to set QEB for %02x\n", idcode[0]); 1058 return -EINVAL; 1059 } 1060 } 1061 1062 /* Read dummy_byte: dummy byte is determined based on the 1063 * dummy cycles of a particular command. 1064 * Fast commands - dummy_byte = dummy_cycles/8 1065 * I/O commands- dummy_byte = (dummy_cycles * no.of lines)/8 1066 * For I/O commands except cmd[0] everything goes on no.of lines 1067 * based on particular command but incase of fast commands except 1068 * data all go on single line irrespective of command. 1069 */ 1070 switch (flash->read_cmd) { 1071 case CMD_READ_QUAD_IO_FAST: 1072 flash->dummy_byte = 2; 1073 break; 1074 case CMD_READ_ARRAY_SLOW: 1075 flash->dummy_byte = 0; 1076 break; 1077 default: 1078 flash->dummy_byte = 1; 1079 } 1080 1081 #ifdef CONFIG_SPI_FLASH_STMICRO 1082 if (params->flags & E_FSR) 1083 flash->flags |= SNOR_F_USE_FSR; 1084 #endif 1085 1086 /* Configure the BAR - discover bank cmds and read current bank */ 1087 #ifdef CONFIG_SPI_FLASH_BAR 1088 ret = spi_flash_read_bar(flash, idcode[0]); 1089 if (ret < 0) 1090 return ret; 1091 #endif 1092 1093 #if CONFIG_IS_ENABLED(OF_CONTROL) 1094 ret = spi_flash_decode_fdt(gd->fdt_blob, flash); 1095 if (ret) { 1096 debug("SF: FDT decode error\n"); 1097 return -EINVAL; 1098 } 1099 #endif 1100 1101 #ifndef CONFIG_SPL_BUILD 1102 printf("SF: Detected %s with page size ", flash->name); 1103 print_size(flash->page_size, ", erase size "); 1104 print_size(flash->erase_size, ", total "); 1105 print_size(flash->size, ""); 1106 if (flash->memory_map) 1107 printf(", mapped at %p", flash->memory_map); 1108 puts("\n"); 1109 #endif 1110 1111 #ifndef CONFIG_SPI_FLASH_BAR 1112 if (((flash->dual_flash == SF_SINGLE_FLASH) && 1113 (flash->size > SPI_FLASH_16MB_BOUN)) || 1114 ((flash->dual_flash > SF_SINGLE_FLASH) && 1115 (flash->size > SPI_FLASH_16MB_BOUN << 1))) { 1116 puts("SF: Warning - Only lower 16MiB accessible,"); 1117 puts(" Full access #define CONFIG_SPI_FLASH_BAR\n"); 1118 } 1119 #endif 1120 1121 return ret; 1122 } 1123