1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with 4 * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c 5 * 6 * Copyright (C) 2005, Intec Automation Inc. 7 * Copyright (C) 2014, Freescale Semiconductor, Inc. 8 * 9 * Synced from Linux v4.19 10 */ 11 12 #include <common.h> 13 #include <linux/err.h> 14 #include <linux/errno.h> 15 #include <linux/log2.h> 16 #include <linux/math64.h> 17 #include <linux/sizes.h> 18 19 #include <linux/mtd/mtd.h> 20 #include <linux/mtd/spi-nor.h> 21 #include <spi-mem.h> 22 #include <spi.h> 23 24 #include "sf_internal.h" 25 26 /* Define max times to check status register before we give up. */ 27 28 /* 29 * For everything but full-chip erase; probably could be much smaller, but kept 30 * around for safety for now 31 */ 32 33 #define HZ CONFIG_SYS_HZ 34 35 #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ) 36 37 static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op 38 *op, void *buf) 39 { 40 if (op->data.dir == SPI_MEM_DATA_IN) 41 op->data.buf.in = buf; 42 else 43 op->data.buf.out = buf; 44 return spi_mem_exec_op(nor->spi, op); 45 } 46 47 static int spi_nor_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len) 48 { 49 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(code, 1), 50 SPI_MEM_OP_NO_ADDR, 51 SPI_MEM_OP_NO_DUMMY, 52 SPI_MEM_OP_DATA_IN(len, NULL, 1)); 53 int ret; 54 55 ret = spi_nor_read_write_reg(nor, &op, val); 56 if (ret < 0) 57 dev_dbg(&flash->spimem->spi->dev, "error %d reading %x\n", ret, 58 code); 59 60 return ret; 61 } 62 63 static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len) 64 { 65 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 1), 66 SPI_MEM_OP_NO_ADDR, 67 SPI_MEM_OP_NO_DUMMY, 68 SPI_MEM_OP_DATA_OUT(len, NULL, 1)); 69 70 return spi_nor_read_write_reg(nor, &op, buf); 71 } 72 73 static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len, 74 u_char *buf) 75 { 76 struct spi_mem_op op = 77 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 1), 78 SPI_MEM_OP_ADDR(nor->addr_width, from, 1), 79 SPI_MEM_OP_DUMMY(nor->read_dummy, 1), 80 SPI_MEM_OP_DATA_IN(len, buf, 1)); 81 size_t remaining = len; 82 int ret; 83 84 /* get transfer protocols. */ 85 op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->read_proto); 86 op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->read_proto); 87 op.dummy.buswidth = op.addr.buswidth; 88 op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto); 89 90 /* convert the dummy cycles to the number of bytes */ 91 op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8; 92 93 while (remaining) { 94 op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX; 95 ret = spi_mem_adjust_op_size(nor->spi, &op); 96 if (ret) 97 return ret; 98 99 ret = spi_mem_exec_op(nor->spi, &op); 100 if (ret) 101 return ret; 102 103 op.addr.val += op.data.nbytes; 104 remaining -= op.data.nbytes; 105 op.data.buf.in += op.data.nbytes; 106 } 107 108 return len; 109 } 110 111 static ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len, 112 const u_char *buf) 113 { 114 struct spi_mem_op op = 115 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 1), 116 SPI_MEM_OP_ADDR(nor->addr_width, to, 1), 117 SPI_MEM_OP_NO_DUMMY, 118 SPI_MEM_OP_DATA_OUT(len, buf, 1)); 119 int ret; 120 121 /* get transfer protocols. */ 122 op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->write_proto); 123 op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->write_proto); 124 op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto); 125 126 if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second) 127 op.addr.nbytes = 0; 128 129 ret = spi_mem_adjust_op_size(nor->spi, &op); 130 if (ret) 131 return ret; 132 op.data.nbytes = len < op.data.nbytes ? len : op.data.nbytes; 133 134 ret = spi_mem_exec_op(nor->spi, &op); 135 if (ret) 136 return ret; 137 138 return op.data.nbytes; 139 } 140 141 /* 142 * Read the status register, returning its value in the location 143 * Return the status register value. 144 * Returns negative if error occurred. 145 */ 146 static int read_sr(struct spi_nor *nor) 147 { 148 int ret; 149 u8 val; 150 151 ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1); 152 if (ret < 0) { 153 pr_debug("error %d reading SR\n", (int)ret); 154 return ret; 155 } 156 157 return val; 158 } 159 160 /* 161 * Read the flag status register, returning its value in the location 162 * Return the status register value. 163 * Returns negative if error occurred. 164 */ 165 static int read_fsr(struct spi_nor *nor) 166 { 167 int ret; 168 u8 val; 169 170 ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1); 171 if (ret < 0) { 172 pr_debug("error %d reading FSR\n", ret); 173 return ret; 174 } 175 176 return val; 177 } 178 179 /* 180 * Read configuration register, returning its value in the 181 * location. Return the configuration register value. 182 * Returns negative if error occurred. 183 */ 184 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 185 static int read_cr(struct spi_nor *nor) 186 { 187 int ret; 188 u8 val; 189 190 ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1); 191 if (ret < 0) { 192 dev_dbg(nor->dev, "error %d reading CR\n", ret); 193 return ret; 194 } 195 196 return val; 197 } 198 #endif 199 200 /* 201 * Write status register 1 byte 202 * Returns negative if error occurred. 203 */ 204 static int write_sr(struct spi_nor *nor, u8 val) 205 { 206 nor->cmd_buf[0] = val; 207 return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1); 208 } 209 210 /* 211 * Set write enable latch with Write Enable command. 212 * Returns negative if error occurred. 213 */ 214 static int write_enable(struct spi_nor *nor) 215 { 216 return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0); 217 } 218 219 /* 220 * Send write disable instruction to the chip. 221 */ 222 static int write_disable(struct spi_nor *nor) 223 { 224 return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0); 225 } 226 227 static struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd) 228 { 229 return mtd->priv; 230 } 231 232 #ifndef CONFIG_SPI_FLASH_BAR 233 static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size) 234 { 235 size_t i; 236 237 for (i = 0; i < size; i++) 238 if (table[i][0] == opcode) 239 return table[i][1]; 240 241 /* No conversion found, keep input op code. */ 242 return opcode; 243 } 244 245 static u8 spi_nor_convert_3to4_read(u8 opcode) 246 { 247 static const u8 spi_nor_3to4_read[][2] = { 248 { SPINOR_OP_READ, SPINOR_OP_READ_4B }, 249 { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B }, 250 { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B }, 251 { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B }, 252 { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B }, 253 { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B }, 254 255 { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B }, 256 { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B }, 257 { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B }, 258 }; 259 260 return spi_nor_convert_opcode(opcode, spi_nor_3to4_read, 261 ARRAY_SIZE(spi_nor_3to4_read)); 262 } 263 264 static u8 spi_nor_convert_3to4_program(u8 opcode) 265 { 266 static const u8 spi_nor_3to4_program[][2] = { 267 { SPINOR_OP_PP, SPINOR_OP_PP_4B }, 268 { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B }, 269 { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B }, 270 }; 271 272 return spi_nor_convert_opcode(opcode, spi_nor_3to4_program, 273 ARRAY_SIZE(spi_nor_3to4_program)); 274 } 275 276 static u8 spi_nor_convert_3to4_erase(u8 opcode) 277 { 278 static const u8 spi_nor_3to4_erase[][2] = { 279 { SPINOR_OP_BE_4K, SPINOR_OP_BE_4K_4B }, 280 { SPINOR_OP_BE_32K, SPINOR_OP_BE_32K_4B }, 281 { SPINOR_OP_SE, SPINOR_OP_SE_4B }, 282 }; 283 284 return spi_nor_convert_opcode(opcode, spi_nor_3to4_erase, 285 ARRAY_SIZE(spi_nor_3to4_erase)); 286 } 287 288 static void spi_nor_set_4byte_opcodes(struct spi_nor *nor, 289 const struct flash_info *info) 290 { 291 /* Do some manufacturer fixups first */ 292 switch (JEDEC_MFR(info)) { 293 case SNOR_MFR_SPANSION: 294 /* No small sector erase for 4-byte command set */ 295 nor->erase_opcode = SPINOR_OP_SE; 296 nor->mtd.erasesize = info->sector_size; 297 break; 298 299 default: 300 break; 301 } 302 303 nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode); 304 nor->program_opcode = spi_nor_convert_3to4_program(nor->program_opcode); 305 nor->erase_opcode = spi_nor_convert_3to4_erase(nor->erase_opcode); 306 } 307 #endif /* !CONFIG_SPI_FLASH_BAR */ 308 309 /* Enable/disable 4-byte addressing mode. */ 310 static int set_4byte(struct spi_nor *nor, const struct flash_info *info, 311 int enable) 312 { 313 int status; 314 bool need_wren = false; 315 u8 cmd; 316 317 switch (JEDEC_MFR(info)) { 318 case SNOR_MFR_ST: 319 case SNOR_MFR_MICRON: 320 /* Some Micron need WREN command; all will accept it */ 321 need_wren = true; 322 case SNOR_MFR_MACRONIX: 323 case SNOR_MFR_WINBOND: 324 if (need_wren) 325 write_enable(nor); 326 327 cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B; 328 status = nor->write_reg(nor, cmd, NULL, 0); 329 if (need_wren) 330 write_disable(nor); 331 332 if (!status && !enable && 333 JEDEC_MFR(info) == SNOR_MFR_WINBOND) { 334 /* 335 * On Winbond W25Q256FV, leaving 4byte mode causes 336 * the Extended Address Register to be set to 1, so all 337 * 3-byte-address reads come from the second 16M. 338 * We must clear the register to enable normal behavior. 339 */ 340 write_enable(nor); 341 nor->cmd_buf[0] = 0; 342 nor->write_reg(nor, SPINOR_OP_WREAR, nor->cmd_buf, 1); 343 write_disable(nor); 344 } 345 346 return status; 347 default: 348 /* Spansion style */ 349 nor->cmd_buf[0] = enable << 7; 350 return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1); 351 } 352 } 353 354 static int spi_nor_sr_ready(struct spi_nor *nor) 355 { 356 int sr = read_sr(nor); 357 358 if (sr < 0) 359 return sr; 360 361 if (nor->flags & SNOR_F_USE_CLSR && sr & (SR_E_ERR | SR_P_ERR)) { 362 if (sr & SR_E_ERR) 363 dev_dbg(nor->dev, "Erase Error occurred\n"); 364 else 365 dev_dbg(nor->dev, "Programming Error occurred\n"); 366 367 nor->write_reg(nor, SPINOR_OP_CLSR, NULL, 0); 368 return -EIO; 369 } 370 371 return !(sr & SR_WIP); 372 } 373 374 static int spi_nor_fsr_ready(struct spi_nor *nor) 375 { 376 int fsr = read_fsr(nor); 377 378 if (fsr < 0) 379 return fsr; 380 381 if (fsr & (FSR_E_ERR | FSR_P_ERR)) { 382 if (fsr & FSR_E_ERR) 383 dev_dbg(nor->dev, "Erase operation failed.\n"); 384 else 385 dev_dbg(nor->dev, "Program operation failed.\n"); 386 387 if (fsr & FSR_PT_ERR) 388 dev_dbg(nor->dev, 389 "Attempted to modify a protected sector.\n"); 390 391 nor->write_reg(nor, SPINOR_OP_CLFSR, NULL, 0); 392 return -EIO; 393 } 394 395 return fsr & FSR_READY; 396 } 397 398 static int spi_nor_ready(struct spi_nor *nor) 399 { 400 int sr, fsr; 401 402 sr = spi_nor_sr_ready(nor); 403 if (sr < 0) 404 return sr; 405 fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1; 406 if (fsr < 0) 407 return fsr; 408 return sr && fsr; 409 } 410 411 /* 412 * Service routine to read status register until ready, or timeout occurs. 413 * Returns non-zero if error. 414 */ 415 static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor, 416 unsigned long timeout) 417 { 418 unsigned long timebase; 419 int ret; 420 421 timebase = get_timer(0); 422 423 while (get_timer(timebase) < timeout) { 424 ret = spi_nor_ready(nor); 425 if (ret < 0) 426 return ret; 427 if (ret) 428 return 0; 429 } 430 431 dev_err(nor->dev, "flash operation timed out\n"); 432 433 return -ETIMEDOUT; 434 } 435 436 static int spi_nor_wait_till_ready(struct spi_nor *nor) 437 { 438 return spi_nor_wait_till_ready_with_timeout(nor, 439 DEFAULT_READY_WAIT_JIFFIES); 440 } 441 442 #ifdef CONFIG_SPI_FLASH_BAR 443 /* 444 * This "clean_bar" is necessary in a situation when one was accessing 445 * spi flash memory > 16 MiB by using Bank Address Register's BA24 bit. 446 * 447 * After it the BA24 bit shall be cleared to allow access to correct 448 * memory region after SW reset (by calling "reset" command). 449 * 450 * Otherwise, the BA24 bit may be left set and then after reset, the 451 * ROM would read/write/erase SPL from 16 MiB * bank_sel address. 452 */ 453 static int clean_bar(struct spi_nor *nor) 454 { 455 u8 cmd, bank_sel = 0; 456 457 if (nor->bank_curr == 0) 458 return 0; 459 cmd = nor->bank_write_cmd; 460 nor->bank_curr = 0; 461 write_enable(nor); 462 463 return nor->write_reg(nor, cmd, &bank_sel, 1); 464 } 465 466 static int write_bar(struct spi_nor *nor, u32 offset) 467 { 468 u8 cmd, bank_sel; 469 int ret; 470 471 bank_sel = offset / SZ_16M; 472 if (bank_sel == nor->bank_curr) 473 goto bar_end; 474 475 cmd = nor->bank_write_cmd; 476 write_enable(nor); 477 ret = nor->write_reg(nor, cmd, &bank_sel, 1); 478 if (ret < 0) { 479 debug("SF: fail to write bank register\n"); 480 return ret; 481 } 482 483 bar_end: 484 nor->bank_curr = bank_sel; 485 return nor->bank_curr; 486 } 487 488 static int read_bar(struct spi_nor *nor, const struct flash_info *info) 489 { 490 u8 curr_bank = 0; 491 int ret; 492 493 switch (JEDEC_MFR(info)) { 494 case SNOR_MFR_SPANSION: 495 nor->bank_read_cmd = SPINOR_OP_BRRD; 496 nor->bank_write_cmd = SPINOR_OP_BRWR; 497 break; 498 default: 499 nor->bank_read_cmd = SPINOR_OP_RDEAR; 500 nor->bank_write_cmd = SPINOR_OP_WREAR; 501 } 502 503 ret = nor->read_reg(nor, nor->bank_read_cmd, 504 &curr_bank, 1); 505 if (ret) { 506 debug("SF: fail to read bank addr register\n"); 507 return ret; 508 } 509 nor->bank_curr = curr_bank; 510 511 return 0; 512 } 513 #endif 514 515 /* 516 * Initiate the erasure of a single sector 517 */ 518 static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr) 519 { 520 struct spi_mem_op op = 521 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->erase_opcode, 1), 522 SPI_MEM_OP_ADDR(nor->addr_width, addr, 1), 523 SPI_MEM_OP_NO_DUMMY, 524 SPI_MEM_OP_NO_DATA); 525 526 if (nor->erase) 527 return nor->erase(nor, addr); 528 529 /* 530 * Default implementation, if driver doesn't have a specialized HW 531 * control 532 */ 533 return spi_mem_exec_op(nor->spi, &op); 534 } 535 536 /* 537 * Erase an address range on the nor chip. The address range may extend 538 * one or more erase sectors. Return an error is there is a problem erasing. 539 */ 540 static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) 541 { 542 struct spi_nor *nor = mtd_to_spi_nor(mtd); 543 u32 addr, len, rem; 544 int ret; 545 546 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr, 547 (long long)instr->len); 548 549 div_u64_rem(instr->len, mtd->erasesize, &rem); 550 if (rem) 551 return -EINVAL; 552 553 addr = instr->addr; 554 len = instr->len; 555 556 while (len) { 557 #ifdef CONFIG_SPI_FLASH_BAR 558 ret = write_bar(nor, addr); 559 if (ret < 0) 560 return ret; 561 #endif 562 write_enable(nor); 563 564 ret = spi_nor_erase_sector(nor, addr); 565 if (ret) 566 goto erase_err; 567 568 addr += mtd->erasesize; 569 len -= mtd->erasesize; 570 571 ret = spi_nor_wait_till_ready(nor); 572 if (ret) 573 goto erase_err; 574 } 575 576 erase_err: 577 #ifdef CONFIG_SPI_FLASH_BAR 578 ret = clean_bar(nor); 579 #endif 580 write_disable(nor); 581 582 return ret; 583 } 584 585 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) 586 /* Write status register and ensure bits in mask match written values */ 587 static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask) 588 { 589 int ret; 590 591 write_enable(nor); 592 ret = write_sr(nor, status_new); 593 if (ret) 594 return ret; 595 596 ret = spi_nor_wait_till_ready(nor); 597 if (ret) 598 return ret; 599 600 ret = read_sr(nor); 601 if (ret < 0) 602 return ret; 603 604 return ((ret & mask) != (status_new & mask)) ? -EIO : 0; 605 } 606 607 static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs, 608 uint64_t *len) 609 { 610 struct mtd_info *mtd = &nor->mtd; 611 u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 612 int shift = ffs(mask) - 1; 613 int pow; 614 615 if (!(sr & mask)) { 616 /* No protection */ 617 *ofs = 0; 618 *len = 0; 619 } else { 620 pow = ((sr & mask) ^ mask) >> shift; 621 *len = mtd->size >> pow; 622 if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB) 623 *ofs = 0; 624 else 625 *ofs = mtd->size - *len; 626 } 627 } 628 629 /* 630 * Return 1 if the entire region is locked (if @locked is true) or unlocked (if 631 * @locked is false); 0 otherwise 632 */ 633 static int stm_check_lock_status_sr(struct spi_nor *nor, loff_t ofs, u64 len, 634 u8 sr, bool locked) 635 { 636 loff_t lock_offs; 637 uint64_t lock_len; 638 639 if (!len) 640 return 1; 641 642 stm_get_locked_range(nor, sr, &lock_offs, &lock_len); 643 644 if (locked) 645 /* Requested range is a sub-range of locked range */ 646 return (ofs + len <= lock_offs + lock_len) && (ofs >= lock_offs); 647 else 648 /* Requested range does not overlap with locked range */ 649 return (ofs >= lock_offs + lock_len) || (ofs + len <= lock_offs); 650 } 651 652 static int stm_is_locked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, 653 u8 sr) 654 { 655 return stm_check_lock_status_sr(nor, ofs, len, sr, true); 656 } 657 658 static int stm_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, 659 u8 sr) 660 { 661 return stm_check_lock_status_sr(nor, ofs, len, sr, false); 662 } 663 664 /* 665 * Lock a region of the flash. Compatible with ST Micro and similar flash. 666 * Supports the block protection bits BP{0,1,2} in the status register 667 * (SR). Does not support these features found in newer SR bitfields: 668 * - SEC: sector/block protect - only handle SEC=0 (block protect) 669 * - CMP: complement protect - only support CMP=0 (range is not complemented) 670 * 671 * Support for the following is provided conditionally for some flash: 672 * - TB: top/bottom protect 673 * 674 * Sample table portion for 8MB flash (Winbond w25q64fw): 675 * 676 * SEC | TB | BP2 | BP1 | BP0 | Prot Length | Protected Portion 677 * -------------------------------------------------------------------------- 678 * X | X | 0 | 0 | 0 | NONE | NONE 679 * 0 | 0 | 0 | 0 | 1 | 128 KB | Upper 1/64 680 * 0 | 0 | 0 | 1 | 0 | 256 KB | Upper 1/32 681 * 0 | 0 | 0 | 1 | 1 | 512 KB | Upper 1/16 682 * 0 | 0 | 1 | 0 | 0 | 1 MB | Upper 1/8 683 * 0 | 0 | 1 | 0 | 1 | 2 MB | Upper 1/4 684 * 0 | 0 | 1 | 1 | 0 | 4 MB | Upper 1/2 685 * X | X | 1 | 1 | 1 | 8 MB | ALL 686 * ------|-------|-------|-------|-------|---------------|------------------- 687 * 0 | 1 | 0 | 0 | 1 | 128 KB | Lower 1/64 688 * 0 | 1 | 0 | 1 | 0 | 256 KB | Lower 1/32 689 * 0 | 1 | 0 | 1 | 1 | 512 KB | Lower 1/16 690 * 0 | 1 | 1 | 0 | 0 | 1 MB | Lower 1/8 691 * 0 | 1 | 1 | 0 | 1 | 2 MB | Lower 1/4 692 * 0 | 1 | 1 | 1 | 0 | 4 MB | Lower 1/2 693 * 694 * Returns negative on errors, 0 on success. 695 */ 696 static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) 697 { 698 struct mtd_info *mtd = &nor->mtd; 699 int status_old, status_new; 700 u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 701 u8 shift = ffs(mask) - 1, pow, val; 702 loff_t lock_len; 703 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB; 704 bool use_top; 705 706 status_old = read_sr(nor); 707 if (status_old < 0) 708 return status_old; 709 710 /* If nothing in our range is unlocked, we don't need to do anything */ 711 if (stm_is_locked_sr(nor, ofs, len, status_old)) 712 return 0; 713 714 /* If anything below us is unlocked, we can't use 'bottom' protection */ 715 if (!stm_is_locked_sr(nor, 0, ofs, status_old)) 716 can_be_bottom = false; 717 718 /* If anything above us is unlocked, we can't use 'top' protection */ 719 if (!stm_is_locked_sr(nor, ofs + len, mtd->size - (ofs + len), 720 status_old)) 721 can_be_top = false; 722 723 if (!can_be_bottom && !can_be_top) 724 return -EINVAL; 725 726 /* Prefer top, if both are valid */ 727 use_top = can_be_top; 728 729 /* lock_len: length of region that should end up locked */ 730 if (use_top) 731 lock_len = mtd->size - ofs; 732 else 733 lock_len = ofs + len; 734 735 /* 736 * Need smallest pow such that: 737 * 738 * 1 / (2^pow) <= (len / size) 739 * 740 * so (assuming power-of-2 size) we do: 741 * 742 * pow = ceil(log2(size / len)) = log2(size) - floor(log2(len)) 743 */ 744 pow = ilog2(mtd->size) - ilog2(lock_len); 745 val = mask - (pow << shift); 746 if (val & ~mask) 747 return -EINVAL; 748 /* Don't "lock" with no region! */ 749 if (!(val & mask)) 750 return -EINVAL; 751 752 status_new = (status_old & ~mask & ~SR_TB) | val; 753 754 /* Disallow further writes if WP pin is asserted */ 755 status_new |= SR_SRWD; 756 757 if (!use_top) 758 status_new |= SR_TB; 759 760 /* Don't bother if they're the same */ 761 if (status_new == status_old) 762 return 0; 763 764 /* Only modify protection if it will not unlock other areas */ 765 if ((status_new & mask) < (status_old & mask)) 766 return -EINVAL; 767 768 return write_sr_and_check(nor, status_new, mask); 769 } 770 771 /* 772 * Unlock a region of the flash. See stm_lock() for more info 773 * 774 * Returns negative on errors, 0 on success. 775 */ 776 static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) 777 { 778 struct mtd_info *mtd = &nor->mtd; 779 int status_old, status_new; 780 u8 mask = SR_BP2 | SR_BP1 | SR_BP0; 781 u8 shift = ffs(mask) - 1, pow, val; 782 loff_t lock_len; 783 bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB; 784 bool use_top; 785 786 status_old = read_sr(nor); 787 if (status_old < 0) 788 return status_old; 789 790 /* If nothing in our range is locked, we don't need to do anything */ 791 if (stm_is_unlocked_sr(nor, ofs, len, status_old)) 792 return 0; 793 794 /* If anything below us is locked, we can't use 'top' protection */ 795 if (!stm_is_unlocked_sr(nor, 0, ofs, status_old)) 796 can_be_top = false; 797 798 /* If anything above us is locked, we can't use 'bottom' protection */ 799 if (!stm_is_unlocked_sr(nor, ofs + len, mtd->size - (ofs + len), 800 status_old)) 801 can_be_bottom = false; 802 803 if (!can_be_bottom && !can_be_top) 804 return -EINVAL; 805 806 /* Prefer top, if both are valid */ 807 use_top = can_be_top; 808 809 /* lock_len: length of region that should remain locked */ 810 if (use_top) 811 lock_len = mtd->size - (ofs + len); 812 else 813 lock_len = ofs; 814 815 /* 816 * Need largest pow such that: 817 * 818 * 1 / (2^pow) >= (len / size) 819 * 820 * so (assuming power-of-2 size) we do: 821 * 822 * pow = floor(log2(size / len)) = log2(size) - ceil(log2(len)) 823 */ 824 pow = ilog2(mtd->size) - order_base_2(lock_len); 825 if (lock_len == 0) { 826 val = 0; /* fully unlocked */ 827 } else { 828 val = mask - (pow << shift); 829 /* Some power-of-two sizes are not supported */ 830 if (val & ~mask) 831 return -EINVAL; 832 } 833 834 status_new = (status_old & ~mask & ~SR_TB) | val; 835 836 /* Don't protect status register if we're fully unlocked */ 837 if (lock_len == 0) 838 status_new &= ~SR_SRWD; 839 840 if (!use_top) 841 status_new |= SR_TB; 842 843 /* Don't bother if they're the same */ 844 if (status_new == status_old) 845 return 0; 846 847 /* Only modify protection if it will not lock other areas */ 848 if ((status_new & mask) > (status_old & mask)) 849 return -EINVAL; 850 851 return write_sr_and_check(nor, status_new, mask); 852 } 853 854 /* 855 * Check if a region of the flash is (completely) locked. See stm_lock() for 856 * more info. 857 * 858 * Returns 1 if entire region is locked, 0 if any portion is unlocked, and 859 * negative on errors. 860 */ 861 static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len) 862 { 863 int status; 864 865 status = read_sr(nor); 866 if (status < 0) 867 return status; 868 869 return stm_is_locked_sr(nor, ofs, len, status); 870 } 871 #endif /* CONFIG_SPI_FLASH_STMICRO */ 872 873 static const struct flash_info *spi_nor_read_id(struct spi_nor *nor) 874 { 875 int tmp; 876 u8 id[SPI_NOR_MAX_ID_LEN]; 877 const struct flash_info *info; 878 879 tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN); 880 if (tmp < 0) { 881 dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp); 882 return ERR_PTR(tmp); 883 } 884 885 info = spi_nor_ids; 886 for (; info->name; info++) { 887 if (info->id_len) { 888 if (!memcmp(info->id, id, info->id_len)) 889 return info; 890 } 891 } 892 893 dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n", 894 id[0], id[1], id[2]); 895 return ERR_PTR(-ENODEV); 896 } 897 898 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, 899 size_t *retlen, u_char *buf) 900 { 901 struct spi_nor *nor = mtd_to_spi_nor(mtd); 902 int ret; 903 904 dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len); 905 906 while (len) { 907 loff_t addr = from; 908 size_t read_len = len; 909 910 #ifdef CONFIG_SPI_FLASH_BAR 911 u32 remain_len; 912 913 ret = write_bar(nor, addr); 914 if (ret < 0) 915 return log_ret(ret); 916 remain_len = (SZ_16M * (nor->bank_curr + 1)) - addr; 917 918 if (len < remain_len) 919 read_len = len; 920 else 921 read_len = remain_len; 922 #endif 923 924 ret = nor->read(nor, addr, read_len, buf); 925 if (ret == 0) { 926 /* We shouldn't see 0-length reads */ 927 ret = -EIO; 928 goto read_err; 929 } 930 if (ret < 0) 931 goto read_err; 932 933 *retlen += ret; 934 buf += ret; 935 from += ret; 936 len -= ret; 937 } 938 ret = 0; 939 940 read_err: 941 #ifdef CONFIG_SPI_FLASH_BAR 942 ret = clean_bar(nor); 943 #endif 944 return ret; 945 } 946 947 #ifdef CONFIG_SPI_FLASH_SST 948 static int sst_write_byteprogram(struct spi_nor *nor, loff_t to, size_t len, 949 size_t *retlen, const u_char *buf) 950 { 951 size_t actual; 952 int ret = 0; 953 954 for (actual = 0; actual < len; actual++) { 955 nor->program_opcode = SPINOR_OP_BP; 956 957 write_enable(nor); 958 /* write one byte. */ 959 ret = nor->write(nor, to, 1, buf + actual); 960 if (ret < 0) 961 goto sst_write_err; 962 ret = spi_nor_wait_till_ready(nor); 963 if (ret) 964 goto sst_write_err; 965 to++; 966 } 967 968 sst_write_err: 969 write_disable(nor); 970 return ret; 971 } 972 973 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, 974 size_t *retlen, const u_char *buf) 975 { 976 struct spi_nor *nor = mtd_to_spi_nor(mtd); 977 struct spi_slave *spi = nor->spi; 978 size_t actual; 979 int ret; 980 981 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); 982 if (spi->mode & SPI_TX_BYTE) 983 return sst_write_byteprogram(nor, to, len, retlen, buf); 984 985 write_enable(nor); 986 987 nor->sst_write_second = false; 988 989 actual = to % 2; 990 /* Start write from odd address. */ 991 if (actual) { 992 nor->program_opcode = SPINOR_OP_BP; 993 994 /* write one byte. */ 995 ret = nor->write(nor, to, 1, buf); 996 if (ret < 0) 997 goto sst_write_err; 998 ret = spi_nor_wait_till_ready(nor); 999 if (ret) 1000 goto sst_write_err; 1001 } 1002 to += actual; 1003 1004 /* Write out most of the data here. */ 1005 for (; actual < len - 1; actual += 2) { 1006 nor->program_opcode = SPINOR_OP_AAI_WP; 1007 1008 /* write two bytes. */ 1009 ret = nor->write(nor, to, 2, buf + actual); 1010 if (ret < 0) 1011 goto sst_write_err; 1012 ret = spi_nor_wait_till_ready(nor); 1013 if (ret) 1014 goto sst_write_err; 1015 to += 2; 1016 nor->sst_write_second = true; 1017 } 1018 nor->sst_write_second = false; 1019 1020 write_disable(nor); 1021 ret = spi_nor_wait_till_ready(nor); 1022 if (ret) 1023 goto sst_write_err; 1024 1025 /* Write out trailing byte if it exists. */ 1026 if (actual != len) { 1027 write_enable(nor); 1028 1029 nor->program_opcode = SPINOR_OP_BP; 1030 ret = nor->write(nor, to, 1, buf + actual); 1031 if (ret < 0) 1032 goto sst_write_err; 1033 ret = spi_nor_wait_till_ready(nor); 1034 if (ret) 1035 goto sst_write_err; 1036 write_disable(nor); 1037 actual += 1; 1038 } 1039 sst_write_err: 1040 *retlen += actual; 1041 return ret; 1042 } 1043 #endif 1044 /* 1045 * Write an address range to the nor chip. Data must be written in 1046 * FLASH_PAGESIZE chunks. The address range may be any size provided 1047 * it is within the physical boundaries. 1048 */ 1049 static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len, 1050 size_t *retlen, const u_char *buf) 1051 { 1052 struct spi_nor *nor = mtd_to_spi_nor(mtd); 1053 size_t page_offset, page_remain, i; 1054 ssize_t ret; 1055 1056 dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len); 1057 1058 for (i = 0; i < len; ) { 1059 ssize_t written; 1060 loff_t addr = to + i; 1061 1062 /* 1063 * If page_size is a power of two, the offset can be quickly 1064 * calculated with an AND operation. On the other cases we 1065 * need to do a modulus operation (more expensive). 1066 * Power of two numbers have only one bit set and we can use 1067 * the instruction hweight32 to detect if we need to do a 1068 * modulus (do_div()) or not. 1069 */ 1070 if (hweight32(nor->page_size) == 1) { 1071 page_offset = addr & (nor->page_size - 1); 1072 } else { 1073 u64 aux = addr; 1074 1075 page_offset = do_div(aux, nor->page_size); 1076 } 1077 /* the size of data remaining on the first page */ 1078 page_remain = min_t(size_t, 1079 nor->page_size - page_offset, len - i); 1080 1081 #ifdef CONFIG_SPI_FLASH_BAR 1082 ret = write_bar(nor, addr); 1083 if (ret < 0) 1084 return ret; 1085 #endif 1086 write_enable(nor); 1087 ret = nor->write(nor, addr, page_remain, buf + i); 1088 if (ret < 0) 1089 goto write_err; 1090 written = ret; 1091 1092 ret = spi_nor_wait_till_ready(nor); 1093 if (ret) 1094 goto write_err; 1095 *retlen += written; 1096 i += written; 1097 } 1098 1099 write_err: 1100 #ifdef CONFIG_SPI_FLASH_BAR 1101 ret = clean_bar(nor); 1102 #endif 1103 return ret; 1104 } 1105 1106 #ifdef CONFIG_SPI_FLASH_MACRONIX 1107 /** 1108 * macronix_quad_enable() - set QE bit in Status Register. 1109 * @nor: pointer to a 'struct spi_nor' 1110 * 1111 * Set the Quad Enable (QE) bit in the Status Register. 1112 * 1113 * bit 6 of the Status Register is the QE bit for Macronix like QSPI memories. 1114 * 1115 * Return: 0 on success, -errno otherwise. 1116 */ 1117 static int macronix_quad_enable(struct spi_nor *nor) 1118 { 1119 int ret, val; 1120 1121 val = read_sr(nor); 1122 if (val < 0) 1123 return val; 1124 if (val & SR_QUAD_EN_MX) 1125 return 0; 1126 1127 write_enable(nor); 1128 1129 write_sr(nor, val | SR_QUAD_EN_MX); 1130 1131 ret = spi_nor_wait_till_ready(nor); 1132 if (ret) 1133 return ret; 1134 1135 ret = read_sr(nor); 1136 if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) { 1137 dev_err(nor->dev, "Macronix Quad bit not set\n"); 1138 return -EINVAL; 1139 } 1140 1141 return 0; 1142 } 1143 #endif 1144 1145 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 1146 /* 1147 * Write status Register and configuration register with 2 bytes 1148 * The first byte will be written to the status register, while the 1149 * second byte will be written to the configuration register. 1150 * Return negative if error occurred. 1151 */ 1152 static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr) 1153 { 1154 int ret; 1155 1156 write_enable(nor); 1157 1158 ret = nor->write_reg(nor, SPINOR_OP_WRSR, sr_cr, 2); 1159 if (ret < 0) { 1160 dev_dbg(nor->dev, 1161 "error while writing configuration register\n"); 1162 return -EINVAL; 1163 } 1164 1165 ret = spi_nor_wait_till_ready(nor); 1166 if (ret) { 1167 dev_dbg(nor->dev, 1168 "timeout while writing configuration register\n"); 1169 return ret; 1170 } 1171 1172 return 0; 1173 } 1174 1175 /** 1176 * spansion_read_cr_quad_enable() - set QE bit in Configuration Register. 1177 * @nor: pointer to a 'struct spi_nor' 1178 * 1179 * Set the Quad Enable (QE) bit in the Configuration Register. 1180 * This function should be used with QSPI memories supporting the Read 1181 * Configuration Register (35h) instruction. 1182 * 1183 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI 1184 * memories. 1185 * 1186 * Return: 0 on success, -errno otherwise. 1187 */ 1188 static int spansion_read_cr_quad_enable(struct spi_nor *nor) 1189 { 1190 u8 sr_cr[2]; 1191 int ret; 1192 1193 /* Check current Quad Enable bit value. */ 1194 ret = read_cr(nor); 1195 if (ret < 0) { 1196 dev_dbg(dev, "error while reading configuration register\n"); 1197 return -EINVAL; 1198 } 1199 1200 if (ret & CR_QUAD_EN_SPAN) 1201 return 0; 1202 1203 sr_cr[1] = ret | CR_QUAD_EN_SPAN; 1204 1205 /* Keep the current value of the Status Register. */ 1206 ret = read_sr(nor); 1207 if (ret < 0) { 1208 dev_dbg(dev, "error while reading status register\n"); 1209 return -EINVAL; 1210 } 1211 sr_cr[0] = ret; 1212 1213 ret = write_sr_cr(nor, sr_cr); 1214 if (ret) 1215 return ret; 1216 1217 /* Read back and check it. */ 1218 ret = read_cr(nor); 1219 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) { 1220 dev_dbg(nor->dev, "Spansion Quad bit not set\n"); 1221 return -EINVAL; 1222 } 1223 1224 return 0; 1225 } 1226 1227 #if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT) 1228 /** 1229 * spansion_no_read_cr_quad_enable() - set QE bit in Configuration Register. 1230 * @nor: pointer to a 'struct spi_nor' 1231 * 1232 * Set the Quad Enable (QE) bit in the Configuration Register. 1233 * This function should be used with QSPI memories not supporting the Read 1234 * Configuration Register (35h) instruction. 1235 * 1236 * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI 1237 * memories. 1238 * 1239 * Return: 0 on success, -errno otherwise. 1240 */ 1241 static int spansion_no_read_cr_quad_enable(struct spi_nor *nor) 1242 { 1243 u8 sr_cr[2]; 1244 int ret; 1245 1246 /* Keep the current value of the Status Register. */ 1247 ret = read_sr(nor); 1248 if (ret < 0) { 1249 dev_dbg(nor->dev, "error while reading status register\n"); 1250 return -EINVAL; 1251 } 1252 sr_cr[0] = ret; 1253 sr_cr[1] = CR_QUAD_EN_SPAN; 1254 1255 return write_sr_cr(nor, sr_cr); 1256 } 1257 1258 #endif /* CONFIG_SPI_FLASH_SFDP_SUPPORT */ 1259 #endif /* CONFIG_SPI_FLASH_SPANSION */ 1260 1261 struct spi_nor_read_command { 1262 u8 num_mode_clocks; 1263 u8 num_wait_states; 1264 u8 opcode; 1265 enum spi_nor_protocol proto; 1266 }; 1267 1268 struct spi_nor_pp_command { 1269 u8 opcode; 1270 enum spi_nor_protocol proto; 1271 }; 1272 1273 enum spi_nor_read_command_index { 1274 SNOR_CMD_READ, 1275 SNOR_CMD_READ_FAST, 1276 SNOR_CMD_READ_1_1_1_DTR, 1277 1278 /* Dual SPI */ 1279 SNOR_CMD_READ_1_1_2, 1280 SNOR_CMD_READ_1_2_2, 1281 SNOR_CMD_READ_2_2_2, 1282 SNOR_CMD_READ_1_2_2_DTR, 1283 1284 /* Quad SPI */ 1285 SNOR_CMD_READ_1_1_4, 1286 SNOR_CMD_READ_1_4_4, 1287 SNOR_CMD_READ_4_4_4, 1288 SNOR_CMD_READ_1_4_4_DTR, 1289 1290 /* Octo SPI */ 1291 SNOR_CMD_READ_1_1_8, 1292 SNOR_CMD_READ_1_8_8, 1293 SNOR_CMD_READ_8_8_8, 1294 SNOR_CMD_READ_1_8_8_DTR, 1295 1296 SNOR_CMD_READ_MAX 1297 }; 1298 1299 enum spi_nor_pp_command_index { 1300 SNOR_CMD_PP, 1301 1302 /* Quad SPI */ 1303 SNOR_CMD_PP_1_1_4, 1304 SNOR_CMD_PP_1_4_4, 1305 SNOR_CMD_PP_4_4_4, 1306 1307 /* Octo SPI */ 1308 SNOR_CMD_PP_1_1_8, 1309 SNOR_CMD_PP_1_8_8, 1310 SNOR_CMD_PP_8_8_8, 1311 1312 SNOR_CMD_PP_MAX 1313 }; 1314 1315 struct spi_nor_flash_parameter { 1316 u64 size; 1317 u32 page_size; 1318 1319 struct spi_nor_hwcaps hwcaps; 1320 struct spi_nor_read_command reads[SNOR_CMD_READ_MAX]; 1321 struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX]; 1322 1323 int (*quad_enable)(struct spi_nor *nor); 1324 }; 1325 1326 static void 1327 spi_nor_set_read_settings(struct spi_nor_read_command *read, 1328 u8 num_mode_clocks, 1329 u8 num_wait_states, 1330 u8 opcode, 1331 enum spi_nor_protocol proto) 1332 { 1333 read->num_mode_clocks = num_mode_clocks; 1334 read->num_wait_states = num_wait_states; 1335 read->opcode = opcode; 1336 read->proto = proto; 1337 } 1338 1339 static void 1340 spi_nor_set_pp_settings(struct spi_nor_pp_command *pp, 1341 u8 opcode, 1342 enum spi_nor_protocol proto) 1343 { 1344 pp->opcode = opcode; 1345 pp->proto = proto; 1346 } 1347 1348 #if CONFIG_IS_ENABLED(SPI_FLASH_SFDP_SUPPORT) 1349 /* 1350 * Serial Flash Discoverable Parameters (SFDP) parsing. 1351 */ 1352 1353 /** 1354 * spi_nor_read_sfdp() - read Serial Flash Discoverable Parameters. 1355 * @nor: pointer to a 'struct spi_nor' 1356 * @addr: offset in the SFDP area to start reading data from 1357 * @len: number of bytes to read 1358 * @buf: buffer where the SFDP data are copied into (dma-safe memory) 1359 * 1360 * Whatever the actual numbers of bytes for address and dummy cycles are 1361 * for (Fast) Read commands, the Read SFDP (5Ah) instruction is always 1362 * followed by a 3-byte address and 8 dummy clock cycles. 1363 * 1364 * Return: 0 on success, -errno otherwise. 1365 */ 1366 static int spi_nor_read_sfdp(struct spi_nor *nor, u32 addr, 1367 size_t len, void *buf) 1368 { 1369 u8 addr_width, read_opcode, read_dummy; 1370 int ret; 1371 1372 read_opcode = nor->read_opcode; 1373 addr_width = nor->addr_width; 1374 read_dummy = nor->read_dummy; 1375 1376 nor->read_opcode = SPINOR_OP_RDSFDP; 1377 nor->addr_width = 3; 1378 nor->read_dummy = 8; 1379 1380 while (len) { 1381 ret = nor->read(nor, addr, len, (u8 *)buf); 1382 if (!ret || ret > len) { 1383 ret = -EIO; 1384 goto read_err; 1385 } 1386 if (ret < 0) 1387 goto read_err; 1388 1389 buf += ret; 1390 addr += ret; 1391 len -= ret; 1392 } 1393 ret = 0; 1394 1395 read_err: 1396 nor->read_opcode = read_opcode; 1397 nor->addr_width = addr_width; 1398 nor->read_dummy = read_dummy; 1399 1400 return ret; 1401 } 1402 1403 struct sfdp_parameter_header { 1404 u8 id_lsb; 1405 u8 minor; 1406 u8 major; 1407 u8 length; /* in double words */ 1408 u8 parameter_table_pointer[3]; /* byte address */ 1409 u8 id_msb; 1410 }; 1411 1412 #define SFDP_PARAM_HEADER_ID(p) (((p)->id_msb << 8) | (p)->id_lsb) 1413 #define SFDP_PARAM_HEADER_PTP(p) \ 1414 (((p)->parameter_table_pointer[2] << 16) | \ 1415 ((p)->parameter_table_pointer[1] << 8) | \ 1416 ((p)->parameter_table_pointer[0] << 0)) 1417 1418 #define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */ 1419 #define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */ 1420 1421 #define SFDP_SIGNATURE 0x50444653U 1422 #define SFDP_JESD216_MAJOR 1 1423 #define SFDP_JESD216_MINOR 0 1424 #define SFDP_JESD216A_MINOR 5 1425 #define SFDP_JESD216B_MINOR 6 1426 1427 struct sfdp_header { 1428 u32 signature; /* Ox50444653U <=> "SFDP" */ 1429 u8 minor; 1430 u8 major; 1431 u8 nph; /* 0-base number of parameter headers */ 1432 u8 unused; 1433 1434 /* Basic Flash Parameter Table. */ 1435 struct sfdp_parameter_header bfpt_header; 1436 }; 1437 1438 /* Basic Flash Parameter Table */ 1439 1440 /* 1441 * JESD216 rev B defines a Basic Flash Parameter Table of 16 DWORDs. 1442 * They are indexed from 1 but C arrays are indexed from 0. 1443 */ 1444 #define BFPT_DWORD(i) ((i) - 1) 1445 #define BFPT_DWORD_MAX 16 1446 1447 /* The first version of JESB216 defined only 9 DWORDs. */ 1448 #define BFPT_DWORD_MAX_JESD216 9 1449 1450 /* 1st DWORD. */ 1451 #define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16) 1452 #define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17) 1453 #define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17) 1454 #define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17) 1455 #define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17) 1456 #define BFPT_DWORD1_DTR BIT(19) 1457 #define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20) 1458 #define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21) 1459 #define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22) 1460 1461 /* 5th DWORD. */ 1462 #define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0) 1463 #define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4) 1464 1465 /* 11th DWORD. */ 1466 #define BFPT_DWORD11_PAGE_SIZE_SHIFT 4 1467 #define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4) 1468 1469 /* 15th DWORD. */ 1470 1471 /* 1472 * (from JESD216 rev B) 1473 * Quad Enable Requirements (QER): 1474 * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4 1475 * reads based on instruction. DQ3/HOLD# functions are hold during 1476 * instruction phase. 1477 * - 001b: QE is bit 1 of status register 2. It is set via Write Status with 1478 * two data bytes where bit 1 of the second byte is one. 1479 * [...] 1480 * Writing only one byte to the status register has the side-effect of 1481 * clearing status register 2, including the QE bit. The 100b code is 1482 * used if writing one byte to the status register does not modify 1483 * status register 2. 1484 * - 010b: QE is bit 6 of status register 1. It is set via Write Status with 1485 * one data byte where bit 6 is one. 1486 * [...] 1487 * - 011b: QE is bit 7 of status register 2. It is set via Write status 1488 * register 2 instruction 3Eh with one data byte where bit 7 is one. 1489 * [...] 1490 * The status register 2 is read using instruction 3Fh. 1491 * - 100b: QE is bit 1 of status register 2. It is set via Write Status with 1492 * two data bytes where bit 1 of the second byte is one. 1493 * [...] 1494 * In contrast to the 001b code, writing one byte to the status 1495 * register does not modify status register 2. 1496 * - 101b: QE is bit 1 of status register 2. Status register 1 is read using 1497 * Read Status instruction 05h. Status register2 is read using 1498 * instruction 35h. QE is set via Writ Status instruction 01h with 1499 * two data bytes where bit 1 of the second byte is one. 1500 * [...] 1501 */ 1502 #define BFPT_DWORD15_QER_MASK GENMASK(22, 20) 1503 #define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */ 1504 #define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20) 1505 #define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */ 1506 #define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20) 1507 #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20) 1508 #define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */ 1509 1510 struct sfdp_bfpt { 1511 u32 dwords[BFPT_DWORD_MAX]; 1512 }; 1513 1514 /* Fast Read settings. */ 1515 1516 static void 1517 spi_nor_set_read_settings_from_bfpt(struct spi_nor_read_command *read, 1518 u16 half, 1519 enum spi_nor_protocol proto) 1520 { 1521 read->num_mode_clocks = (half >> 5) & 0x07; 1522 read->num_wait_states = (half >> 0) & 0x1f; 1523 read->opcode = (half >> 8) & 0xff; 1524 read->proto = proto; 1525 } 1526 1527 struct sfdp_bfpt_read { 1528 /* The Fast Read x-y-z hardware capability in params->hwcaps.mask. */ 1529 u32 hwcaps; 1530 1531 /* 1532 * The <supported_bit> bit in <supported_dword> BFPT DWORD tells us 1533 * whether the Fast Read x-y-z command is supported. 1534 */ 1535 u32 supported_dword; 1536 u32 supported_bit; 1537 1538 /* 1539 * The half-word at offset <setting_shift> in <setting_dword> BFPT DWORD 1540 * encodes the op code, the number of mode clocks and the number of wait 1541 * states to be used by Fast Read x-y-z command. 1542 */ 1543 u32 settings_dword; 1544 u32 settings_shift; 1545 1546 /* The SPI protocol for this Fast Read x-y-z command. */ 1547 enum spi_nor_protocol proto; 1548 }; 1549 1550 static const struct sfdp_bfpt_read sfdp_bfpt_reads[] = { 1551 /* Fast Read 1-1-2 */ 1552 { 1553 SNOR_HWCAPS_READ_1_1_2, 1554 BFPT_DWORD(1), BIT(16), /* Supported bit */ 1555 BFPT_DWORD(4), 0, /* Settings */ 1556 SNOR_PROTO_1_1_2, 1557 }, 1558 1559 /* Fast Read 1-2-2 */ 1560 { 1561 SNOR_HWCAPS_READ_1_2_2, 1562 BFPT_DWORD(1), BIT(20), /* Supported bit */ 1563 BFPT_DWORD(4), 16, /* Settings */ 1564 SNOR_PROTO_1_2_2, 1565 }, 1566 1567 /* Fast Read 2-2-2 */ 1568 { 1569 SNOR_HWCAPS_READ_2_2_2, 1570 BFPT_DWORD(5), BIT(0), /* Supported bit */ 1571 BFPT_DWORD(6), 16, /* Settings */ 1572 SNOR_PROTO_2_2_2, 1573 }, 1574 1575 /* Fast Read 1-1-4 */ 1576 { 1577 SNOR_HWCAPS_READ_1_1_4, 1578 BFPT_DWORD(1), BIT(22), /* Supported bit */ 1579 BFPT_DWORD(3), 16, /* Settings */ 1580 SNOR_PROTO_1_1_4, 1581 }, 1582 1583 /* Fast Read 1-4-4 */ 1584 { 1585 SNOR_HWCAPS_READ_1_4_4, 1586 BFPT_DWORD(1), BIT(21), /* Supported bit */ 1587 BFPT_DWORD(3), 0, /* Settings */ 1588 SNOR_PROTO_1_4_4, 1589 }, 1590 1591 /* Fast Read 4-4-4 */ 1592 { 1593 SNOR_HWCAPS_READ_4_4_4, 1594 BFPT_DWORD(5), BIT(4), /* Supported bit */ 1595 BFPT_DWORD(7), 16, /* Settings */ 1596 SNOR_PROTO_4_4_4, 1597 }, 1598 }; 1599 1600 struct sfdp_bfpt_erase { 1601 /* 1602 * The half-word at offset <shift> in DWORD <dwoard> encodes the 1603 * op code and erase sector size to be used by Sector Erase commands. 1604 */ 1605 u32 dword; 1606 u32 shift; 1607 }; 1608 1609 static const struct sfdp_bfpt_erase sfdp_bfpt_erases[] = { 1610 /* Erase Type 1 in DWORD8 bits[15:0] */ 1611 {BFPT_DWORD(8), 0}, 1612 1613 /* Erase Type 2 in DWORD8 bits[31:16] */ 1614 {BFPT_DWORD(8), 16}, 1615 1616 /* Erase Type 3 in DWORD9 bits[15:0] */ 1617 {BFPT_DWORD(9), 0}, 1618 1619 /* Erase Type 4 in DWORD9 bits[31:16] */ 1620 {BFPT_DWORD(9), 16}, 1621 }; 1622 1623 static int spi_nor_hwcaps_read2cmd(u32 hwcaps); 1624 1625 /** 1626 * spi_nor_parse_bfpt() - read and parse the Basic Flash Parameter Table. 1627 * @nor: pointer to a 'struct spi_nor' 1628 * @bfpt_header: pointer to the 'struct sfdp_parameter_header' describing 1629 * the Basic Flash Parameter Table length and version 1630 * @params: pointer to the 'struct spi_nor_flash_parameter' to be 1631 * filled 1632 * 1633 * The Basic Flash Parameter Table is the main and only mandatory table as 1634 * defined by the SFDP (JESD216) specification. 1635 * It provides us with the total size (memory density) of the data array and 1636 * the number of address bytes for Fast Read, Page Program and Sector Erase 1637 * commands. 1638 * For Fast READ commands, it also gives the number of mode clock cycles and 1639 * wait states (regrouped in the number of dummy clock cycles) for each 1640 * supported instruction op code. 1641 * For Page Program, the page size is now available since JESD216 rev A, however 1642 * the supported instruction op codes are still not provided. 1643 * For Sector Erase commands, this table stores the supported instruction op 1644 * codes and the associated sector sizes. 1645 * Finally, the Quad Enable Requirements (QER) are also available since JESD216 1646 * rev A. The QER bits encode the manufacturer dependent procedure to be 1647 * executed to set the Quad Enable (QE) bit in some internal register of the 1648 * Quad SPI memory. Indeed the QE bit, when it exists, must be set before 1649 * sending any Quad SPI command to the memory. Actually, setting the QE bit 1650 * tells the memory to reassign its WP# and HOLD#/RESET# pins to functions IO2 1651 * and IO3 hence enabling 4 (Quad) I/O lines. 1652 * 1653 * Return: 0 on success, -errno otherwise. 1654 */ 1655 static int spi_nor_parse_bfpt(struct spi_nor *nor, 1656 const struct sfdp_parameter_header *bfpt_header, 1657 struct spi_nor_flash_parameter *params) 1658 { 1659 struct mtd_info *mtd = &nor->mtd; 1660 struct sfdp_bfpt bfpt; 1661 size_t len; 1662 int i, cmd, err; 1663 u32 addr; 1664 u16 half; 1665 1666 /* JESD216 Basic Flash Parameter Table length is at least 9 DWORDs. */ 1667 if (bfpt_header->length < BFPT_DWORD_MAX_JESD216) 1668 return -EINVAL; 1669 1670 /* Read the Basic Flash Parameter Table. */ 1671 len = min_t(size_t, sizeof(bfpt), 1672 bfpt_header->length * sizeof(u32)); 1673 addr = SFDP_PARAM_HEADER_PTP(bfpt_header); 1674 memset(&bfpt, 0, sizeof(bfpt)); 1675 err = spi_nor_read_sfdp(nor, addr, len, &bfpt); 1676 if (err < 0) 1677 return err; 1678 1679 /* Fix endianness of the BFPT DWORDs. */ 1680 for (i = 0; i < BFPT_DWORD_MAX; i++) 1681 bfpt.dwords[i] = le32_to_cpu(bfpt.dwords[i]); 1682 1683 /* Number of address bytes. */ 1684 switch (bfpt.dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) { 1685 case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY: 1686 nor->addr_width = 3; 1687 break; 1688 1689 case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY: 1690 nor->addr_width = 4; 1691 break; 1692 1693 default: 1694 break; 1695 } 1696 1697 /* Flash Memory Density (in bits). */ 1698 params->size = bfpt.dwords[BFPT_DWORD(2)]; 1699 if (params->size & BIT(31)) { 1700 params->size &= ~BIT(31); 1701 1702 /* 1703 * Prevent overflows on params->size. Anyway, a NOR of 2^64 1704 * bits is unlikely to exist so this error probably means 1705 * the BFPT we are reading is corrupted/wrong. 1706 */ 1707 if (params->size > 63) 1708 return -EINVAL; 1709 1710 params->size = 1ULL << params->size; 1711 } else { 1712 params->size++; 1713 } 1714 params->size >>= 3; /* Convert to bytes. */ 1715 1716 /* Fast Read settings. */ 1717 for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_reads); i++) { 1718 const struct sfdp_bfpt_read *rd = &sfdp_bfpt_reads[i]; 1719 struct spi_nor_read_command *read; 1720 1721 if (!(bfpt.dwords[rd->supported_dword] & rd->supported_bit)) { 1722 params->hwcaps.mask &= ~rd->hwcaps; 1723 continue; 1724 } 1725 1726 params->hwcaps.mask |= rd->hwcaps; 1727 cmd = spi_nor_hwcaps_read2cmd(rd->hwcaps); 1728 read = ¶ms->reads[cmd]; 1729 half = bfpt.dwords[rd->settings_dword] >> rd->settings_shift; 1730 spi_nor_set_read_settings_from_bfpt(read, half, rd->proto); 1731 } 1732 1733 /* Sector Erase settings. */ 1734 for (i = 0; i < ARRAY_SIZE(sfdp_bfpt_erases); i++) { 1735 const struct sfdp_bfpt_erase *er = &sfdp_bfpt_erases[i]; 1736 u32 erasesize; 1737 u8 opcode; 1738 1739 half = bfpt.dwords[er->dword] >> er->shift; 1740 erasesize = half & 0xff; 1741 1742 /* erasesize == 0 means this Erase Type is not supported. */ 1743 if (!erasesize) 1744 continue; 1745 1746 erasesize = 1U << erasesize; 1747 opcode = (half >> 8) & 0xff; 1748 #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS 1749 if (erasesize == SZ_4K) { 1750 nor->erase_opcode = opcode; 1751 mtd->erasesize = erasesize; 1752 break; 1753 } 1754 #endif 1755 if (!mtd->erasesize || mtd->erasesize < erasesize) { 1756 nor->erase_opcode = opcode; 1757 mtd->erasesize = erasesize; 1758 } 1759 } 1760 1761 /* Stop here if not JESD216 rev A or later. */ 1762 if (bfpt_header->length < BFPT_DWORD_MAX) 1763 return 0; 1764 1765 /* Page size: this field specifies 'N' so the page size = 2^N bytes. */ 1766 params->page_size = bfpt.dwords[BFPT_DWORD(11)]; 1767 params->page_size &= BFPT_DWORD11_PAGE_SIZE_MASK; 1768 params->page_size >>= BFPT_DWORD11_PAGE_SIZE_SHIFT; 1769 params->page_size = 1U << params->page_size; 1770 1771 /* Quad Enable Requirements. */ 1772 switch (bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK) { 1773 case BFPT_DWORD15_QER_NONE: 1774 params->quad_enable = NULL; 1775 break; 1776 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 1777 case BFPT_DWORD15_QER_SR2_BIT1_BUGGY: 1778 case BFPT_DWORD15_QER_SR2_BIT1_NO_RD: 1779 params->quad_enable = spansion_no_read_cr_quad_enable; 1780 break; 1781 #endif 1782 #ifdef CONFIG_SPI_FLASH_MACRONIX 1783 case BFPT_DWORD15_QER_SR1_BIT6: 1784 params->quad_enable = macronix_quad_enable; 1785 break; 1786 #endif 1787 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 1788 case BFPT_DWORD15_QER_SR2_BIT1: 1789 params->quad_enable = spansion_read_cr_quad_enable; 1790 break; 1791 #endif 1792 default: 1793 return -EINVAL; 1794 } 1795 1796 return 0; 1797 } 1798 1799 /** 1800 * spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters. 1801 * @nor: pointer to a 'struct spi_nor' 1802 * @params: pointer to the 'struct spi_nor_flash_parameter' to be 1803 * filled 1804 * 1805 * The Serial Flash Discoverable Parameters are described by the JEDEC JESD216 1806 * specification. This is a standard which tends to supported by almost all 1807 * (Q)SPI memory manufacturers. Those hard-coded tables allow us to learn at 1808 * runtime the main parameters needed to perform basic SPI flash operations such 1809 * as Fast Read, Page Program or Sector Erase commands. 1810 * 1811 * Return: 0 on success, -errno otherwise. 1812 */ 1813 static int spi_nor_parse_sfdp(struct spi_nor *nor, 1814 struct spi_nor_flash_parameter *params) 1815 { 1816 const struct sfdp_parameter_header *param_header, *bfpt_header; 1817 struct sfdp_parameter_header *param_headers = NULL; 1818 struct sfdp_header header; 1819 size_t psize; 1820 int i, err; 1821 1822 /* Get the SFDP header. */ 1823 err = spi_nor_read_sfdp(nor, 0, sizeof(header), &header); 1824 if (err < 0) 1825 return err; 1826 1827 /* Check the SFDP header version. */ 1828 if (le32_to_cpu(header.signature) != SFDP_SIGNATURE || 1829 header.major != SFDP_JESD216_MAJOR) 1830 return -EINVAL; 1831 1832 /* 1833 * Verify that the first and only mandatory parameter header is a 1834 * Basic Flash Parameter Table header as specified in JESD216. 1835 */ 1836 bfpt_header = &header.bfpt_header; 1837 if (SFDP_PARAM_HEADER_ID(bfpt_header) != SFDP_BFPT_ID || 1838 bfpt_header->major != SFDP_JESD216_MAJOR) 1839 return -EINVAL; 1840 1841 /* 1842 * Allocate memory then read all parameter headers with a single 1843 * Read SFDP command. These parameter headers will actually be parsed 1844 * twice: a first time to get the latest revision of the basic flash 1845 * parameter table, then a second time to handle the supported optional 1846 * tables. 1847 * Hence we read the parameter headers once for all to reduce the 1848 * processing time. Also we use kmalloc() instead of devm_kmalloc() 1849 * because we don't need to keep these parameter headers: the allocated 1850 * memory is always released with kfree() before exiting this function. 1851 */ 1852 if (header.nph) { 1853 psize = header.nph * sizeof(*param_headers); 1854 1855 param_headers = kmalloc(psize, GFP_KERNEL); 1856 if (!param_headers) 1857 return -ENOMEM; 1858 1859 err = spi_nor_read_sfdp(nor, sizeof(header), 1860 psize, param_headers); 1861 if (err < 0) { 1862 dev_err(dev, "failed to read SFDP parameter headers\n"); 1863 goto exit; 1864 } 1865 } 1866 1867 /* 1868 * Check other parameter headers to get the latest revision of 1869 * the basic flash parameter table. 1870 */ 1871 for (i = 0; i < header.nph; i++) { 1872 param_header = ¶m_headers[i]; 1873 1874 if (SFDP_PARAM_HEADER_ID(param_header) == SFDP_BFPT_ID && 1875 param_header->major == SFDP_JESD216_MAJOR && 1876 (param_header->minor > bfpt_header->minor || 1877 (param_header->minor == bfpt_header->minor && 1878 param_header->length > bfpt_header->length))) 1879 bfpt_header = param_header; 1880 } 1881 1882 err = spi_nor_parse_bfpt(nor, bfpt_header, params); 1883 if (err) 1884 goto exit; 1885 1886 /* Parse other parameter headers. */ 1887 for (i = 0; i < header.nph; i++) { 1888 param_header = ¶m_headers[i]; 1889 1890 switch (SFDP_PARAM_HEADER_ID(param_header)) { 1891 case SFDP_SECTOR_MAP_ID: 1892 dev_info(dev, "non-uniform erase sector maps are not supported yet.\n"); 1893 break; 1894 1895 default: 1896 break; 1897 } 1898 1899 if (err) 1900 goto exit; 1901 } 1902 1903 exit: 1904 kfree(param_headers); 1905 return err; 1906 } 1907 #else 1908 static int spi_nor_parse_sfdp(struct spi_nor *nor, 1909 struct spi_nor_flash_parameter *params) 1910 { 1911 return -EINVAL; 1912 } 1913 #endif /* SPI_FLASH_SFDP_SUPPORT */ 1914 1915 static int spi_nor_init_params(struct spi_nor *nor, 1916 const struct flash_info *info, 1917 struct spi_nor_flash_parameter *params) 1918 { 1919 /* Set legacy flash parameters as default. */ 1920 memset(params, 0, sizeof(*params)); 1921 1922 /* Set SPI NOR sizes. */ 1923 params->size = info->sector_size * info->n_sectors; 1924 params->page_size = info->page_size; 1925 1926 /* (Fast) Read settings. */ 1927 params->hwcaps.mask |= SNOR_HWCAPS_READ; 1928 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ], 1929 0, 0, SPINOR_OP_READ, 1930 SNOR_PROTO_1_1_1); 1931 1932 if (!(info->flags & SPI_NOR_NO_FR)) { 1933 params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST; 1934 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_FAST], 1935 0, 8, SPINOR_OP_READ_FAST, 1936 SNOR_PROTO_1_1_1); 1937 } 1938 1939 if (info->flags & SPI_NOR_DUAL_READ) { 1940 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2; 1941 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_2], 1942 0, 8, SPINOR_OP_READ_1_1_2, 1943 SNOR_PROTO_1_1_2); 1944 } 1945 1946 if (info->flags & SPI_NOR_QUAD_READ) { 1947 params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4; 1948 spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4], 1949 0, 8, SPINOR_OP_READ_1_1_4, 1950 SNOR_PROTO_1_1_4); 1951 } 1952 1953 /* Page Program settings. */ 1954 params->hwcaps.mask |= SNOR_HWCAPS_PP; 1955 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP], 1956 SPINOR_OP_PP, SNOR_PROTO_1_1_1); 1957 1958 if (info->flags & SPI_NOR_QUAD_READ) { 1959 params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4; 1960 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_1_4], 1961 SPINOR_OP_PP_1_1_4, SNOR_PROTO_1_1_4); 1962 } 1963 1964 /* Select the procedure to set the Quad Enable bit. */ 1965 if (params->hwcaps.mask & (SNOR_HWCAPS_READ_QUAD | 1966 SNOR_HWCAPS_PP_QUAD)) { 1967 switch (JEDEC_MFR(info)) { 1968 #ifdef CONFIG_SPI_FLASH_MACRONIX 1969 case SNOR_MFR_MACRONIX: 1970 params->quad_enable = macronix_quad_enable; 1971 break; 1972 #endif 1973 case SNOR_MFR_ST: 1974 case SNOR_MFR_MICRON: 1975 break; 1976 1977 default: 1978 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) 1979 /* Kept only for backward compatibility purpose. */ 1980 params->quad_enable = spansion_read_cr_quad_enable; 1981 #endif 1982 break; 1983 } 1984 } 1985 1986 /* Override the parameters with data read from SFDP tables. */ 1987 nor->addr_width = 0; 1988 nor->mtd.erasesize = 0; 1989 if ((info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)) && 1990 !(info->flags & SPI_NOR_SKIP_SFDP)) { 1991 struct spi_nor_flash_parameter sfdp_params; 1992 1993 memcpy(&sfdp_params, params, sizeof(sfdp_params)); 1994 if (spi_nor_parse_sfdp(nor, &sfdp_params)) { 1995 nor->addr_width = 0; 1996 nor->mtd.erasesize = 0; 1997 } else { 1998 memcpy(params, &sfdp_params, sizeof(*params)); 1999 } 2000 } 2001 2002 return 0; 2003 } 2004 2005 static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size) 2006 { 2007 size_t i; 2008 2009 for (i = 0; i < size; i++) 2010 if (table[i][0] == (int)hwcaps) 2011 return table[i][1]; 2012 2013 return -EINVAL; 2014 } 2015 2016 static int spi_nor_hwcaps_read2cmd(u32 hwcaps) 2017 { 2018 static const int hwcaps_read2cmd[][2] = { 2019 { SNOR_HWCAPS_READ, SNOR_CMD_READ }, 2020 { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST }, 2021 { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR }, 2022 { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 }, 2023 { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 }, 2024 { SNOR_HWCAPS_READ_2_2_2, SNOR_CMD_READ_2_2_2 }, 2025 { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR }, 2026 { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 }, 2027 { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 }, 2028 { SNOR_HWCAPS_READ_4_4_4, SNOR_CMD_READ_4_4_4 }, 2029 { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR }, 2030 { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 }, 2031 { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 }, 2032 { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 }, 2033 { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR }, 2034 }; 2035 2036 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd, 2037 ARRAY_SIZE(hwcaps_read2cmd)); 2038 } 2039 2040 static int spi_nor_hwcaps_pp2cmd(u32 hwcaps) 2041 { 2042 static const int hwcaps_pp2cmd[][2] = { 2043 { SNOR_HWCAPS_PP, SNOR_CMD_PP }, 2044 { SNOR_HWCAPS_PP_1_1_4, SNOR_CMD_PP_1_1_4 }, 2045 { SNOR_HWCAPS_PP_1_4_4, SNOR_CMD_PP_1_4_4 }, 2046 { SNOR_HWCAPS_PP_4_4_4, SNOR_CMD_PP_4_4_4 }, 2047 { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 }, 2048 { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 }, 2049 { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 }, 2050 }; 2051 2052 return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd, 2053 ARRAY_SIZE(hwcaps_pp2cmd)); 2054 } 2055 2056 static int spi_nor_select_read(struct spi_nor *nor, 2057 const struct spi_nor_flash_parameter *params, 2058 u32 shared_hwcaps) 2059 { 2060 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_READ_MASK) - 1; 2061 const struct spi_nor_read_command *read; 2062 2063 if (best_match < 0) 2064 return -EINVAL; 2065 2066 cmd = spi_nor_hwcaps_read2cmd(BIT(best_match)); 2067 if (cmd < 0) 2068 return -EINVAL; 2069 2070 read = ¶ms->reads[cmd]; 2071 nor->read_opcode = read->opcode; 2072 nor->read_proto = read->proto; 2073 2074 /* 2075 * In the spi-nor framework, we don't need to make the difference 2076 * between mode clock cycles and wait state clock cycles. 2077 * Indeed, the value of the mode clock cycles is used by a QSPI 2078 * flash memory to know whether it should enter or leave its 0-4-4 2079 * (Continuous Read / XIP) mode. 2080 * eXecution In Place is out of the scope of the mtd sub-system. 2081 * Hence we choose to merge both mode and wait state clock cycles 2082 * into the so called dummy clock cycles. 2083 */ 2084 nor->read_dummy = read->num_mode_clocks + read->num_wait_states; 2085 return 0; 2086 } 2087 2088 static int spi_nor_select_pp(struct spi_nor *nor, 2089 const struct spi_nor_flash_parameter *params, 2090 u32 shared_hwcaps) 2091 { 2092 int cmd, best_match = fls(shared_hwcaps & SNOR_HWCAPS_PP_MASK) - 1; 2093 const struct spi_nor_pp_command *pp; 2094 2095 if (best_match < 0) 2096 return -EINVAL; 2097 2098 cmd = spi_nor_hwcaps_pp2cmd(BIT(best_match)); 2099 if (cmd < 0) 2100 return -EINVAL; 2101 2102 pp = ¶ms->page_programs[cmd]; 2103 nor->program_opcode = pp->opcode; 2104 nor->write_proto = pp->proto; 2105 return 0; 2106 } 2107 2108 static int spi_nor_select_erase(struct spi_nor *nor, 2109 const struct flash_info *info) 2110 { 2111 struct mtd_info *mtd = &nor->mtd; 2112 2113 /* Do nothing if already configured from SFDP. */ 2114 if (mtd->erasesize) 2115 return 0; 2116 2117 #ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS 2118 /* prefer "small sector" erase if possible */ 2119 if (info->flags & SECT_4K) { 2120 nor->erase_opcode = SPINOR_OP_BE_4K; 2121 mtd->erasesize = 4096; 2122 } else if (info->flags & SECT_4K_PMC) { 2123 nor->erase_opcode = SPINOR_OP_BE_4K_PMC; 2124 mtd->erasesize = 4096; 2125 } else 2126 #endif 2127 { 2128 nor->erase_opcode = SPINOR_OP_SE; 2129 mtd->erasesize = info->sector_size; 2130 } 2131 return 0; 2132 } 2133 2134 static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info, 2135 const struct spi_nor_flash_parameter *params, 2136 const struct spi_nor_hwcaps *hwcaps) 2137 { 2138 u32 ignored_mask, shared_mask; 2139 bool enable_quad_io; 2140 int err; 2141 2142 /* 2143 * Keep only the hardware capabilities supported by both the SPI 2144 * controller and the SPI flash memory. 2145 */ 2146 shared_mask = hwcaps->mask & params->hwcaps.mask; 2147 2148 /* SPI n-n-n protocols are not supported yet. */ 2149 ignored_mask = (SNOR_HWCAPS_READ_2_2_2 | 2150 SNOR_HWCAPS_READ_4_4_4 | 2151 SNOR_HWCAPS_READ_8_8_8 | 2152 SNOR_HWCAPS_PP_4_4_4 | 2153 SNOR_HWCAPS_PP_8_8_8); 2154 if (shared_mask & ignored_mask) { 2155 dev_dbg(nor->dev, 2156 "SPI n-n-n protocols are not supported yet.\n"); 2157 shared_mask &= ~ignored_mask; 2158 } 2159 2160 /* Select the (Fast) Read command. */ 2161 err = spi_nor_select_read(nor, params, shared_mask); 2162 if (err) { 2163 dev_dbg(nor->dev, 2164 "can't select read settings supported by both the SPI controller and memory.\n"); 2165 return err; 2166 } 2167 2168 /* Select the Page Program command. */ 2169 err = spi_nor_select_pp(nor, params, shared_mask); 2170 if (err) { 2171 dev_dbg(nor->dev, 2172 "can't select write settings supported by both the SPI controller and memory.\n"); 2173 return err; 2174 } 2175 2176 /* Select the Sector Erase command. */ 2177 err = spi_nor_select_erase(nor, info); 2178 if (err) { 2179 dev_dbg(nor->dev, 2180 "can't select erase settings supported by both the SPI controller and memory.\n"); 2181 return err; 2182 } 2183 2184 /* Enable Quad I/O if needed. */ 2185 enable_quad_io = (spi_nor_get_protocol_width(nor->read_proto) == 4 || 2186 spi_nor_get_protocol_width(nor->write_proto) == 4); 2187 if (enable_quad_io && params->quad_enable) 2188 nor->quad_enable = params->quad_enable; 2189 else 2190 nor->quad_enable = NULL; 2191 2192 return 0; 2193 } 2194 2195 static int spi_nor_init(struct spi_nor *nor) 2196 { 2197 int err; 2198 2199 /* 2200 * Atmel, SST, Intel/Numonyx, and others serial NOR tend to power up 2201 * with the software protection bits set 2202 */ 2203 if (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL || 2204 JEDEC_MFR(nor->info) == SNOR_MFR_INTEL || 2205 JEDEC_MFR(nor->info) == SNOR_MFR_SST || 2206 nor->info->flags & SPI_NOR_HAS_LOCK) { 2207 write_enable(nor); 2208 write_sr(nor, 0); 2209 spi_nor_wait_till_ready(nor); 2210 } 2211 2212 if (nor->quad_enable) { 2213 err = nor->quad_enable(nor); 2214 if (err) { 2215 dev_dbg(nor->dev, "quad mode not supported\n"); 2216 return err; 2217 } 2218 } 2219 2220 if (nor->addr_width == 4 && 2221 (JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION) && 2222 !(nor->info->flags & SPI_NOR_4B_OPCODES)) { 2223 /* 2224 * If the RESET# pin isn't hooked up properly, or the system 2225 * otherwise doesn't perform a reset command in the boot 2226 * sequence, it's impossible to 100% protect against unexpected 2227 * reboots (e.g., crashes). Warn the user (or hopefully, system 2228 * designer) that this is bad. 2229 */ 2230 if (nor->flags & SNOR_F_BROKEN_RESET) 2231 printf("enabling reset hack; may not recover from unexpected reboots\n"); 2232 set_4byte(nor, nor->info, 1); 2233 } 2234 2235 return 0; 2236 } 2237 2238 int spi_nor_scan(struct spi_nor *nor) 2239 { 2240 struct spi_nor_flash_parameter params; 2241 const struct flash_info *info = NULL; 2242 struct mtd_info *mtd = &nor->mtd; 2243 struct spi_nor_hwcaps hwcaps = { 2244 .mask = SNOR_HWCAPS_READ | 2245 SNOR_HWCAPS_READ_FAST | 2246 SNOR_HWCAPS_PP, 2247 }; 2248 struct spi_slave *spi = nor->spi; 2249 int ret; 2250 2251 /* Reset SPI protocol for all commands. */ 2252 nor->reg_proto = SNOR_PROTO_1_1_1; 2253 nor->read_proto = SNOR_PROTO_1_1_1; 2254 nor->write_proto = SNOR_PROTO_1_1_1; 2255 nor->read = spi_nor_read_data; 2256 nor->write = spi_nor_write_data; 2257 nor->read_reg = spi_nor_read_reg; 2258 nor->write_reg = spi_nor_write_reg; 2259 2260 if (spi->mode & SPI_RX_QUAD) { 2261 hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4; 2262 2263 if (spi->mode & SPI_TX_QUAD) 2264 hwcaps.mask |= (SNOR_HWCAPS_READ_1_4_4 | 2265 SNOR_HWCAPS_PP_1_1_4 | 2266 SNOR_HWCAPS_PP_1_4_4); 2267 } else if (spi->mode & SPI_RX_DUAL) { 2268 hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2; 2269 2270 if (spi->mode & SPI_TX_DUAL) 2271 hwcaps.mask |= SNOR_HWCAPS_READ_1_2_2; 2272 } 2273 2274 info = spi_nor_read_id(nor); 2275 if (IS_ERR_OR_NULL(info)) 2276 return -ENOENT; 2277 /* Parse the Serial Flash Discoverable Parameters table. */ 2278 ret = spi_nor_init_params(nor, info, ¶ms); 2279 if (ret) 2280 return ret; 2281 2282 if (!mtd->name) 2283 mtd->name = info->name; 2284 mtd->priv = nor; 2285 mtd->type = MTD_NORFLASH; 2286 mtd->writesize = 1; 2287 mtd->flags = MTD_CAP_NORFLASH; 2288 mtd->size = params.size; 2289 mtd->_erase = spi_nor_erase; 2290 mtd->_read = spi_nor_read; 2291 2292 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST) 2293 /* NOR protection support for STmicro/Micron chips and similar */ 2294 if (JEDEC_MFR(info) == SNOR_MFR_ST || 2295 JEDEC_MFR(info) == SNOR_MFR_MICRON || 2296 JEDEC_MFR(info) == SNOR_MFR_SST || 2297 info->flags & SPI_NOR_HAS_LOCK) { 2298 nor->flash_lock = stm_lock; 2299 nor->flash_unlock = stm_unlock; 2300 nor->flash_is_locked = stm_is_locked; 2301 } 2302 #endif 2303 2304 #ifdef CONFIG_SPI_FLASH_SST 2305 /* sst nor chips use AAI word program */ 2306 if (info->flags & SST_WRITE) 2307 mtd->_write = sst_write; 2308 else 2309 #endif 2310 mtd->_write = spi_nor_write; 2311 2312 if (info->flags & USE_FSR) 2313 nor->flags |= SNOR_F_USE_FSR; 2314 if (info->flags & SPI_NOR_HAS_TB) 2315 nor->flags |= SNOR_F_HAS_SR_TB; 2316 if (info->flags & NO_CHIP_ERASE) 2317 nor->flags |= SNOR_F_NO_OP_CHIP_ERASE; 2318 if (info->flags & USE_CLSR) 2319 nor->flags |= SNOR_F_USE_CLSR; 2320 2321 if (info->flags & SPI_NOR_NO_ERASE) 2322 mtd->flags |= MTD_NO_ERASE; 2323 2324 nor->page_size = params.page_size; 2325 mtd->writebufsize = nor->page_size; 2326 2327 /* Some devices cannot do fast-read, no matter what DT tells us */ 2328 if ((info->flags & SPI_NOR_NO_FR) || (spi->mode & SPI_RX_SLOW)) 2329 params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST; 2330 2331 /* 2332 * Configure the SPI memory: 2333 * - select op codes for (Fast) Read, Page Program and Sector Erase. 2334 * - set the number of dummy cycles (mode cycles + wait states). 2335 * - set the SPI protocols for register and memory accesses. 2336 * - set the Quad Enable bit if needed (required by SPI x-y-4 protos). 2337 */ 2338 ret = spi_nor_setup(nor, info, ¶ms, &hwcaps); 2339 if (ret) 2340 return ret; 2341 2342 if (nor->addr_width) { 2343 /* already configured from SFDP */ 2344 } else if (info->addr_width) { 2345 nor->addr_width = info->addr_width; 2346 } else if (mtd->size > SZ_16M) { 2347 #ifndef CONFIG_SPI_FLASH_BAR 2348 /* enable 4-byte addressing if the device exceeds 16MiB */ 2349 nor->addr_width = 4; 2350 if (JEDEC_MFR(info) == SNOR_MFR_SPANSION || 2351 info->flags & SPI_NOR_4B_OPCODES) 2352 spi_nor_set_4byte_opcodes(nor, info); 2353 #else 2354 /* Configure the BAR - discover bank cmds and read current bank */ 2355 nor->addr_width = 3; 2356 ret = read_bar(nor, info); 2357 if (ret < 0) 2358 return ret; 2359 #endif 2360 } else { 2361 nor->addr_width = 3; 2362 } 2363 2364 if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) { 2365 dev_dbg(dev, "address width is too large: %u\n", 2366 nor->addr_width); 2367 return -EINVAL; 2368 } 2369 2370 /* Send all the required SPI flash commands to initialize device */ 2371 nor->info = info; 2372 ret = spi_nor_init(nor); 2373 if (ret) 2374 return ret; 2375 2376 nor->name = mtd->name; 2377 nor->size = mtd->size; 2378 nor->erase_size = mtd->erasesize; 2379 nor->sector_size = mtd->erasesize; 2380 2381 #ifndef CONFIG_SPL_BUILD 2382 printf("SF: Detected %s with page size ", nor->name); 2383 print_size(nor->page_size, ", erase size "); 2384 print_size(nor->erase_size, ", total "); 2385 print_size(nor->size, ""); 2386 puts("\n"); 2387 #endif 2388 2389 return 0; 2390 } 2391 2392 /* U-Boot specific functions, need to extend MTD to support these */ 2393 int spi_flash_cmd_get_sw_write_prot(struct spi_nor *nor) 2394 { 2395 int sr = read_sr(nor); 2396 2397 if (sr < 0) 2398 return sr; 2399 2400 return (sr >> 2) & 7; 2401 } 2402