1 /* 2 * SPI flash internal definitions 3 * 4 * Copyright (C) 2008 Atmel Corporation 5 * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef _SF_INTERNAL_H_ 11 #define _SF_INTERNAL_H_ 12 13 #include <linux/types.h> 14 #include <linux/compiler.h> 15 16 /* Dual SPI flash memories - see SPI_COMM_DUAL_... */ 17 enum spi_dual_flash { 18 SF_SINGLE_FLASH = 0, 19 SF_DUAL_STACKED_FLASH = BIT(0), 20 SF_DUAL_PARALLEL_FLASH = BIT(1), 21 }; 22 23 enum spi_nor_option_flags { 24 SNOR_F_SST_WR = BIT(0), 25 SNOR_F_USE_FSR = BIT(1), 26 SNOR_F_USE_UPAGE = BIT(3), 27 }; 28 29 #define SPI_FLASH_3B_ADDR_LEN 3 30 #define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN) 31 #define SPI_FLASH_16MB_BOUN 0x1000000 32 33 /* CFI Manufacture ID's */ 34 #define SPI_FLASH_CFI_MFR_SPANSION 0x01 35 #define SPI_FLASH_CFI_MFR_STMICRO 0x20 36 #define SPI_FLASH_CFI_MFR_MACRONIX 0xc2 37 #define SPI_FLASH_CFI_MFR_SST 0xbf 38 #define SPI_FLASH_CFI_MFR_WINBOND 0xef 39 #define SPI_FLASH_CFI_MFR_ATMEL 0x1f 40 #define SPI_FLASH_CIF_MFR_GIGADEVICE 0xc8 41 42 /* Erase commands */ 43 #define CMD_ERASE_4K 0x20 44 #define CMD_ERASE_CHIP 0xc7 45 #define CMD_ERASE_64K 0xd8 46 47 /* Write commands */ 48 #define CMD_WRITE_STATUS 0x01 49 #define CMD_PAGE_PROGRAM 0x02 50 #define CMD_WRITE_DISABLE 0x04 51 #define CMD_WRITE_ENABLE 0x06 52 #define CMD_QUAD_PAGE_PROGRAM 0x32 53 54 /* Read commands */ 55 #define CMD_READ_ARRAY_SLOW 0x03 56 #define CMD_READ_ARRAY_FAST 0x0b 57 #define CMD_READ_DUAL_OUTPUT_FAST 0x3b 58 #define CMD_READ_DUAL_IO_FAST 0xbb 59 #define CMD_READ_QUAD_OUTPUT_FAST 0x6b 60 #define CMD_READ_QUAD_IO_FAST 0xeb 61 #define CMD_READ_ID 0x9f 62 #define CMD_READ_STATUS 0x05 63 #define CMD_READ_STATUS1 0x35 64 #define CMD_READ_CONFIG 0x35 65 #define CMD_FLAG_STATUS 0x70 66 67 /* Bank addr access commands */ 68 #ifdef CONFIG_SPI_FLASH_BAR 69 # define CMD_BANKADDR_BRWR 0x17 70 # define CMD_BANKADDR_BRRD 0x16 71 # define CMD_EXTNADDR_WREAR 0xC5 72 # define CMD_EXTNADDR_RDEAR 0xC8 73 #endif 74 75 /* Common status */ 76 #define STATUS_WIP BIT(0) 77 #define STATUS_QEB_WINSPAN BIT(1) 78 #define STATUS_QEB_MXIC BIT(6) 79 #define STATUS_PEC BIT(7) 80 #define SR_BP0 BIT(2) /* Block protect 0 */ 81 #define SR_BP1 BIT(3) /* Block protect 1 */ 82 #define SR_BP2 BIT(4) /* Block protect 2 */ 83 84 /* Flash timeout values */ 85 #define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ) 86 #define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ) 87 #define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ) 88 89 /* SST specific */ 90 #ifdef CONFIG_SPI_FLASH_SST 91 #define SST26_CMD_READ_BPR 0x72 92 #define SST26_CMD_WRITE_BPR 0x42 93 94 #define SST26_BPR_8K_NUM 4 95 #define SST26_MAX_BPR_REG_LEN (18 + 1) 96 #define SST26_BOUND_REG_SIZE ((32 + SST26_BPR_8K_NUM * 8) * SZ_1K) 97 98 enum lock_ctl { 99 SST26_CTL_LOCK, 100 SST26_CTL_UNLOCK, 101 SST26_CTL_CHECK 102 }; 103 104 # define CMD_SST_BP 0x02 /* Byte Program */ 105 # define CMD_SST_AAI_WP 0xAD /* Auto Address Incr Word Program */ 106 107 int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, 108 const void *buf); 109 int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len, 110 const void *buf); 111 #endif 112 113 #define JEDEC_MFR(info) ((info)->id[0]) 114 #define JEDEC_ID(info) (((info)->id[1]) << 8 | ((info)->id[2])) 115 #define JEDEC_EXT(info) (((info)->id[3]) << 8 | ((info)->id[4])) 116 #define SPI_FLASH_MAX_ID_LEN 6 117 118 struct spi_flash_info { 119 /* Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO]) */ 120 const char *name; 121 122 /* 123 * This array stores the ID bytes. 124 * The first three bytes are the JEDIC ID. 125 * JEDEC ID zero means "no ID" (mostly older chips). 126 */ 127 u8 id[SPI_FLASH_MAX_ID_LEN]; 128 u8 id_len; 129 130 /* 131 * The size listed here is what works with SPINOR_OP_SE, which isn't 132 * necessarily called a "sector" by the vendor. 133 */ 134 u32 sector_size; 135 u32 n_sectors; 136 137 u16 page_size; 138 139 u16 flags; 140 #define SECT_4K BIT(0) /* CMD_ERASE_4K works uniformly */ 141 #define E_FSR BIT(1) /* use flag status register for */ 142 #define SST_WR BIT(2) /* use SST byte/word programming */ 143 #define WR_QPP BIT(3) /* use Quad Page Program */ 144 #define RD_QUAD BIT(4) /* use Quad Read */ 145 #define RD_DUAL BIT(5) /* use Dual Read */ 146 #define RD_QUADIO BIT(6) /* use Quad IO Read */ 147 #define RD_DUALIO BIT(7) /* use Dual IO Read */ 148 #define RD_FULL (RD_QUAD | RD_DUAL | RD_QUADIO | RD_DUALIO) 149 }; 150 151 extern const struct spi_flash_info spi_flash_ids[]; 152 153 /* Send a single-byte command to the device and read the response */ 154 int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len); 155 156 /* 157 * Send a multi-byte command to the device and read the response. Used 158 * for flash array reads, etc. 159 */ 160 int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd, 161 size_t cmd_len, void *data, size_t data_len); 162 163 /* 164 * Send a multi-byte command to the device followed by (optional) 165 * data. Used for programming the flash array, etc. 166 */ 167 int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, 168 const void *data, size_t data_len); 169 170 171 /* Flash erase(sectors) operation, support all possible erase commands */ 172 int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len); 173 174 /* Lock stmicro spi flash region */ 175 int stm_lock(struct spi_flash *flash, u32 ofs, size_t len); 176 177 /* Unlock stmicro spi flash region */ 178 int stm_unlock(struct spi_flash *flash, u32 ofs, size_t len); 179 180 /* Check if a stmicro spi flash region is completely locked */ 181 int stm_is_locked(struct spi_flash *flash, u32 ofs, size_t len); 182 183 /* Enable writing on the SPI flash */ 184 static inline int spi_flash_cmd_write_enable(struct spi_flash *flash) 185 { 186 return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0); 187 } 188 189 /* Disable writing on the SPI flash */ 190 static inline int spi_flash_cmd_write_disable(struct spi_flash *flash) 191 { 192 return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0); 193 } 194 195 /* 196 * Used for spi_flash write operation 197 * - SPI claim 198 * - spi_flash_cmd_write_enable 199 * - spi_flash_cmd_write 200 * - spi_flash_wait_till_ready 201 * - SPI release 202 */ 203 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, 204 size_t cmd_len, const void *buf, size_t buf_len); 205 206 /* 207 * Flash write operation, support all possible write commands. 208 * Write the requested data out breaking it up into multiple write 209 * commands as needed per the write size. 210 */ 211 int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, 212 size_t len, const void *buf); 213 214 /* 215 * Same as spi_flash_cmd_read() except it also claims/releases the SPI 216 * bus. Used as common part of the ->read() operation. 217 */ 218 int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, 219 size_t cmd_len, void *data, size_t data_len); 220 221 /* Flash read operation, support all possible read commands */ 222 int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, 223 size_t len, void *data); 224 225 #ifdef CONFIG_SPI_FLASH_MTD 226 int spi_flash_mtd_register(struct spi_flash *flash); 227 void spi_flash_mtd_unregister(void); 228 #endif 229 230 /** 231 * spi_flash_scan - scan the SPI FLASH 232 * @flash: the spi flash structure 233 * 234 * The drivers can use this fuction to scan the SPI FLASH. 235 * In the scanning, it will try to get all the necessary information to 236 * fill the spi_flash{}. 237 * 238 * Return: 0 for success, others for failure. 239 */ 240 int spi_flash_scan(struct spi_flash *flash); 241 242 #endif /* _SF_INTERNAL_H_ */ 243