1898e76c9SJagannadha Sutradharudu Teki /* 2898e76c9SJagannadha Sutradharudu Teki * SPI flash internal definitions 3898e76c9SJagannadha Sutradharudu Teki * 4898e76c9SJagannadha Sutradharudu Teki * Copyright (C) 2008 Atmel Corporation 5898e76c9SJagannadha Sutradharudu Teki * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. 6898e76c9SJagannadha Sutradharudu Teki * 70c88a84aSJagannadha Sutradharudu Teki * SPDX-License-Identifier: GPL-2.0+ 8898e76c9SJagannadha Sutradharudu Teki */ 9898e76c9SJagannadha Sutradharudu Teki 10469146c0SJagannadha Sutradharudu Teki #ifndef _SF_INTERNAL_H_ 11469146c0SJagannadha Sutradharudu Teki #define _SF_INTERNAL_H_ 12898e76c9SJagannadha Sutradharudu Teki 13898e76c9SJagannadha Sutradharudu Teki #define SPI_FLASH_16MB_BOUN 0x1000000 14898e76c9SJagannadha Sutradharudu Teki 15898e76c9SJagannadha Sutradharudu Teki /* SECT flags */ 16898e76c9SJagannadha Sutradharudu Teki #define SECT_4K (1 << 1) 17898e76c9SJagannadha Sutradharudu Teki #define SECT_32K (1 << 2) 18898e76c9SJagannadha Sutradharudu Teki #define E_FSR (1 << 3) 19898e76c9SJagannadha Sutradharudu Teki 20898e76c9SJagannadha Sutradharudu Teki /* Erase commands */ 21898e76c9SJagannadha Sutradharudu Teki #define CMD_ERASE_4K 0x20 22898e76c9SJagannadha Sutradharudu Teki #define CMD_ERASE_32K 0x52 23898e76c9SJagannadha Sutradharudu Teki #define CMD_ERASE_CHIP 0xc7 24898e76c9SJagannadha Sutradharudu Teki #define CMD_ERASE_64K 0xd8 25898e76c9SJagannadha Sutradharudu Teki 26898e76c9SJagannadha Sutradharudu Teki /* Write commands */ 27898e76c9SJagannadha Sutradharudu Teki #define CMD_WRITE_STATUS 0x01 28898e76c9SJagannadha Sutradharudu Teki #define CMD_PAGE_PROGRAM 0x02 29898e76c9SJagannadha Sutradharudu Teki #define CMD_WRITE_DISABLE 0x04 30898e76c9SJagannadha Sutradharudu Teki #define CMD_READ_STATUS 0x05 31*ffdb20beSMike Frysinger #define CMD_READ_STATUS1 0x35 32898e76c9SJagannadha Sutradharudu Teki #define CMD_WRITE_ENABLE 0x06 33898e76c9SJagannadha Sutradharudu Teki #define CMD_READ_CONFIG 0x35 34898e76c9SJagannadha Sutradharudu Teki #define CMD_FLAG_STATUS 0x70 35898e76c9SJagannadha Sutradharudu Teki 36898e76c9SJagannadha Sutradharudu Teki /* Read commands */ 37898e76c9SJagannadha Sutradharudu Teki #define CMD_READ_ARRAY_SLOW 0x03 38898e76c9SJagannadha Sutradharudu Teki #define CMD_READ_ARRAY_FAST 0x0b 39898e76c9SJagannadha Sutradharudu Teki #define CMD_READ_ID 0x9f 40898e76c9SJagannadha Sutradharudu Teki 41898e76c9SJagannadha Sutradharudu Teki /* Bank addr access commands */ 42898e76c9SJagannadha Sutradharudu Teki #ifdef CONFIG_SPI_FLASH_BAR 43898e76c9SJagannadha Sutradharudu Teki # define CMD_BANKADDR_BRWR 0x17 44898e76c9SJagannadha Sutradharudu Teki # define CMD_BANKADDR_BRRD 0x16 45898e76c9SJagannadha Sutradharudu Teki # define CMD_EXTNADDR_WREAR 0xC5 46898e76c9SJagannadha Sutradharudu Teki # define CMD_EXTNADDR_RDEAR 0xC8 47898e76c9SJagannadha Sutradharudu Teki #endif 48898e76c9SJagannadha Sutradharudu Teki 49898e76c9SJagannadha Sutradharudu Teki /* Common status */ 50898e76c9SJagannadha Sutradharudu Teki #define STATUS_WIP 0x01 51898e76c9SJagannadha Sutradharudu Teki #define STATUS_PEC 0x80 52898e76c9SJagannadha Sutradharudu Teki 53898e76c9SJagannadha Sutradharudu Teki /* Flash timeout values */ 54898e76c9SJagannadha Sutradharudu Teki #define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ) 55898e76c9SJagannadha Sutradharudu Teki #define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ) 56898e76c9SJagannadha Sutradharudu Teki #define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ) 57898e76c9SJagannadha Sutradharudu Teki 58898e76c9SJagannadha Sutradharudu Teki /* SST specific */ 59898e76c9SJagannadha Sutradharudu Teki #ifdef CONFIG_SPI_FLASH_SST 60898e76c9SJagannadha Sutradharudu Teki # define SST_WP 0x01 /* Supports AAI word program */ 61898e76c9SJagannadha Sutradharudu Teki # define CMD_SST_BP 0x02 /* Byte Program */ 62898e76c9SJagannadha Sutradharudu Teki # define CMD_SST_AAI_WP 0xAD /* Auto Address Incr Word Program */ 63898e76c9SJagannadha Sutradharudu Teki 64898e76c9SJagannadha Sutradharudu Teki int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, 65898e76c9SJagannadha Sutradharudu Teki const void *buf); 66898e76c9SJagannadha Sutradharudu Teki #endif 67898e76c9SJagannadha Sutradharudu Teki 68898e76c9SJagannadha Sutradharudu Teki /* Send a single-byte command to the device and read the response */ 69898e76c9SJagannadha Sutradharudu Teki int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len); 70898e76c9SJagannadha Sutradharudu Teki 71898e76c9SJagannadha Sutradharudu Teki /* 72898e76c9SJagannadha Sutradharudu Teki * Send a multi-byte command to the device and read the response. Used 73898e76c9SJagannadha Sutradharudu Teki * for flash array reads, etc. 74898e76c9SJagannadha Sutradharudu Teki */ 75898e76c9SJagannadha Sutradharudu Teki int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd, 76898e76c9SJagannadha Sutradharudu Teki size_t cmd_len, void *data, size_t data_len); 77898e76c9SJagannadha Sutradharudu Teki 78898e76c9SJagannadha Sutradharudu Teki /* 79898e76c9SJagannadha Sutradharudu Teki * Send a multi-byte command to the device followed by (optional) 80898e76c9SJagannadha Sutradharudu Teki * data. Used for programming the flash array, etc. 81898e76c9SJagannadha Sutradharudu Teki */ 82898e76c9SJagannadha Sutradharudu Teki int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, 83898e76c9SJagannadha Sutradharudu Teki const void *data, size_t data_len); 84898e76c9SJagannadha Sutradharudu Teki 85898e76c9SJagannadha Sutradharudu Teki 86898e76c9SJagannadha Sutradharudu Teki /* Flash erase(sectors) operation, support all possible erase commands */ 87898e76c9SJagannadha Sutradharudu Teki int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len); 88898e76c9SJagannadha Sutradharudu Teki 89898e76c9SJagannadha Sutradharudu Teki /* Program the status register */ 90898e76c9SJagannadha Sutradharudu Teki int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr); 91898e76c9SJagannadha Sutradharudu Teki 92898e76c9SJagannadha Sutradharudu Teki /* Set quad enbale bit */ 93898e76c9SJagannadha Sutradharudu Teki int spi_flash_set_qeb(struct spi_flash *flash); 94898e76c9SJagannadha Sutradharudu Teki 95898e76c9SJagannadha Sutradharudu Teki /* Enable writing on the SPI flash */ 96898e76c9SJagannadha Sutradharudu Teki static inline int spi_flash_cmd_write_enable(struct spi_flash *flash) 97898e76c9SJagannadha Sutradharudu Teki { 98898e76c9SJagannadha Sutradharudu Teki return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0); 99898e76c9SJagannadha Sutradharudu Teki } 100898e76c9SJagannadha Sutradharudu Teki 101898e76c9SJagannadha Sutradharudu Teki /* Disable writing on the SPI flash */ 102898e76c9SJagannadha Sutradharudu Teki static inline int spi_flash_cmd_write_disable(struct spi_flash *flash) 103898e76c9SJagannadha Sutradharudu Teki { 104898e76c9SJagannadha Sutradharudu Teki return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0); 105898e76c9SJagannadha Sutradharudu Teki } 106898e76c9SJagannadha Sutradharudu Teki 107898e76c9SJagannadha Sutradharudu Teki /* 108898e76c9SJagannadha Sutradharudu Teki * Send the read status command to the device and wait for the wip 109898e76c9SJagannadha Sutradharudu Teki * (write-in-progress) bit to clear itself. 110898e76c9SJagannadha Sutradharudu Teki */ 111898e76c9SJagannadha Sutradharudu Teki int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout); 112898e76c9SJagannadha Sutradharudu Teki 113898e76c9SJagannadha Sutradharudu Teki /* 114898e76c9SJagannadha Sutradharudu Teki * Used for spi_flash write operation 115898e76c9SJagannadha Sutradharudu Teki * - SPI claim 116898e76c9SJagannadha Sutradharudu Teki * - spi_flash_cmd_write_enable 117898e76c9SJagannadha Sutradharudu Teki * - spi_flash_cmd_write 118898e76c9SJagannadha Sutradharudu Teki * - spi_flash_cmd_wait_ready 119898e76c9SJagannadha Sutradharudu Teki * - SPI release 120898e76c9SJagannadha Sutradharudu Teki */ 121898e76c9SJagannadha Sutradharudu Teki int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, 122898e76c9SJagannadha Sutradharudu Teki size_t cmd_len, const void *buf, size_t buf_len); 123898e76c9SJagannadha Sutradharudu Teki 124898e76c9SJagannadha Sutradharudu Teki /* 125898e76c9SJagannadha Sutradharudu Teki * Flash write operation, support all possible write commands. 126898e76c9SJagannadha Sutradharudu Teki * Write the requested data out breaking it up into multiple write 127898e76c9SJagannadha Sutradharudu Teki * commands as needed per the write size. 128898e76c9SJagannadha Sutradharudu Teki */ 129898e76c9SJagannadha Sutradharudu Teki int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, 130898e76c9SJagannadha Sutradharudu Teki size_t len, const void *buf); 131898e76c9SJagannadha Sutradharudu Teki 132898e76c9SJagannadha Sutradharudu Teki /* 133898e76c9SJagannadha Sutradharudu Teki * Same as spi_flash_cmd_read() except it also claims/releases the SPI 134898e76c9SJagannadha Sutradharudu Teki * bus. Used as common part of the ->read() operation. 135898e76c9SJagannadha Sutradharudu Teki */ 136898e76c9SJagannadha Sutradharudu Teki int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, 137898e76c9SJagannadha Sutradharudu Teki size_t cmd_len, void *data, size_t data_len); 138898e76c9SJagannadha Sutradharudu Teki 139898e76c9SJagannadha Sutradharudu Teki /* Flash read operation, support all possible read commands */ 140898e76c9SJagannadha Sutradharudu Teki int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, 141898e76c9SJagannadha Sutradharudu Teki size_t len, void *data); 142898e76c9SJagannadha Sutradharudu Teki 143469146c0SJagannadha Sutradharudu Teki #endif /* _SF_INTERNAL_H_ */ 144