1898e76c9SJagannadha Sutradharudu Teki /* 2898e76c9SJagannadha Sutradharudu Teki * SPI flash internal definitions 3898e76c9SJagannadha Sutradharudu Teki * 4898e76c9SJagannadha Sutradharudu Teki * Copyright (C) 2008 Atmel Corporation 5898e76c9SJagannadha Sutradharudu Teki * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc. 6898e76c9SJagannadha Sutradharudu Teki * 70c88a84aSJagannadha Sutradharudu Teki * SPDX-License-Identifier: GPL-2.0+ 8898e76c9SJagannadha Sutradharudu Teki */ 9898e76c9SJagannadha Sutradharudu Teki 10469146c0SJagannadha Sutradharudu Teki #ifndef _SF_INTERNAL_H_ 11469146c0SJagannadha Sutradharudu Teki #define _SF_INTERNAL_H_ 12898e76c9SJagannadha Sutradharudu Teki 13ff0960f9SSimon Glass #include <linux/types.h> 14ff0960f9SSimon Glass #include <linux/compiler.h> 15ff0960f9SSimon Glass 16ff0960f9SSimon Glass /* Dual SPI flash memories - see SPI_COMM_DUAL_... */ 17ff0960f9SSimon Glass enum spi_dual_flash { 18ff0960f9SSimon Glass SF_SINGLE_FLASH = 0, 19ff0960f9SSimon Glass SF_DUAL_STACKED_FLASH = 1 << 0, 20ff0960f9SSimon Glass SF_DUAL_PARALLEL_FLASH = 1 << 1, 21ff0960f9SSimon Glass }; 22ff0960f9SSimon Glass 23ff0960f9SSimon Glass /* Enum list - Full read commands */ 24ff0960f9SSimon Glass enum spi_read_cmds { 25ff0960f9SSimon Glass ARRAY_SLOW = 1 << 0, 266dd6e90eSJagannadha Sutradharudu Teki ARRAY_FAST = 1 << 1, 276dd6e90eSJagannadha Sutradharudu Teki DUAL_OUTPUT_FAST = 1 << 2, 286dd6e90eSJagannadha Sutradharudu Teki DUAL_IO_FAST = 1 << 3, 296dd6e90eSJagannadha Sutradharudu Teki QUAD_OUTPUT_FAST = 1 << 4, 306dd6e90eSJagannadha Sutradharudu Teki QUAD_IO_FAST = 1 << 5, 31ff0960f9SSimon Glass }; 32ff0960f9SSimon Glass 336dd6e90eSJagannadha Sutradharudu Teki /* Normal - Extended - Full command set */ 346dd6e90eSJagannadha Sutradharudu Teki #define RD_NORM (ARRAY_SLOW | ARRAY_FAST) 356dd6e90eSJagannadha Sutradharudu Teki #define RD_EXTN (RD_NORM | DUAL_OUTPUT_FAST | DUAL_IO_FAST) 36ff0960f9SSimon Glass #define RD_FULL (RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST) 37ff0960f9SSimon Glass 38ff0960f9SSimon Glass /* sf param flags */ 39ff0960f9SSimon Glass enum { 40ff0960f9SSimon Glass SECT_4K = 1 << 0, 41ff0960f9SSimon Glass SECT_32K = 1 << 1, 42ff0960f9SSimon Glass E_FSR = 1 << 2, 4354ba653aSJagannadha Sutradharudu Teki SST_BP = 1 << 3, 44b648742aSSimon Glass SST_WP = 1 << 4, 4554ba653aSJagannadha Sutradharudu Teki WR_QPP = 1 << 5, 46ff0960f9SSimon Glass }; 47ff0960f9SSimon Glass 4854ba653aSJagannadha Sutradharudu Teki #define SST_WR (SST_BP | SST_WP) 4954ba653aSJagannadha Sutradharudu Teki 50ff063ed4SJagannadha Sutradharudu Teki #define SPI_FLASH_3B_ADDR_LEN 3 51ff063ed4SJagannadha Sutradharudu Teki #define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN) 52898e76c9SJagannadha Sutradharudu Teki #define SPI_FLASH_16MB_BOUN 0x1000000 53898e76c9SJagannadha Sutradharudu Teki 54d08a1bafSJagannadha Sutradharudu Teki /* CFI Manufacture ID's */ 55d08a1bafSJagannadha Sutradharudu Teki #define SPI_FLASH_CFI_MFR_SPANSION 0x01 56d08a1bafSJagannadha Sutradharudu Teki #define SPI_FLASH_CFI_MFR_STMICRO 0x20 5706795122SJagannadha Sutradharudu Teki #define SPI_FLASH_CFI_MFR_MACRONIX 0xc2 58d08a1bafSJagannadha Sutradharudu Teki #define SPI_FLASH_CFI_MFR_WINBOND 0xef 59d08a1bafSJagannadha Sutradharudu Teki 60898e76c9SJagannadha Sutradharudu Teki /* Erase commands */ 61898e76c9SJagannadha Sutradharudu Teki #define CMD_ERASE_4K 0x20 62898e76c9SJagannadha Sutradharudu Teki #define CMD_ERASE_32K 0x52 63898e76c9SJagannadha Sutradharudu Teki #define CMD_ERASE_CHIP 0xc7 64898e76c9SJagannadha Sutradharudu Teki #define CMD_ERASE_64K 0xd8 65898e76c9SJagannadha Sutradharudu Teki 66898e76c9SJagannadha Sutradharudu Teki /* Write commands */ 67898e76c9SJagannadha Sutradharudu Teki #define CMD_WRITE_STATUS 0x01 68898e76c9SJagannadha Sutradharudu Teki #define CMD_PAGE_PROGRAM 0x02 69898e76c9SJagannadha Sutradharudu Teki #define CMD_WRITE_DISABLE 0x04 70898e76c9SJagannadha Sutradharudu Teki #define CMD_READ_STATUS 0x05 713163aaa6SJagannadha Sutradharudu Teki #define CMD_QUAD_PAGE_PROGRAM 0x32 72ffdb20beSMike Frysinger #define CMD_READ_STATUS1 0x35 73898e76c9SJagannadha Sutradharudu Teki #define CMD_WRITE_ENABLE 0x06 74898e76c9SJagannadha Sutradharudu Teki #define CMD_READ_CONFIG 0x35 75898e76c9SJagannadha Sutradharudu Teki #define CMD_FLAG_STATUS 0x70 76898e76c9SJagannadha Sutradharudu Teki 77898e76c9SJagannadha Sutradharudu Teki /* Read commands */ 78898e76c9SJagannadha Sutradharudu Teki #define CMD_READ_ARRAY_SLOW 0x03 79898e76c9SJagannadha Sutradharudu Teki #define CMD_READ_ARRAY_FAST 0x0b 804e09cc1eSJagannadha Sutradharudu Teki #define CMD_READ_DUAL_OUTPUT_FAST 0x3b 814e09cc1eSJagannadha Sutradharudu Teki #define CMD_READ_DUAL_IO_FAST 0xbb 823163aaa6SJagannadha Sutradharudu Teki #define CMD_READ_QUAD_OUTPUT_FAST 0x6b 83c4ba0d82SJagannadha Sutradharudu Teki #define CMD_READ_QUAD_IO_FAST 0xeb 84898e76c9SJagannadha Sutradharudu Teki #define CMD_READ_ID 0x9f 85898e76c9SJagannadha Sutradharudu Teki 86898e76c9SJagannadha Sutradharudu Teki /* Bank addr access commands */ 87898e76c9SJagannadha Sutradharudu Teki #ifdef CONFIG_SPI_FLASH_BAR 88898e76c9SJagannadha Sutradharudu Teki # define CMD_BANKADDR_BRWR 0x17 89898e76c9SJagannadha Sutradharudu Teki # define CMD_BANKADDR_BRRD 0x16 90898e76c9SJagannadha Sutradharudu Teki # define CMD_EXTNADDR_WREAR 0xC5 91898e76c9SJagannadha Sutradharudu Teki # define CMD_EXTNADDR_RDEAR 0xC8 92898e76c9SJagannadha Sutradharudu Teki #endif 93898e76c9SJagannadha Sutradharudu Teki 94898e76c9SJagannadha Sutradharudu Teki /* Common status */ 952ba863faSJagannadha Sutradharudu Teki #define STATUS_WIP (1 << 0) 96d08a1bafSJagannadha Sutradharudu Teki #define STATUS_QEB_WINSPAN (1 << 1) 9706795122SJagannadha Sutradharudu Teki #define STATUS_QEB_MXIC (1 << 6) 982ba863faSJagannadha Sutradharudu Teki #define STATUS_PEC (1 << 7) 99898e76c9SJagannadha Sutradharudu Teki 100898e76c9SJagannadha Sutradharudu Teki /* Flash timeout values */ 101898e76c9SJagannadha Sutradharudu Teki #define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ) 102898e76c9SJagannadha Sutradharudu Teki #define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ) 103898e76c9SJagannadha Sutradharudu Teki #define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ) 104898e76c9SJagannadha Sutradharudu Teki 105898e76c9SJagannadha Sutradharudu Teki /* SST specific */ 106898e76c9SJagannadha Sutradharudu Teki #ifdef CONFIG_SPI_FLASH_SST 107898e76c9SJagannadha Sutradharudu Teki # define CMD_SST_BP 0x02 /* Byte Program */ 108898e76c9SJagannadha Sutradharudu Teki # define CMD_SST_AAI_WP 0xAD /* Auto Address Incr Word Program */ 109898e76c9SJagannadha Sutradharudu Teki 110898e76c9SJagannadha Sutradharudu Teki int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len, 111898e76c9SJagannadha Sutradharudu Teki const void *buf); 11274c2cee4SBin Meng int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len, 11374c2cee4SBin Meng const void *buf); 114898e76c9SJagannadha Sutradharudu Teki #endif 115898e76c9SJagannadha Sutradharudu Teki 116ff0960f9SSimon Glass /** 117ff0960f9SSimon Glass * struct spi_flash_params - SPI/QSPI flash device params structure 118ff0960f9SSimon Glass * 119ff0960f9SSimon Glass * @name: Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO]) 120ff0960f9SSimon Glass * @jedec: Device jedec ID (0x[1byte_manuf_id][2byte_dev_id]) 121ff0960f9SSimon Glass * @ext_jedec: Device ext_jedec ID 122*c650ca7bSJagannadha Sutradharudu Teki * @sector_size: Isn't necessarily a sector size from vendor, 123*c650ca7bSJagannadha Sutradharudu Teki * the size listed here is what works with CMD_ERASE_64K 124ff0960f9SSimon Glass * @nr_sectors: No.of sectors on this device 125ff0960f9SSimon Glass * @e_rd_cmd: Enum list for read commands 126ff0960f9SSimon Glass * @flags: Important param, for flash specific behaviour 127ff0960f9SSimon Glass */ 128ff0960f9SSimon Glass struct spi_flash_params { 129ff0960f9SSimon Glass const char *name; 130ff0960f9SSimon Glass u32 jedec; 131ff0960f9SSimon Glass u16 ext_jedec; 132ff0960f9SSimon Glass u32 sector_size; 133ff0960f9SSimon Glass u32 nr_sectors; 134ff0960f9SSimon Glass u8 e_rd_cmd; 135ff0960f9SSimon Glass u16 flags; 136ff0960f9SSimon Glass }; 137ff0960f9SSimon Glass 138ff0960f9SSimon Glass extern const struct spi_flash_params spi_flash_params_table[]; 139ff0960f9SSimon Glass 140898e76c9SJagannadha Sutradharudu Teki /* Send a single-byte command to the device and read the response */ 141898e76c9SJagannadha Sutradharudu Teki int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len); 142898e76c9SJagannadha Sutradharudu Teki 143898e76c9SJagannadha Sutradharudu Teki /* 144898e76c9SJagannadha Sutradharudu Teki * Send a multi-byte command to the device and read the response. Used 145898e76c9SJagannadha Sutradharudu Teki * for flash array reads, etc. 146898e76c9SJagannadha Sutradharudu Teki */ 147898e76c9SJagannadha Sutradharudu Teki int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd, 148898e76c9SJagannadha Sutradharudu Teki size_t cmd_len, void *data, size_t data_len); 149898e76c9SJagannadha Sutradharudu Teki 150898e76c9SJagannadha Sutradharudu Teki /* 151898e76c9SJagannadha Sutradharudu Teki * Send a multi-byte command to the device followed by (optional) 152898e76c9SJagannadha Sutradharudu Teki * data. Used for programming the flash array, etc. 153898e76c9SJagannadha Sutradharudu Teki */ 154898e76c9SJagannadha Sutradharudu Teki int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len, 155898e76c9SJagannadha Sutradharudu Teki const void *data, size_t data_len); 156898e76c9SJagannadha Sutradharudu Teki 157898e76c9SJagannadha Sutradharudu Teki 158898e76c9SJagannadha Sutradharudu Teki /* Flash erase(sectors) operation, support all possible erase commands */ 159898e76c9SJagannadha Sutradharudu Teki int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len); 160898e76c9SJagannadha Sutradharudu Teki 1619f4322fdSJagannadha Sutradharudu Teki /* Read the status register */ 1629f4322fdSJagannadha Sutradharudu Teki int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs); 1639f4322fdSJagannadha Sutradharudu Teki 164898e76c9SJagannadha Sutradharudu Teki /* Program the status register */ 1652ba863faSJagannadha Sutradharudu Teki int spi_flash_cmd_write_status(struct spi_flash *flash, u8 ws); 166898e76c9SJagannadha Sutradharudu Teki 1679f4322fdSJagannadha Sutradharudu Teki /* Read the config register */ 1689f4322fdSJagannadha Sutradharudu Teki int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc); 16906795122SJagannadha Sutradharudu Teki 1709f4322fdSJagannadha Sutradharudu Teki /* Program the config register */ 1719f4322fdSJagannadha Sutradharudu Teki int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc); 172898e76c9SJagannadha Sutradharudu Teki 173898e76c9SJagannadha Sutradharudu Teki /* Enable writing on the SPI flash */ 174898e76c9SJagannadha Sutradharudu Teki static inline int spi_flash_cmd_write_enable(struct spi_flash *flash) 175898e76c9SJagannadha Sutradharudu Teki { 176898e76c9SJagannadha Sutradharudu Teki return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0); 177898e76c9SJagannadha Sutradharudu Teki } 178898e76c9SJagannadha Sutradharudu Teki 179898e76c9SJagannadha Sutradharudu Teki /* Disable writing on the SPI flash */ 180898e76c9SJagannadha Sutradharudu Teki static inline int spi_flash_cmd_write_disable(struct spi_flash *flash) 181898e76c9SJagannadha Sutradharudu Teki { 182898e76c9SJagannadha Sutradharudu Teki return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0); 183898e76c9SJagannadha Sutradharudu Teki } 184898e76c9SJagannadha Sutradharudu Teki 185898e76c9SJagannadha Sutradharudu Teki /* 186898e76c9SJagannadha Sutradharudu Teki * Send the read status command to the device and wait for the wip 187898e76c9SJagannadha Sutradharudu Teki * (write-in-progress) bit to clear itself. 188898e76c9SJagannadha Sutradharudu Teki */ 189898e76c9SJagannadha Sutradharudu Teki int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout); 190898e76c9SJagannadha Sutradharudu Teki 191898e76c9SJagannadha Sutradharudu Teki /* 192898e76c9SJagannadha Sutradharudu Teki * Used for spi_flash write operation 193898e76c9SJagannadha Sutradharudu Teki * - SPI claim 194898e76c9SJagannadha Sutradharudu Teki * - spi_flash_cmd_write_enable 195898e76c9SJagannadha Sutradharudu Teki * - spi_flash_cmd_write 196898e76c9SJagannadha Sutradharudu Teki * - spi_flash_cmd_wait_ready 197898e76c9SJagannadha Sutradharudu Teki * - SPI release 198898e76c9SJagannadha Sutradharudu Teki */ 199898e76c9SJagannadha Sutradharudu Teki int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, 200898e76c9SJagannadha Sutradharudu Teki size_t cmd_len, const void *buf, size_t buf_len); 201898e76c9SJagannadha Sutradharudu Teki 202898e76c9SJagannadha Sutradharudu Teki /* 203898e76c9SJagannadha Sutradharudu Teki * Flash write operation, support all possible write commands. 204898e76c9SJagannadha Sutradharudu Teki * Write the requested data out breaking it up into multiple write 205898e76c9SJagannadha Sutradharudu Teki * commands as needed per the write size. 206898e76c9SJagannadha Sutradharudu Teki */ 207898e76c9SJagannadha Sutradharudu Teki int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, 208898e76c9SJagannadha Sutradharudu Teki size_t len, const void *buf); 209898e76c9SJagannadha Sutradharudu Teki 210898e76c9SJagannadha Sutradharudu Teki /* 211898e76c9SJagannadha Sutradharudu Teki * Same as spi_flash_cmd_read() except it also claims/releases the SPI 212898e76c9SJagannadha Sutradharudu Teki * bus. Used as common part of the ->read() operation. 213898e76c9SJagannadha Sutradharudu Teki */ 214898e76c9SJagannadha Sutradharudu Teki int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, 215898e76c9SJagannadha Sutradharudu Teki size_t cmd_len, void *data, size_t data_len); 216898e76c9SJagannadha Sutradharudu Teki 217898e76c9SJagannadha Sutradharudu Teki /* Flash read operation, support all possible read commands */ 218898e76c9SJagannadha Sutradharudu Teki int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, 219898e76c9SJagannadha Sutradharudu Teki size_t len, void *data); 220898e76c9SJagannadha Sutradharudu Teki 221469146c0SJagannadha Sutradharudu Teki #endif /* _SF_INTERNAL_H_ */ 222