1 /*
2 * Copyright (c) 2017 Yifeng Zhao <yifeng.zhao@rock-chips.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #include <common.h>
8 #include <dm.h>
9 #include <fdtdec.h>
10 #include <fdt_support.h>
11 #include <inttypes.h>
12 #include <nand.h>
13 #include <linux/io.h>
14 #include <linux/kernel.h>
15 #include <linux/mtd/mtd.h>
16 #include <linux/mtd/nand.h>
17 #include <linux/mtd/partitions.h>
18
19 DECLARE_GLOBAL_DATA_PTR;
20
21 #define NANDC_V9_NUM_BANKS 4
22 #define NANDC_V9_DEF_TIMEOUT 20000
23 #define NANDC_V9_READ 0
24 #define NANDC_V9_WRITE 1
25 #define NANDC_REG_V9_FMCTL 0x00
26 #define NANDC_REG_V9_FMWAIT 0x04
27 #define NANDC_REG_V9_FLCTL 0x10
28 #define NANDC_REG_V9_BCHCTL 0x20
29 #define NANDC_REG_V9_DMA_CFG 0x30
30 #define NANDC_REG_V9_DMA_BUF0 0x34
31 #define NANDC_REG_V9_DMA_BUF1 0x38
32 #define NANDC_REG_V9_DMA_ST 0x40
33 #define NANDC_REG_V9_VER 0x80
34 #define NANDC_REG_V9_INTEN 0x120
35 #define NANDC_REG_V9_INTCLR 0x124
36 #define NANDC_REG_V9_INTST 0x128
37 #define NANDC_REG_V9_BCHST 0x150
38 #define NANDC_REG_V9_SPARE0 0x200
39 #define NANDC_REG_V9_SPARE1 0x204
40 #define NANDC_REG_V9_RANDMZ 0x208
41 #define NANDC_REG_V9_BANK0 0x800
42 #define NANDC_REG_V9_SRAM0 0x1000
43 #define NANDC_REG_V9_SRAM_SIZE 0x400
44
45 #define NANDC_REG_V9_DATA 0x00
46 #define NANDC_REG_V9_ADDR 0x04
47 #define NANDC_REG_V9_CMD 0x08
48
49 /* FMCTL */
50 #define NANDC_V9_FM_WP BIT(8)
51 #define NANDC_V9_FM_CE_SEL_M 0xFF
52 #define NANDC_V9_FM_CE_SEL(x) (1 << (x))
53 #define NANDC_V9_FM_FREADY BIT(9)
54
55 /* FLCTL */
56 #define NANDC_V9_FL_RST BIT(0)
57 #define NANDC_V9_FL_DIR_S 0x1
58 #define NANDC_V9_FL_XFER_START BIT(2)
59 #define NANDC_V9_FL_XFER_EN BIT(3)
60 #define NANDC_V9_FL_ST_BUF_S 0x4
61 #define NANDC_V9_FL_XFER_COUNT BIT(5)
62 #define NANDC_V9_FL_ACORRECT BIT(10)
63 #define NANDC_V9_FL_XFER_READY BIT(20)
64
65 /* BCHCTL */
66 #define NAND_V9_BCH_MODE_S 25
67 #define NAND_V9_BCH_MODE_M 0x7
68
69 /* BCHST */
70 #define NANDC_V9_BCH0_ST_ERR BIT(2)
71 #define NANDC_V9_BCH1_ST_ERR BIT(18)
72 #define NANDC_V9_ECC_ERR_CNT0(x) (((x) & (0x7F << 3)) >> 3)
73 #define NANDC_V9_ECC_ERR_CNT1(x) (((x) & (0x7F << 19)) >> 19)
74
75 struct rk_nand {
76 void __iomem *regs;
77 u8 chipnr;
78 u8 id[5];
79 u8 *databuf;
80 struct udevice *dev;
81 struct mtd_info *mtd;
82 };
83
84 static struct rk_nand *g_rk_nand;
85 static u32 nand_page_size;
86 static u32 nand_page_num;
87 static u32 nand_block_num;
88
nandc_init(struct rk_nand * rknand)89 static void nandc_init(struct rk_nand *rknand)
90 {
91 writel(0, rknand->regs + NANDC_REG_V9_RANDMZ);
92 writel(0, rknand->regs + NANDC_REG_V9_DMA_CFG);
93 writel(0x02000001, rknand->regs + NANDC_REG_V9_BCHCTL);
94 writel(0x1081, rknand->regs + NANDC_REG_V9_FMWAIT);
95 }
96
rockchip_nand_wait_dev_ready(void __iomem * regs)97 static void rockchip_nand_wait_dev_ready(void __iomem *regs)
98 {
99 u32 reg;
100 u32 timeout = NANDC_V9_DEF_TIMEOUT;
101
102 while (timeout--) {
103 udelay(1);
104 reg = readl(regs + NANDC_REG_V9_FMCTL);
105
106 if (reg & NANDC_V9_FM_FREADY)
107 break;
108 }
109 }
110
rockchip_nand_select_chip(void __iomem * regs,int chipnr)111 static void rockchip_nand_select_chip(void __iomem *regs, int chipnr)
112 {
113 u32 reg;
114
115 reg = readl(regs + NANDC_REG_V9_FMCTL);
116 reg &= ~NANDC_V9_FM_CE_SEL_M;
117 if (chipnr != -1)
118 reg |= 1 << chipnr;
119 writel(reg, regs + NANDC_REG_V9_FMCTL);
120 }
121
rockchip_nand_read_page(void __iomem * regs,int page,int col)122 static void rockchip_nand_read_page(void __iomem *regs,
123 int page, int col)
124 {
125 void __iomem *bank_base = regs + NANDC_REG_V9_BANK0;
126
127 writeb(0x00, bank_base + NANDC_REG_V9_CMD);
128 writeb(col, bank_base + NANDC_REG_V9_ADDR);
129 writeb(col >> 8, bank_base + NANDC_REG_V9_ADDR);
130 writeb(page, bank_base + NANDC_REG_V9_ADDR);
131 writeb(page >> 8, bank_base + NANDC_REG_V9_ADDR);
132 writeb(page >> 16, bank_base + NANDC_REG_V9_ADDR);
133 writeb(0x30, bank_base + NANDC_REG_V9_CMD);
134 }
135
rockchip_nand_pio_xfer_start(struct rk_nand * rknand,u8 dir,u8 st_buf)136 static void rockchip_nand_pio_xfer_start(struct rk_nand *rknand,
137 u8 dir,
138 u8 st_buf)
139 {
140 u32 reg;
141
142 reg = (dir << NANDC_V9_FL_DIR_S) | (st_buf << NANDC_V9_FL_ST_BUF_S) |
143 NANDC_V9_FL_XFER_EN | NANDC_V9_FL_XFER_COUNT |
144 NANDC_V9_FL_ACORRECT;
145 writel(reg, rknand->regs + NANDC_REG_V9_FLCTL);
146
147 reg |= NANDC_V9_FL_XFER_START;
148 writel(reg, rknand->regs + NANDC_REG_V9_FLCTL);
149 }
150
rockchip_nand_wait_pio_xfer_done(struct rk_nand * rknand)151 static int rockchip_nand_wait_pio_xfer_done(struct rk_nand *rknand)
152 {
153 int timeout = NANDC_V9_DEF_TIMEOUT;
154 int reg;
155
156 while (timeout--) {
157 reg = readl(rknand->regs + NANDC_REG_V9_FLCTL);
158
159 if ((reg & NANDC_V9_FL_XFER_READY) != 0)
160 break;
161
162 udelay(1);
163 }
164
165 if (timeout == 0)
166 return -1;
167
168 return 0;
169 }
170
nandc_read_page(unsigned int page,uint8_t * buf)171 static int nandc_read_page(unsigned int page, uint8_t *buf)
172 {
173 void __iomem *sram_base = g_rk_nand->regs + NANDC_REG_V9_SRAM0;
174 unsigned int max_bitflips = 0;
175 int ret, step, bch_st, ecc_step;
176
177 ecc_step = nand_page_size / 1024;
178 rockchip_nand_select_chip(g_rk_nand->regs, 0);
179 rockchip_nand_read_page(g_rk_nand->regs, page, 0);
180 rockchip_nand_wait_dev_ready(g_rk_nand->regs);
181 rockchip_nand_pio_xfer_start(g_rk_nand, NANDC_V9_READ, 0);
182
183 for (step = 0; step < ecc_step; step++) {
184 int data_off = step * 1024;
185 u8 *data = buf + data_off;
186
187 ret = rockchip_nand_wait_pio_xfer_done(g_rk_nand);
188 if (ret)
189 return ret;
190
191 bch_st = readl(g_rk_nand->regs + NANDC_REG_V9_BCHST);
192
193 if (bch_st & NANDC_V9_BCH0_ST_ERR) {
194 max_bitflips = -1;
195 } else {
196 ret = NANDC_V9_ECC_ERR_CNT0(bch_st);
197 max_bitflips = max_t(unsigned int, max_bitflips, ret);
198 }
199
200 if ((step + 1) < ecc_step)
201 rockchip_nand_pio_xfer_start(g_rk_nand, NANDC_V9_READ,
202 (step + 1) & 0x1);
203
204 memcpy_fromio(data, sram_base + NANDC_REG_V9_SRAM_SIZE *
205 (step & 1), 1024);
206 }
207 rockchip_nand_select_chip(g_rk_nand->regs, -1);
208
209 return max_bitflips;
210 }
211
is_badblock(unsigned int page)212 static int is_badblock(unsigned int page)
213 {
214 int res = 0, i;
215 u16 bad = 0xff;
216 void __iomem *regs = g_rk_nand->regs;
217 void __iomem *bank_base = regs + NANDC_REG_V9_BANK0;
218
219 if (nandc_read_page(page, g_rk_nand->databuf) == -1) {
220 rockchip_nand_select_chip(regs, 0);
221 rockchip_nand_read_page(regs, page, nand_page_size);
222 rockchip_nand_wait_dev_ready(regs);
223 for (i = 0; i < 8; i++) {
224 bad = readb(bank_base);
225 if (bad)
226 break;
227 }
228 if (i >= 8)
229 res = 1;
230 rockchip_nand_select_chip(regs, 0);
231 }
232 if (res)
233 printf("%s 0x%x %x %x\n", __func__, page, res, bad);
234 return res;
235 }
236
read_flash_id(struct rk_nand * rknand,uint8_t * id)237 static void read_flash_id(struct rk_nand *rknand, uint8_t *id)
238 {
239 void __iomem *bank_base = rknand->regs + NANDC_REG_V9_BANK0;
240
241 rockchip_nand_wait_dev_ready(g_rk_nand->regs);
242 writeb(0x90, bank_base + NANDC_REG_V9_CMD);
243 writeb(0x00, bank_base + NANDC_REG_V9_ADDR);
244 udelay(1);
245 id[0] = readb(bank_base);
246 id[1] = readb(bank_base);
247 id[2] = readb(bank_base);
248 id[3] = readb(bank_base);
249 id[4] = readb(bank_base);
250 rockchip_nand_select_chip(rknand->regs, -1);
251 if (id[0] != 0xFF && id[0] != 0x00)
252 printf("NAND:%x %x\n", id[0], id[1]);
253 }
254
255 #ifdef CONFIG_NAND_ROCKCHIP_DT
256 static const struct udevice_id rockchip_nandc_ids[] = {
257 { .compatible = "rockchip,rk-nandc" },
258 { }
259 };
260
spl_nand_block_isbad(struct mtd_info * mtd,loff_t ofs)261 static int spl_nand_block_isbad(struct mtd_info *mtd, loff_t ofs)
262 {
263 return is_badblock((u32)ofs / nand_page_size);
264 }
265
spl_nand_read_page(struct mtd_info * mtd,loff_t from,size_t len,size_t * retlen,u_char * buf)266 static int spl_nand_read_page(struct mtd_info *mtd, loff_t from, size_t len,
267 size_t *retlen, u_char *buf)
268 {
269 int read_size, offset, read_len;
270 unsigned int page;
271 unsigned int max_pages = nand_page_num * nand_block_num;
272
273 /* Convert to page number */
274 page = (u32)from / nand_page_size;
275 offset = from & (nand_page_size - 1);
276 read_len = len;
277 *retlen = 0;
278
279 while (read_len) {
280 read_size = nand_page_size - offset;
281 if (read_size > read_len)
282 read_size = read_len;
283 if (offset || read_size < nand_page_size) {
284 if (nandc_read_page(page, g_rk_nand->databuf) < 0)
285 return -EIO;
286 memcpy(buf, g_rk_nand->databuf + offset, read_size);
287 offset = 0;
288 } else {
289 if (nandc_read_page(page, buf) < 0)
290 return -EIO;
291 }
292 page++;
293 read_len -= read_size;
294 buf += read_size;
295 if (page >= max_pages)
296 return -EIO;
297 }
298
299 *retlen = len;
300
301 return 0;
302 }
303
rockchip_nandc_probe(struct udevice * dev)304 static int rockchip_nandc_probe(struct udevice *dev)
305 {
306 const void *blob = gd->fdt_blob;
307 struct rk_nand *rknand = dev_get_priv(dev);
308 struct mtd_info *mtd = dev_get_uclass_priv(dev);
309 fdt_addr_t regs;
310 int ret = -ENODEV;
311 int node;
312 u8 *id;
313
314 g_rk_nand = rknand;
315 rknand->dev = dev;
316
317 node = fdtdec_next_compatible(blob, 0, COMPAT_ROCKCHIP_NANDC);
318
319 if (node < 0) {
320 printf("Nand node not found\n");
321 return -ENODEV;
322 }
323
324 if (!fdtdec_get_is_enabled(blob, node)) {
325 debug("Nand disabled in device tree\n");
326 return -ENODEV;
327 }
328
329 regs = fdt_get_base_address(blob, node);
330 if (!regs) {
331 debug("Nand address not found\n");
332 return -ENODEV;
333 }
334
335 rknand->regs = (void *)regs;
336
337 nandc_init(g_rk_nand);
338 read_flash_id(g_rk_nand, g_rk_nand->id);
339
340 id = g_rk_nand->id;
341 if (id[0] == id[1])
342 return -ENODEV;
343
344 if (id[1] == 0xA1 || id[1] == 0xF1 ||
345 id[1] == 0xD1 || id[1] == 0xAA ||
346 id[1] == 0xDA || id[1] == 0xAC ||
347 id[1] == 0xDC || id[1] == 0xA3 ||
348 id[1] == 0xD3 || id[1] == 0x95 ||
349 id[1] == 0x48 || id[1] == 0xD7 ||
350 id[1] == 0x63) {
351 nand_page_size = 2048;
352 nand_page_num = 64;
353 nand_block_num = 1024;
354 if (id[1] == 0xDC || id[1] == 0xAC) {
355 if ((id[0] == 0x2C && id[3] == 0xA6) ||
356 (id[0] == 0xC2 && id[3] == 0xA2) ||
357 (id[0] == 0x98 && id[3] == 0x26) ||
358 (id[0] == 0xCD && id[3] == 0xA2)) {
359 nand_page_size = 4096;
360 nand_block_num = 2048;
361 } else {
362 nand_block_num = 4096;
363 }
364 } else if (id[1] == 0xDA) {
365 nand_block_num = 2048;
366 } else if (id[1] == 0x48) {
367 nand_page_size = 4096;
368 nand_page_num = 128;
369 nand_block_num = 4096;
370 } else if (id[1] == 0xD3) {
371 if ((id[2] == 0xD1 && id[4] == 0x5a) || /* S34ML08G2 */
372 (id[3] == 0x05 && id[4] == 0x04)) { /* S34ML08G3 */
373 nand_block_num = 8192;
374 } else {
375 nand_page_size = 4096;
376 nand_block_num = 4096;
377 }
378 } else if (id[1] == 0xd7 && id[3] == 0x32) { /* TC58NVG5H2HTAI0 */
379 nand_page_size = 8192;
380 nand_page_num = 128;
381 nand_block_num = 4096;
382 } else if (id[1] == 0x63 && id[3] == 0x19) { /* IS34ML08G088 */
383 nand_page_size = 4096;
384 nand_page_num = 64;
385 nand_block_num = 4096;
386 }
387 g_rk_nand->chipnr = 1;
388 g_rk_nand->databuf = kzalloc(nand_page_size, GFP_KERNEL);
389 if (!g_rk_nand)
390 return -ENOMEM;
391 mtd->_block_isbad = spl_nand_block_isbad;
392 mtd->_read = spl_nand_read_page;
393 mtd->size = (size_t)nand_page_size * nand_page_num *
394 nand_block_num;
395 mtd->writesize = nand_page_size;
396 mtd->erasesize = nand_page_size * nand_page_num;
397 mtd->erasesize_shift = ffs(mtd->erasesize) - 1;
398 mtd->erasesize_mask = (1 << mtd->erasesize_shift) - 1;
399 mtd->type = MTD_NANDFLASH;
400 mtd->dev = rknand->dev;
401 mtd->priv = rknand;
402 add_mtd_device(mtd);
403 rknand->mtd = mtd;
404 ret = 0;
405 }
406
407 return ret;
408 }
409
rockchip_nandc_bind(struct udevice * udev)410 static int rockchip_nandc_bind(struct udevice *udev)
411 {
412 int ret = 0;
413
414 #ifdef CONFIG_MTD_BLK
415 struct udevice *bdev;
416
417 ret = blk_create_devicef(udev, "mtd_blk", "blk", IF_TYPE_MTD,
418 BLK_MTD_NAND, 512, 0, &bdev);
419 if (ret)
420 printf("Cannot create block device\n");
421 #endif
422 return ret;
423 }
424
425 U_BOOT_DRIVER(rk_nandc_v9) = {
426 .name = "rk_nandc_v9",
427 .id = UCLASS_MTD,
428 .of_match = rockchip_nandc_ids,
429 .bind = rockchip_nandc_bind,
430 .probe = rockchip_nandc_probe,
431 .priv_auto_alloc_size = sizeof(struct rk_nand),
432 };
433
board_nand_init(void)434 void board_nand_init(void)
435 {
436 struct udevice *dev;
437 int ret;
438
439 ret = uclass_get_device_by_driver(UCLASS_MTD,
440 DM_GET_DRIVER(rk_nandc_v9),
441 &dev);
442 if (ret && ret != -ENODEV)
443 pr_err("Failed to initialize NAND controller. (error %d)\n",
444 ret);
445 }
446
nand_spl_load_image(u32 offs,u32 size,void * buf)447 int nand_spl_load_image(u32 offs, u32 size, void *buf)
448 {
449 return -EIO;
450 }
451
nand_init(void)452 void nand_init(void){};
453
rk_nand_init(void)454 int rk_nand_init(void)
455 {
456 return -ENODEV;
457 }
458
459 #else
board_nand_init(void)460 void board_nand_init(void)
461 {
462 const void *blob = gd->fdt_blob;
463 static int initialized;
464 fdt_addr_t regs;
465 int node;
466
467 if (initialized)
468 return;
469
470 initialized = 1;
471 nand_page_size = CONFIG_SYS_NAND_PAGE_SIZE;
472 nand_page_num = CONFIG_SYS_NAND_PAGE_COUNT;
473
474 if (g_rk_nand)
475 return;
476
477 node = fdtdec_next_compatible(blob, 0, COMPAT_ROCKCHIP_NANDC);
478
479 if (node < 0) {
480 printf("Nand node not found\n");
481 return;
482 }
483
484 if (!fdtdec_get_is_enabled(blob, node)) {
485 debug("Nand disabled in device tree\n");
486 return;
487 }
488
489 regs = fdt_get_base_address(blob, node);
490 if (!regs) {
491 debug("Nand address not found\n");
492 return;
493 }
494
495 g_rk_nand = kzalloc(sizeof(*g_rk_nand), GFP_KERNEL);
496 g_rk_nand->regs = (void *)regs;
497 g_rk_nand->databuf = kzalloc(nand_page_size, GFP_KERNEL);
498 nandc_init(g_rk_nand);
499 read_flash_id(g_rk_nand, g_rk_nand->id);
500
501 if (g_rk_nand->id[0] == g_rk_nand->id[1])
502 goto err;
503
504 if (g_rk_nand->id[1] == 0xA1 || g_rk_nand->id[1] == 0xF1 ||
505 g_rk_nand->id[1] == 0xD1 || g_rk_nand->id[1] == 0xAA ||
506 g_rk_nand->id[1] == 0xDA || g_rk_nand->id[1] == 0xAC ||
507 g_rk_nand->id[1] == 0xDC || g_rk_nand->id[1] == 0xA3 ||
508 g_rk_nand->id[1] == 0xD3 || g_rk_nand->id[1] == 0x95 ||
509 g_rk_nand->id[1] == 0x48 || g_rk_nand->id[1] == 0xD7) {
510 g_rk_nand->chipnr = 1;
511 return;
512 }
513
514 err:
515 kfree(g_rk_nand->databuf);
516 kfree(g_rk_nand);
517 g_rk_nand = NULL;
518 }
519
nand_spl_load_image(u32 offs,u32 size,void * buf)520 int nand_spl_load_image(u32 offs, u32 size, void *buf)
521 {
522 int i;
523 unsigned int page;
524 int force_bad_block_check = 1;
525 unsigned int maxpages = CONFIG_SYS_NAND_SIZE /
526 nand_page_size;
527
528 /* Convert to page number */
529 page = offs / nand_page_size;
530 i = 0;
531
532 size = roundup(size, nand_page_size);
533 while (i < size / nand_page_size) {
534 /*
535 * Check if we have crossed a block boundary, and if so
536 * check for bad block.
537 */
538 if (force_bad_block_check || !(page % nand_page_num)) {
539 /*
540 * Yes, new block. See if this block is good. If not,
541 * loop until we find a good block.
542 */
543 while (is_badblock(page)) {
544 page = page + nand_page_num;
545 /* Check i we've reached the end of flash. */
546 if (page >= maxpages)
547 return -EIO;
548 }
549 }
550
551 force_bad_block_check = 0;
552
553 if (nandc_read_page(page, buf) < 0)
554 return -EIO;
555
556 page++;
557 i++;
558 buf = buf + nand_page_size;
559 }
560 return 0;
561 }
562
nand_init(void)563 void nand_init(void)
564 {
565 board_nand_init();
566 }
567
rk_nand_init(void)568 int rk_nand_init(void)
569 {
570 board_nand_init();
571 if (g_rk_nand && g_rk_nand->chipnr)
572 return 0;
573 else
574 return -ENODEV;
575 }
576 #endif
577
nand_deselect(void)578 void nand_deselect(void) {}
579
580