1 /* 2 * NAND driver for TI DaVinci based boards. 3 * 4 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 5 * 6 * Based on Linux DaVinci NAND driver by TI. Original copyright follows: 7 */ 8 9 /* 10 * 11 * linux/drivers/mtd/nand/raw/nand_davinci.c 12 * 13 * NAND Flash Driver 14 * 15 * Copyright (C) 2006 Texas Instruments. 16 * 17 * ---------------------------------------------------------------------------- 18 * 19 * SPDX-License-Identifier: GPL-2.0+ 20 * 21 * ---------------------------------------------------------------------------- 22 * 23 * Overview: 24 * This is a device driver for the NAND flash device found on the 25 * DaVinci board which utilizes the Samsung k9k2g08 part. 26 * 27 Modifications: 28 ver. 1.0: Feb 2005, Vinod/Sudhakar 29 - 30 */ 31 32 #include <common.h> 33 #include <asm/io.h> 34 #include <nand.h> 35 #include <asm/ti-common/davinci_nand.h> 36 37 /* Definitions for 4-bit hardware ECC */ 38 #define NAND_TIMEOUT 10240 39 #define NAND_ECC_BUSY 0xC 40 #define NAND_4BITECC_MASK 0x03FF03FF 41 #define EMIF_NANDFSR_ECC_STATE_MASK 0x00000F00 42 #define ECC_STATE_NO_ERR 0x0 43 #define ECC_STATE_TOO_MANY_ERRS 0x1 44 #define ECC_STATE_ERR_CORR_COMP_P 0x2 45 #define ECC_STATE_ERR_CORR_COMP_N 0x3 46 47 /* 48 * Exploit the little endianness of the ARM to do multi-byte transfers 49 * per device read. This can perform over twice as quickly as individual 50 * byte transfers when buffer alignment is conducive. 51 * 52 * NOTE: This only works if the NAND is not connected to the 2 LSBs of 53 * the address bus. On Davinci EVM platforms this has always been true. 54 */ 55 static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) 56 { 57 struct nand_chip *chip = mtd_to_nand(mtd); 58 const u32 *nand = chip->IO_ADDR_R; 59 60 /* Make sure that buf is 32 bit aligned */ 61 if (((int)buf & 0x3) != 0) { 62 if (((int)buf & 0x1) != 0) { 63 if (len) { 64 *buf = readb(nand); 65 buf += 1; 66 len--; 67 } 68 } 69 70 if (((int)buf & 0x3) != 0) { 71 if (len >= 2) { 72 *(u16 *)buf = readw(nand); 73 buf += 2; 74 len -= 2; 75 } 76 } 77 } 78 79 /* copy aligned data */ 80 while (len >= 4) { 81 *(u32 *)buf = __raw_readl(nand); 82 buf += 4; 83 len -= 4; 84 } 85 86 /* mop up any remaining bytes */ 87 if (len) { 88 if (len >= 2) { 89 *(u16 *)buf = readw(nand); 90 buf += 2; 91 len -= 2; 92 } 93 94 if (len) 95 *buf = readb(nand); 96 } 97 } 98 99 static void nand_davinci_write_buf(struct mtd_info *mtd, const uint8_t *buf, 100 int len) 101 { 102 struct nand_chip *chip = mtd_to_nand(mtd); 103 const u32 *nand = chip->IO_ADDR_W; 104 105 /* Make sure that buf is 32 bit aligned */ 106 if (((int)buf & 0x3) != 0) { 107 if (((int)buf & 0x1) != 0) { 108 if (len) { 109 writeb(*buf, nand); 110 buf += 1; 111 len--; 112 } 113 } 114 115 if (((int)buf & 0x3) != 0) { 116 if (len >= 2) { 117 writew(*(u16 *)buf, nand); 118 buf += 2; 119 len -= 2; 120 } 121 } 122 } 123 124 /* copy aligned data */ 125 while (len >= 4) { 126 __raw_writel(*(u32 *)buf, nand); 127 buf += 4; 128 len -= 4; 129 } 130 131 /* mop up any remaining bytes */ 132 if (len) { 133 if (len >= 2) { 134 writew(*(u16 *)buf, nand); 135 buf += 2; 136 len -= 2; 137 } 138 139 if (len) 140 writeb(*buf, nand); 141 } 142 } 143 144 static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, 145 unsigned int ctrl) 146 { 147 struct nand_chip *this = mtd_to_nand(mtd); 148 u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W; 149 150 if (ctrl & NAND_CTRL_CHANGE) { 151 IO_ADDR_W &= ~(MASK_ALE|MASK_CLE); 152 153 if (ctrl & NAND_CLE) 154 IO_ADDR_W |= MASK_CLE; 155 if (ctrl & NAND_ALE) 156 IO_ADDR_W |= MASK_ALE; 157 this->IO_ADDR_W = (void __iomem *) IO_ADDR_W; 158 } 159 160 if (cmd != NAND_CMD_NONE) 161 writeb(cmd, IO_ADDR_W); 162 } 163 164 #ifdef CONFIG_SYS_NAND_HW_ECC 165 166 static u_int32_t nand_davinci_readecc(struct mtd_info *mtd) 167 { 168 u_int32_t ecc = 0; 169 170 ecc = __raw_readl(&(davinci_emif_regs->nandfecc[ 171 CONFIG_SYS_NAND_CS - 2])); 172 173 return ecc; 174 } 175 176 static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode) 177 { 178 u_int32_t val; 179 180 /* reading the ECC result register resets the ECC calculation */ 181 nand_davinci_readecc(mtd); 182 183 val = __raw_readl(&davinci_emif_regs->nandfcr); 184 val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS); 185 val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS); 186 __raw_writel(val, &davinci_emif_regs->nandfcr); 187 } 188 189 static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, 190 u_char *ecc_code) 191 { 192 u_int32_t tmp; 193 194 tmp = nand_davinci_readecc(mtd); 195 196 /* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits 197 * and shifting. RESERVED bits are 31 to 28 and 15 to 12. */ 198 tmp = (tmp & 0x00000fff) | ((tmp & 0x0fff0000) >> 4); 199 200 /* Invert so that erased block ECC is correct */ 201 tmp = ~tmp; 202 203 *ecc_code++ = tmp; 204 *ecc_code++ = tmp >> 8; 205 *ecc_code++ = tmp >> 16; 206 207 /* NOTE: the above code matches mainline Linux: 208 * .PQR.stu ==> ~PQRstu 209 * 210 * MontaVista/TI kernels encode those bytes differently, use 211 * complicated (and allegedly sometimes-wrong) correction code, 212 * and usually shipped with U-Boot that uses software ECC: 213 * .PQR.stu ==> PsQRtu 214 * 215 * If you need MV/TI compatible NAND I/O in U-Boot, it should 216 * be possible to (a) change the mangling above, (b) reverse 217 * that mangling in nand_davinci_correct_data() below. 218 */ 219 220 return 0; 221 } 222 223 static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, 224 u_char *read_ecc, u_char *calc_ecc) 225 { 226 struct nand_chip *this = mtd_to_nand(mtd); 227 u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) | 228 (read_ecc[2] << 16); 229 u_int32_t ecc_calc = calc_ecc[0] | (calc_ecc[1] << 8) | 230 (calc_ecc[2] << 16); 231 u_int32_t diff = ecc_calc ^ ecc_nand; 232 233 if (diff) { 234 if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) { 235 /* Correctable error */ 236 if ((diff >> (12 + 3)) < this->ecc.size) { 237 uint8_t find_bit = 1 << ((diff >> 12) & 7); 238 uint32_t find_byte = diff >> (12 + 3); 239 240 dat[find_byte] ^= find_bit; 241 pr_debug("Correcting single " 242 "bit ECC error at offset: %d, bit: " 243 "%d\n", find_byte, find_bit); 244 return 1; 245 } else { 246 return -EBADMSG; 247 } 248 } else if (!(diff & (diff - 1))) { 249 /* Single bit ECC error in the ECC itself, 250 nothing to fix */ 251 pr_debug("Single bit ECC error in " "ECC.\n"); 252 return 1; 253 } else { 254 /* Uncorrectable error */ 255 pr_debug("ECC UNCORRECTED_ERROR 1\n"); 256 return -EBADMSG; 257 } 258 } 259 return 0; 260 } 261 #endif /* CONFIG_SYS_NAND_HW_ECC */ 262 263 #ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST 264 static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = { 265 #if defined(CONFIG_SYS_NAND_PAGE_2K) 266 .eccbytes = 40, 267 #ifdef CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC 268 .eccpos = { 269 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 270 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 271 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 272 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 273 }, 274 .oobfree = { 275 {2, 4}, {16, 6}, {32, 6}, {48, 6}, 276 }, 277 #else 278 .eccpos = { 279 24, 25, 26, 27, 28, 280 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 281 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 282 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 283 59, 60, 61, 62, 63, 284 }, 285 .oobfree = { 286 {.offset = 2, .length = 22, }, 287 }, 288 #endif /* #ifdef CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC */ 289 #elif defined(CONFIG_SYS_NAND_PAGE_4K) 290 .eccbytes = 80, 291 .eccpos = { 292 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 293 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 294 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 295 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 296 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 297 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 298 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 299 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 300 }, 301 .oobfree = { 302 {.offset = 2, .length = 46, }, 303 }, 304 #endif 305 }; 306 307 #if defined CONFIG_KEYSTONE_RBL_NAND 308 static struct nand_ecclayout nand_keystone_rbl_4bit_layout_oobfirst = { 309 #if defined(CONFIG_SYS_NAND_PAGE_2K) 310 .eccbytes = 40, 311 .eccpos = { 312 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 313 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 314 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 315 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 316 }, 317 .oobfree = { 318 {.offset = 2, .length = 4, }, 319 {.offset = 16, .length = 6, }, 320 {.offset = 32, .length = 6, }, 321 {.offset = 48, .length = 6, }, 322 }, 323 #elif defined(CONFIG_SYS_NAND_PAGE_4K) 324 .eccbytes = 80, 325 .eccpos = { 326 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 327 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 328 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 329 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 330 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 331 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 332 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 333 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 334 }, 335 .oobfree = { 336 {.offset = 2, .length = 4, }, 337 {.offset = 16, .length = 6, }, 338 {.offset = 32, .length = 6, }, 339 {.offset = 48, .length = 6, }, 340 {.offset = 64, .length = 6, }, 341 {.offset = 80, .length = 6, }, 342 {.offset = 96, .length = 6, }, 343 {.offset = 112, .length = 6, }, 344 }, 345 #endif 346 }; 347 348 #ifdef CONFIG_SYS_NAND_PAGE_2K 349 #define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 11 350 #elif defined(CONFIG_SYS_NAND_PAGE_4K) 351 #define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 12 352 #endif 353 354 /** 355 * nand_davinci_write_page - write one page 356 * @mtd: MTD device structure 357 * @chip: NAND chip descriptor 358 * @buf: the data to write 359 * @oob_required: must write chip->oob_poi to OOB 360 * @page: page number to write 361 * @raw: use _raw version of write_page 362 */ 363 static int nand_davinci_write_page(struct mtd_info *mtd, struct nand_chip *chip, 364 uint32_t offset, int data_len, 365 const uint8_t *buf, int oob_required, 366 int page, int raw) 367 { 368 int status; 369 int ret = 0; 370 struct nand_ecclayout *saved_ecc_layout; 371 372 /* save current ECC layout and assign Keystone RBL ECC layout */ 373 if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) { 374 saved_ecc_layout = chip->ecc.layout; 375 chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst; 376 mtd->oobavail = chip->ecc.layout->oobavail; 377 } 378 379 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page); 380 381 if (unlikely(raw)) { 382 status = chip->ecc.write_page_raw(mtd, chip, buf, 383 oob_required, page); 384 } else { 385 status = chip->ecc.write_page(mtd, chip, buf, 386 oob_required, page); 387 } 388 389 if (status < 0) { 390 ret = status; 391 goto err; 392 } 393 394 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); 395 status = chip->waitfunc(mtd, chip); 396 397 if (status & NAND_STATUS_FAIL) { 398 ret = -EIO; 399 goto err; 400 } 401 402 err: 403 /* restore ECC layout */ 404 if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) { 405 chip->ecc.layout = saved_ecc_layout; 406 mtd->oobavail = saved_ecc_layout->oobavail; 407 } 408 409 return ret; 410 } 411 412 /** 413 * nand_davinci_read_page_hwecc - hardware ECC based page read function 414 * @mtd: mtd info structure 415 * @chip: nand chip info structure 416 * @buf: buffer to store read data 417 * @oob_required: caller requires OOB data read to chip->oob_poi 418 * @page: page number to read 419 * 420 * Not for syndrome calculating ECC controllers which need a special oob layout. 421 */ 422 static int nand_davinci_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, 423 uint8_t *buf, int oob_required, int page) 424 { 425 int i, eccsize = chip->ecc.size; 426 int eccbytes = chip->ecc.bytes; 427 int eccsteps = chip->ecc.steps; 428 uint32_t *eccpos; 429 uint8_t *p = buf; 430 uint8_t *ecc_code = chip->buffers->ecccode; 431 uint8_t *ecc_calc = chip->buffers->ecccalc; 432 struct nand_ecclayout *saved_ecc_layout = chip->ecc.layout; 433 434 /* save current ECC layout and assign Keystone RBL ECC layout */ 435 if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) { 436 chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst; 437 mtd->oobavail = chip->ecc.layout->oobavail; 438 } 439 440 eccpos = chip->ecc.layout->eccpos; 441 442 /* Read the OOB area first */ 443 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); 444 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); 445 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); 446 447 for (i = 0; i < chip->ecc.total; i++) 448 ecc_code[i] = chip->oob_poi[eccpos[i]]; 449 450 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 451 int stat; 452 453 chip->ecc.hwctl(mtd, NAND_ECC_READ); 454 chip->read_buf(mtd, p, eccsize); 455 chip->ecc.calculate(mtd, p, &ecc_calc[i]); 456 457 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL); 458 if (stat < 0) 459 mtd->ecc_stats.failed++; 460 else 461 mtd->ecc_stats.corrected += stat; 462 } 463 464 /* restore ECC layout */ 465 if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) { 466 chip->ecc.layout = saved_ecc_layout; 467 mtd->oobavail = saved_ecc_layout->oobavail; 468 } 469 470 return 0; 471 } 472 #endif /* CONFIG_KEYSTONE_RBL_NAND */ 473 474 static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode) 475 { 476 u32 val; 477 478 switch (mode) { 479 case NAND_ECC_WRITE: 480 case NAND_ECC_READ: 481 /* 482 * Start a new ECC calculation for reading or writing 512 bytes 483 * of data. 484 */ 485 val = __raw_readl(&davinci_emif_regs->nandfcr); 486 val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK; 487 val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS); 488 val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS); 489 val |= DAVINCI_NANDFCR_4BIT_ECC_START; 490 __raw_writel(val, &davinci_emif_regs->nandfcr); 491 break; 492 case NAND_ECC_READSYN: 493 val = __raw_readl(&davinci_emif_regs->nand4bitecc[0]); 494 break; 495 default: 496 break; 497 } 498 } 499 500 static u32 nand_davinci_4bit_readecc(struct mtd_info *mtd, unsigned int ecc[4]) 501 { 502 int i; 503 504 for (i = 0; i < 4; i++) { 505 ecc[i] = __raw_readl(&davinci_emif_regs->nand4bitecc[i]) & 506 NAND_4BITECC_MASK; 507 } 508 509 return 0; 510 } 511 512 static int nand_davinci_4bit_calculate_ecc(struct mtd_info *mtd, 513 const uint8_t *dat, 514 uint8_t *ecc_code) 515 { 516 unsigned int hw_4ecc[4]; 517 unsigned int i; 518 519 nand_davinci_4bit_readecc(mtd, hw_4ecc); 520 521 /*Convert 10 bit ecc value to 8 bit */ 522 for (i = 0; i < 2; i++) { 523 unsigned int hw_ecc_low = hw_4ecc[i * 2]; 524 unsigned int hw_ecc_hi = hw_4ecc[(i * 2) + 1]; 525 526 /* Take first 8 bits from val1 (count1=0) or val5 (count1=1) */ 527 *ecc_code++ = hw_ecc_low & 0xFF; 528 529 /* 530 * Take 2 bits as LSB bits from val1 (count1=0) or val5 531 * (count1=1) and 6 bits from val2 (count1=0) or 532 * val5 (count1=1) 533 */ 534 *ecc_code++ = 535 ((hw_ecc_low >> 8) & 0x3) | ((hw_ecc_low >> 14) & 0xFC); 536 537 /* 538 * Take 4 bits from val2 (count1=0) or val5 (count1=1) and 539 * 4 bits from val3 (count1=0) or val6 (count1=1) 540 */ 541 *ecc_code++ = 542 ((hw_ecc_low >> 22) & 0xF) | ((hw_ecc_hi << 4) & 0xF0); 543 544 /* 545 * Take 6 bits from val3(count1=0) or val6 (count1=1) and 546 * 2 bits from val4 (count1=0) or val7 (count1=1) 547 */ 548 *ecc_code++ = 549 ((hw_ecc_hi >> 4) & 0x3F) | ((hw_ecc_hi >> 10) & 0xC0); 550 551 /* Take 8 bits from val4 (count1=0) or val7 (count1=1) */ 552 *ecc_code++ = (hw_ecc_hi >> 18) & 0xFF; 553 } 554 555 return 0; 556 } 557 558 static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat, 559 uint8_t *read_ecc, uint8_t *calc_ecc) 560 { 561 int i; 562 unsigned int hw_4ecc[4]; 563 unsigned int iserror; 564 unsigned short *ecc16; 565 unsigned int numerrors, erroraddress, errorvalue; 566 u32 val; 567 568 /* 569 * Check for an ECC where all bytes are 0xFF. If this is the case, we 570 * will assume we are looking at an erased page and we should ignore 571 * the ECC. 572 */ 573 for (i = 0; i < 10; i++) { 574 if (read_ecc[i] != 0xFF) 575 break; 576 } 577 if (i == 10) 578 return 0; 579 580 /* Convert 8 bit in to 10 bit */ 581 ecc16 = (unsigned short *)&read_ecc[0]; 582 583 /* 584 * Write the parity values in the NAND Flash 4-bit ECC Load register. 585 * Write each parity value one at a time starting from 4bit_ecc_val8 586 * to 4bit_ecc_val1. 587 */ 588 589 /*Take 2 bits from 8th byte and 8 bits from 9th byte */ 590 __raw_writel(((ecc16[4]) >> 6) & 0x3FF, 591 &davinci_emif_regs->nand4biteccload); 592 593 /* Take 4 bits from 7th byte and 6 bits from 8th byte */ 594 __raw_writel((((ecc16[3]) >> 12) & 0xF) | ((((ecc16[4])) << 4) & 0x3F0), 595 &davinci_emif_regs->nand4biteccload); 596 597 /* Take 6 bits from 6th byte and 4 bits from 7th byte */ 598 __raw_writel((ecc16[3] >> 2) & 0x3FF, 599 &davinci_emif_regs->nand4biteccload); 600 601 /* Take 8 bits from 5th byte and 2 bits from 6th byte */ 602 __raw_writel(((ecc16[2]) >> 8) | ((((ecc16[3])) << 8) & 0x300), 603 &davinci_emif_regs->nand4biteccload); 604 605 /*Take 2 bits from 3rd byte and 8 bits from 4th byte */ 606 __raw_writel((((ecc16[1]) >> 14) & 0x3) | ((((ecc16[2])) << 2) & 0x3FC), 607 &davinci_emif_regs->nand4biteccload); 608 609 /* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */ 610 __raw_writel(((ecc16[1]) >> 4) & 0x3FF, 611 &davinci_emif_regs->nand4biteccload); 612 613 /* Take 6 bits from 1st byte and 4 bits from 2nd byte */ 614 __raw_writel((((ecc16[0]) >> 10) & 0x3F) | (((ecc16[1]) << 6) & 0x3C0), 615 &davinci_emif_regs->nand4biteccload); 616 617 /* Take 10 bits from 0th and 1st bytes */ 618 __raw_writel((ecc16[0]) & 0x3FF, 619 &davinci_emif_regs->nand4biteccload); 620 621 /* 622 * Perform a dummy read to the EMIF Revision Code and Status register. 623 * This is required to ensure time for syndrome calculation after 624 * writing the ECC values in previous step. 625 */ 626 627 val = __raw_readl(&davinci_emif_regs->nandfsr); 628 629 /* 630 * Read the syndrome from the NAND Flash 4-Bit ECC 1-4 registers. 631 * A syndrome value of 0 means no bit errors. If the syndrome is 632 * non-zero then go further otherwise return. 633 */ 634 nand_davinci_4bit_readecc(mtd, hw_4ecc); 635 636 if (!(hw_4ecc[0] | hw_4ecc[1] | hw_4ecc[2] | hw_4ecc[3])) 637 return 0; 638 639 /* 640 * Clear any previous address calculation by doing a dummy read of an 641 * error address register. 642 */ 643 val = __raw_readl(&davinci_emif_regs->nanderradd1); 644 645 /* 646 * Set the addr_calc_st bit(bit no 13) in the NAND Flash Control 647 * register to 1. 648 */ 649 __raw_writel(DAVINCI_NANDFCR_4BIT_CALC_START, 650 &davinci_emif_regs->nandfcr); 651 652 /* 653 * Wait for the corr_state field (bits 8 to 11) in the 654 * NAND Flash Status register to be not equal to 0x0, 0x1, 0x2, or 0x3. 655 * Otherwise ECC calculation has not even begun and the next loop might 656 * fail because of a false positive! 657 */ 658 i = NAND_TIMEOUT; 659 do { 660 val = __raw_readl(&davinci_emif_regs->nandfsr); 661 val &= 0xc00; 662 i--; 663 } while ((i > 0) && !val); 664 665 /* 666 * Wait for the corr_state field (bits 8 to 11) in the 667 * NAND Flash Status register to be equal to 0x0, 0x1, 0x2, or 0x3. 668 */ 669 i = NAND_TIMEOUT; 670 do { 671 val = __raw_readl(&davinci_emif_regs->nandfsr); 672 val &= 0xc00; 673 i--; 674 } while ((i > 0) && val); 675 676 iserror = __raw_readl(&davinci_emif_regs->nandfsr); 677 iserror &= EMIF_NANDFSR_ECC_STATE_MASK; 678 iserror = iserror >> 8; 679 680 /* 681 * ECC_STATE_TOO_MANY_ERRS (0x1) means errors cannot be 682 * corrected (five or more errors). The number of errors 683 * calculated (err_num field) differs from the number of errors 684 * searched. ECC_STATE_ERR_CORR_COMP_P (0x2) means error 685 * correction complete (errors on bit 8 or 9). 686 * ECC_STATE_ERR_CORR_COMP_N (0x3) means error correction 687 * complete (error exists). 688 */ 689 690 if (iserror == ECC_STATE_NO_ERR) { 691 val = __raw_readl(&davinci_emif_regs->nanderrval1); 692 return 0; 693 } else if (iserror == ECC_STATE_TOO_MANY_ERRS) { 694 val = __raw_readl(&davinci_emif_regs->nanderrval1); 695 return -EBADMSG; 696 } 697 698 numerrors = ((__raw_readl(&davinci_emif_regs->nandfsr) >> 16) 699 & 0x3) + 1; 700 701 /* Read the error address, error value and correct */ 702 for (i = 0; i < numerrors; i++) { 703 if (i > 1) { 704 erroraddress = 705 ((__raw_readl(&davinci_emif_regs->nanderradd2) >> 706 (16 * (i & 1))) & 0x3FF); 707 erroraddress = ((512 + 7) - erroraddress); 708 errorvalue = 709 ((__raw_readl(&davinci_emif_regs->nanderrval2) >> 710 (16 * (i & 1))) & 0xFF); 711 } else { 712 erroraddress = 713 ((__raw_readl(&davinci_emif_regs->nanderradd1) >> 714 (16 * (i & 1))) & 0x3FF); 715 erroraddress = ((512 + 7) - erroraddress); 716 errorvalue = 717 ((__raw_readl(&davinci_emif_regs->nanderrval1) >> 718 (16 * (i & 1))) & 0xFF); 719 } 720 /* xor the corrupt data with error value */ 721 if (erroraddress < 512) 722 dat[erroraddress] ^= errorvalue; 723 } 724 725 return numerrors; 726 } 727 #endif /* CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST */ 728 729 static int nand_davinci_dev_ready(struct mtd_info *mtd) 730 { 731 return __raw_readl(&davinci_emif_regs->nandfsr) & 0x1; 732 } 733 734 void davinci_nand_init(struct nand_chip *nand) 735 { 736 #if defined CONFIG_KEYSTONE_RBL_NAND 737 int i; 738 struct nand_ecclayout *layout; 739 740 layout = &nand_keystone_rbl_4bit_layout_oobfirst; 741 layout->oobavail = 0; 742 for (i = 0; layout->oobfree[i].length && 743 i < ARRAY_SIZE(layout->oobfree); i++) 744 layout->oobavail += layout->oobfree[i].length; 745 746 nand->write_page = nand_davinci_write_page; 747 nand->ecc.read_page = nand_davinci_read_page_hwecc; 748 #endif 749 nand->chip_delay = 0; 750 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT 751 nand->bbt_options |= NAND_BBT_USE_FLASH; 752 #endif 753 #ifdef CONFIG_SYS_NAND_NO_SUBPAGE_WRITE 754 nand->options |= NAND_NO_SUBPAGE_WRITE; 755 #endif 756 #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT 757 nand->options |= NAND_BUSWIDTH_16; 758 #endif 759 #ifdef CONFIG_SYS_NAND_HW_ECC 760 nand->ecc.mode = NAND_ECC_HW; 761 nand->ecc.size = 512; 762 nand->ecc.bytes = 3; 763 nand->ecc.strength = 1; 764 nand->ecc.calculate = nand_davinci_calculate_ecc; 765 nand->ecc.correct = nand_davinci_correct_data; 766 nand->ecc.hwctl = nand_davinci_enable_hwecc; 767 #else 768 nand->ecc.mode = NAND_ECC_SOFT; 769 #endif /* CONFIG_SYS_NAND_HW_ECC */ 770 #ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST 771 nand->ecc.mode = NAND_ECC_HW_OOB_FIRST; 772 nand->ecc.size = 512; 773 nand->ecc.bytes = 10; 774 nand->ecc.strength = 4; 775 nand->ecc.calculate = nand_davinci_4bit_calculate_ecc; 776 nand->ecc.correct = nand_davinci_4bit_correct_data; 777 nand->ecc.hwctl = nand_davinci_4bit_enable_hwecc; 778 nand->ecc.layout = &nand_davinci_4bit_layout_oobfirst; 779 #endif 780 /* Set address of hardware control function */ 781 nand->cmd_ctrl = nand_davinci_hwcontrol; 782 783 nand->read_buf = nand_davinci_read_buf; 784 nand->write_buf = nand_davinci_write_buf; 785 786 nand->dev_ready = nand_davinci_dev_ready; 787 } 788 789 int board_nand_init(struct nand_chip *chip) __attribute__((weak)); 790 791 int board_nand_init(struct nand_chip *chip) 792 { 793 davinci_nand_init(chip); 794 return 0; 795 } 796