1 /* 2 * Arasan NAND Flash Controller Driver 3 * 4 * Copyright (C) 2014 - 2015 Xilinx, Inc. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <malloc.h> 11 #include <asm/io.h> 12 #include <linux/errno.h> 13 #include <linux/mtd/mtd.h> 14 #include <linux/mtd/rawnand.h> 15 #include <linux/mtd/partitions.h> 16 #include <linux/mtd/nand_ecc.h> 17 #include <asm/arch/hardware.h> 18 #include <asm/arch/sys_proto.h> 19 #include <nand.h> 20 21 struct arasan_nand_info { 22 void __iomem *nand_base; 23 u32 page; 24 bool on_die_ecc_enabled; 25 }; 26 27 struct nand_regs { 28 u32 pkt_reg; 29 u32 memadr_reg1; 30 u32 memadr_reg2; 31 u32 cmd_reg; 32 u32 pgm_reg; 33 u32 intsts_enr; 34 u32 intsig_enr; 35 u32 intsts_reg; 36 u32 rdy_busy; 37 u32 cms_sysadr_reg; 38 u32 flash_sts_reg; 39 u32 tmg_reg; 40 u32 buf_dataport; 41 u32 ecc_reg; 42 u32 ecc_errcnt_reg; 43 u32 ecc_sprcmd_reg; 44 u32 errcnt_1bitreg; 45 u32 errcnt_2bitreg; 46 u32 errcnt_3bitreg; 47 u32 errcnt_4bitreg; 48 u32 dma_sysadr0_reg; 49 u32 dma_bufbdry_reg; 50 u32 cpu_rls_reg; 51 u32 errcnt_5bitreg; 52 u32 errcnt_6bitreg; 53 u32 errcnt_7bitreg; 54 u32 errcnt_8bitreg; 55 u32 data_if_reg; 56 }; 57 58 #define arasan_nand_base ((struct nand_regs __iomem *)ARASAN_NAND_BASEADDR) 59 60 struct arasan_nand_command_format { 61 u8 cmd1; 62 u8 cmd2; 63 u8 addr_cycles; 64 u32 pgm; 65 }; 66 67 #define ONDIE_ECC_FEATURE_ADDR 0x90 68 #define ENABLE_ONDIE_ECC 0x08 69 70 #define ARASAN_PROG_RD_MASK 0x00000001 71 #define ARASAN_PROG_BLK_ERS_MASK 0x00000004 72 #define ARASAN_PROG_RD_ID_MASK 0x00000040 73 #define ARASAN_PROG_RD_STS_MASK 0x00000008 74 #define ARASAN_PROG_PG_PROG_MASK 0x00000010 75 #define ARASAN_PROG_RD_PARAM_PG_MASK 0x00000080 76 #define ARASAN_PROG_RST_MASK 0x00000100 77 #define ARASAN_PROG_GET_FTRS_MASK 0x00000200 78 #define ARASAN_PROG_SET_FTRS_MASK 0x00000400 79 #define ARASAN_PROG_CHNG_ROWADR_END_MASK 0x00400000 80 81 #define ARASAN_NAND_CMD_ECC_ON_MASK 0x80000000 82 #define ARASAN_NAND_CMD_CMD12_MASK 0xFFFF 83 #define ARASAN_NAND_CMD_PG_SIZE_MASK 0x3800000 84 #define ARASAN_NAND_CMD_PG_SIZE_SHIFT 23 85 #define ARASAN_NAND_CMD_CMD2_SHIFT 8 86 #define ARASAN_NAND_CMD_ADDR_CYCL_MASK 0x70000000 87 #define ARASAN_NAND_CMD_ADDR_CYCL_SHIFT 28 88 89 #define ARASAN_NAND_MEM_ADDR1_PAGE_MASK 0xFFFF0000 90 #define ARASAN_NAND_MEM_ADDR1_COL_MASK 0xFFFF 91 #define ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT 16 92 #define ARASAN_NAND_MEM_ADDR2_PAGE_MASK 0xFF 93 #define ARASAN_NAND_MEM_ADDR2_CS_MASK 0xC0000000 94 #define ARASAN_NAND_MEM_ADDR2_CS0_MASK (0x3 << 30) 95 #define ARASAN_NAND_MEM_ADDR2_CS1_MASK (0x1 << 30) 96 #define ARASAN_NAND_MEM_ADDR2_BCH_MASK 0xE000000 97 #define ARASAN_NAND_MEM_ADDR2_BCH_SHIFT 25 98 99 #define ARASAN_NAND_INT_STS_ERR_EN_MASK 0x10 100 #define ARASAN_NAND_INT_STS_MUL_BIT_ERR_MASK 0x08 101 #define ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK 0x02 102 #define ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK 0x01 103 #define ARASAN_NAND_INT_STS_XFR_CMPLT_MASK 0x04 104 105 #define ARASAN_NAND_PKT_REG_PKT_CNT_MASK 0xFFF000 106 #define ARASAN_NAND_PKT_REG_PKT_SIZE_MASK 0x7FF 107 #define ARASAN_NAND_PKT_REG_PKT_CNT_SHFT 12 108 109 #define ARASAN_NAND_ROW_ADDR_CYCL_MASK 0x0F 110 #define ARASAN_NAND_COL_ADDR_CYCL_MASK 0xF0 111 #define ARASAN_NAND_COL_ADDR_CYCL_SHIFT 4 112 113 #define ARASAN_NAND_ECC_SIZE_SHIFT 16 114 #define ARASAN_NAND_ECC_BCH_SHIFT 27 115 116 #define ARASAN_NAND_PKTSIZE_1K 1024 117 #define ARASAN_NAND_PKTSIZE_512 512 118 119 #define ARASAN_NAND_POLL_TIMEOUT 1000000 120 #define ARASAN_NAND_INVALID_ADDR_CYCL 0xFF 121 122 #define ERR_ADDR_CYCLE -1 123 #define READ_BUFF_SIZE 0x4000 124 125 static struct arasan_nand_command_format *curr_cmd; 126 127 enum addr_cycles { 128 NAND_ADDR_CYCL_NONE, 129 NAND_ADDR_CYCL_ONE, 130 NAND_ADDR_CYCL_ROW, 131 NAND_ADDR_CYCL_COL, 132 NAND_ADDR_CYCL_BOTH, 133 }; 134 135 static struct arasan_nand_command_format arasan_nand_commands[] = { 136 {NAND_CMD_READ0, NAND_CMD_READSTART, NAND_ADDR_CYCL_BOTH, 137 ARASAN_PROG_RD_MASK}, 138 {NAND_CMD_RNDOUT, NAND_CMD_RNDOUTSTART, NAND_ADDR_CYCL_COL, 139 ARASAN_PROG_RD_MASK}, 140 {NAND_CMD_READID, NAND_CMD_NONE, NAND_ADDR_CYCL_ONE, 141 ARASAN_PROG_RD_ID_MASK}, 142 {NAND_CMD_STATUS, NAND_CMD_NONE, NAND_ADDR_CYCL_NONE, 143 ARASAN_PROG_RD_STS_MASK}, 144 {NAND_CMD_SEQIN, NAND_CMD_PAGEPROG, NAND_ADDR_CYCL_BOTH, 145 ARASAN_PROG_PG_PROG_MASK}, 146 {NAND_CMD_RNDIN, NAND_CMD_NONE, NAND_ADDR_CYCL_COL, 147 ARASAN_PROG_CHNG_ROWADR_END_MASK}, 148 {NAND_CMD_ERASE1, NAND_CMD_ERASE2, NAND_ADDR_CYCL_ROW, 149 ARASAN_PROG_BLK_ERS_MASK}, 150 {NAND_CMD_RESET, NAND_CMD_NONE, NAND_ADDR_CYCL_NONE, 151 ARASAN_PROG_RST_MASK}, 152 {NAND_CMD_PARAM, NAND_CMD_NONE, NAND_ADDR_CYCL_ONE, 153 ARASAN_PROG_RD_PARAM_PG_MASK}, 154 {NAND_CMD_GET_FEATURES, NAND_CMD_NONE, NAND_ADDR_CYCL_ONE, 155 ARASAN_PROG_GET_FTRS_MASK}, 156 {NAND_CMD_SET_FEATURES, NAND_CMD_NONE, NAND_ADDR_CYCL_ONE, 157 ARASAN_PROG_SET_FTRS_MASK}, 158 {NAND_CMD_NONE, NAND_CMD_NONE, NAND_ADDR_CYCL_NONE, 0}, 159 }; 160 161 struct arasan_ecc_matrix { 162 u32 pagesize; 163 u32 ecc_codeword_size; 164 u8 eccbits; 165 u8 bch; 166 u8 bchval; 167 u16 eccaddr; 168 u16 eccsize; 169 }; 170 171 static const struct arasan_ecc_matrix ecc_matrix[] = { 172 {512, 512, 1, 0, 0, 0x20D, 0x3}, 173 {512, 512, 4, 1, 3, 0x209, 0x7}, 174 {512, 512, 8, 1, 2, 0x203, 0xD}, 175 /* 176 * 2K byte page 177 */ 178 {2048, 512, 1, 0, 0, 0x834, 0xC}, 179 {2048, 512, 4, 1, 3, 0x826, 0x1A}, 180 {2048, 512, 8, 1, 2, 0x80c, 0x34}, 181 {2048, 512, 12, 1, 1, 0x822, 0x4E}, 182 {2048, 512, 16, 1, 0, 0x808, 0x68}, 183 {2048, 1024, 24, 1, 4, 0x81c, 0x54}, 184 /* 185 * 4K byte page 186 */ 187 {4096, 512, 1, 0, 0, 0x1068, 0x18}, 188 {4096, 512, 4, 1, 3, 0x104c, 0x34}, 189 {4096, 512, 8, 1, 2, 0x1018, 0x68}, 190 {4096, 512, 12, 1, 1, 0x1044, 0x9C}, 191 {4096, 512, 16, 1, 0, 0x1010, 0xD0}, 192 {4096, 1024, 24, 1, 4, 0x1038, 0xA8}, 193 /* 194 * 8K byte page 195 */ 196 {8192, 512, 1, 0, 0, 0x20d0, 0x30}, 197 {8192, 512, 4, 1, 3, 0x2098, 0x68}, 198 {8192, 512, 8, 1, 2, 0x2030, 0xD0}, 199 {8192, 512, 12, 1, 1, 0x2088, 0x138}, 200 {8192, 512, 16, 1, 0, 0x2020, 0x1A0}, 201 {8192, 1024, 24, 1, 4, 0x2070, 0x150}, 202 /* 203 * 16K byte page 204 */ 205 {16384, 512, 1, 0, 0, 0x4460, 0x60}, 206 {16384, 512, 4, 1, 3, 0x43f0, 0xD0}, 207 {16384, 512, 8, 1, 2, 0x4320, 0x1A0}, 208 {16384, 512, 12, 1, 1, 0x4250, 0x270}, 209 {16384, 512, 16, 1, 0, 0x4180, 0x340}, 210 {16384, 1024, 24, 1, 4, 0x4220, 0x2A0} 211 }; 212 213 static struct nand_ecclayout ondie_nand_oob_64 = { 214 .eccbytes = 32, 215 216 .eccpos = { 217 8, 9, 10, 11, 12, 13, 14, 15, 218 24, 25, 26, 27, 28, 29, 30, 31, 219 40, 41, 42, 43, 44, 45, 46, 47, 220 56, 57, 58, 59, 60, 61, 62, 63 221 }, 222 223 .oobfree = { 224 { .offset = 4, .length = 4 }, 225 { .offset = 20, .length = 4 }, 226 { .offset = 36, .length = 4 }, 227 { .offset = 52, .length = 4 } 228 } 229 }; 230 231 /* 232 * bbt decriptors for chips with on-die ECC and 233 * chips with 64-byte OOB 234 */ 235 static u8 bbt_pattern[] = {'B', 'b', 't', '0' }; 236 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' }; 237 238 static struct nand_bbt_descr bbt_main_descr = { 239 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | 240 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, 241 .offs = 4, 242 .len = 4, 243 .veroffs = 20, 244 .maxblocks = 4, 245 .pattern = bbt_pattern 246 }; 247 248 static struct nand_bbt_descr bbt_mirror_descr = { 249 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | 250 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, 251 .offs = 4, 252 .len = 4, 253 .veroffs = 20, 254 .maxblocks = 4, 255 .pattern = mirror_pattern 256 }; 257 258 static u8 buf_data[READ_BUFF_SIZE]; 259 static u32 buf_index; 260 261 static struct nand_ecclayout nand_oob; 262 263 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; 264 265 static void arasan_nand_select_chip(struct mtd_info *mtd, int chip) 266 { 267 u32 reg_val; 268 269 reg_val = readl(&arasan_nand_base->memadr_reg2); 270 if (chip == 0) { 271 reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS0_MASK; 272 writel(reg_val, &arasan_nand_base->memadr_reg2); 273 } else if (chip == 1) { 274 reg_val |= ARASAN_NAND_MEM_ADDR2_CS1_MASK; 275 writel(reg_val, &arasan_nand_base->memadr_reg2); 276 } 277 } 278 279 static void arasan_nand_enable_ecc(void) 280 { 281 u32 reg_val; 282 283 reg_val = readl(&arasan_nand_base->cmd_reg); 284 reg_val |= ARASAN_NAND_CMD_ECC_ON_MASK; 285 286 writel(reg_val, &arasan_nand_base->cmd_reg); 287 } 288 289 static u8 arasan_nand_get_addrcycle(struct mtd_info *mtd) 290 { 291 u8 addrcycles; 292 struct nand_chip *chip = mtd_to_nand(mtd); 293 294 switch (curr_cmd->addr_cycles) { 295 case NAND_ADDR_CYCL_NONE: 296 addrcycles = 0; 297 break; 298 case NAND_ADDR_CYCL_ONE: 299 addrcycles = 1; 300 break; 301 case NAND_ADDR_CYCL_ROW: 302 addrcycles = chip->onfi_params.addr_cycles & 303 ARASAN_NAND_ROW_ADDR_CYCL_MASK; 304 break; 305 case NAND_ADDR_CYCL_COL: 306 addrcycles = (chip->onfi_params.addr_cycles & 307 ARASAN_NAND_COL_ADDR_CYCL_MASK) >> 308 ARASAN_NAND_COL_ADDR_CYCL_SHIFT; 309 break; 310 case NAND_ADDR_CYCL_BOTH: 311 addrcycles = chip->onfi_params.addr_cycles & 312 ARASAN_NAND_ROW_ADDR_CYCL_MASK; 313 addrcycles += (chip->onfi_params.addr_cycles & 314 ARASAN_NAND_COL_ADDR_CYCL_MASK) >> 315 ARASAN_NAND_COL_ADDR_CYCL_SHIFT; 316 break; 317 default: 318 addrcycles = ARASAN_NAND_INVALID_ADDR_CYCL; 319 break; 320 } 321 return addrcycles; 322 } 323 324 static int arasan_nand_read_page(struct mtd_info *mtd, u8 *buf, u32 size) 325 { 326 struct nand_chip *chip = mtd_to_nand(mtd); 327 struct arasan_nand_info *nand = nand_get_controller_data(chip); 328 u32 reg_val, i, pktsize, pktnum; 329 u32 *bufptr = (u32 *)buf; 330 u32 timeout; 331 u32 rdcount = 0; 332 u8 addr_cycles; 333 334 if (chip->ecc_step_ds >= ARASAN_NAND_PKTSIZE_1K) 335 pktsize = ARASAN_NAND_PKTSIZE_1K; 336 else 337 pktsize = ARASAN_NAND_PKTSIZE_512; 338 339 if (size % pktsize) 340 pktnum = size/pktsize + 1; 341 else 342 pktnum = size/pktsize; 343 344 reg_val = readl(&arasan_nand_base->intsts_enr); 345 reg_val |= ARASAN_NAND_INT_STS_ERR_EN_MASK | 346 ARASAN_NAND_INT_STS_MUL_BIT_ERR_MASK; 347 writel(reg_val, &arasan_nand_base->intsts_enr); 348 349 reg_val = readl(&arasan_nand_base->pkt_reg); 350 reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK | 351 ARASAN_NAND_PKT_REG_PKT_SIZE_MASK); 352 reg_val |= (pktnum << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | 353 pktsize; 354 writel(reg_val, &arasan_nand_base->pkt_reg); 355 356 if (!nand->on_die_ecc_enabled) { 357 arasan_nand_enable_ecc(); 358 addr_cycles = arasan_nand_get_addrcycle(mtd); 359 if (addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL) 360 return ERR_ADDR_CYCLE; 361 362 writel((NAND_CMD_RNDOUTSTART << ARASAN_NAND_CMD_CMD2_SHIFT) | 363 NAND_CMD_RNDOUT | (addr_cycles << 364 ARASAN_NAND_CMD_ADDR_CYCL_SHIFT), 365 &arasan_nand_base->ecc_sprcmd_reg); 366 } 367 writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg); 368 369 while (rdcount < pktnum) { 370 timeout = ARASAN_NAND_POLL_TIMEOUT; 371 while (!(readl(&arasan_nand_base->intsts_reg) & 372 ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK) && timeout) { 373 udelay(1); 374 timeout--; 375 } 376 if (!timeout) { 377 puts("arasan_read_page: timedout:Buff RDY\n"); 378 return -ETIMEDOUT; 379 } 380 381 rdcount++; 382 383 if (pktnum == rdcount) { 384 reg_val = readl(&arasan_nand_base->intsts_enr); 385 reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK; 386 writel(reg_val, &arasan_nand_base->intsts_enr); 387 } else { 388 reg_val = readl(&arasan_nand_base->intsts_enr); 389 writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK, 390 &arasan_nand_base->intsts_enr); 391 } 392 reg_val = readl(&arasan_nand_base->intsts_reg); 393 writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK, 394 &arasan_nand_base->intsts_reg); 395 396 for (i = 0; i < pktsize/4; i++) 397 bufptr[i] = readl(&arasan_nand_base->buf_dataport); 398 399 400 bufptr += pktsize/4; 401 402 if (rdcount >= pktnum) 403 break; 404 405 writel(ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK, 406 &arasan_nand_base->intsts_enr); 407 } 408 409 timeout = ARASAN_NAND_POLL_TIMEOUT; 410 411 while (!(readl(&arasan_nand_base->intsts_reg) & 412 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) { 413 udelay(1); 414 timeout--; 415 } 416 if (!timeout) { 417 puts("arasan rd_page timedout:Xfer CMPLT\n"); 418 return -ETIMEDOUT; 419 } 420 421 reg_val = readl(&arasan_nand_base->intsts_enr); 422 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, 423 &arasan_nand_base->intsts_enr); 424 reg_val = readl(&arasan_nand_base->intsts_reg); 425 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, 426 &arasan_nand_base->intsts_reg); 427 428 if (!nand->on_die_ecc_enabled) { 429 if (readl(&arasan_nand_base->intsts_reg) & 430 ARASAN_NAND_INT_STS_MUL_BIT_ERR_MASK) { 431 printf("arasan rd_page:sbiterror\n"); 432 return -1; 433 } 434 435 if (readl(&arasan_nand_base->intsts_reg) & 436 ARASAN_NAND_INT_STS_ERR_EN_MASK) { 437 mtd->ecc_stats.failed++; 438 printf("arasan rd_page:multibiterror\n"); 439 return -1; 440 } 441 } 442 443 return 0; 444 } 445 446 static int arasan_nand_read_page_hwecc(struct mtd_info *mtd, 447 struct nand_chip *chip, u8 *buf, int oob_required, int page) 448 { 449 int status; 450 451 status = arasan_nand_read_page(mtd, buf, (mtd->writesize)); 452 453 if (oob_required) 454 chip->ecc.read_oob(mtd, chip, page); 455 456 return status; 457 } 458 459 static void arasan_nand_fill_tx(const u8 *buf, int len) 460 { 461 u32 __iomem *nand = &arasan_nand_base->buf_dataport; 462 463 if (((unsigned long)buf & 0x3) != 0) { 464 if (((unsigned long)buf & 0x1) != 0) { 465 if (len) { 466 writeb(*buf, nand); 467 buf += 1; 468 len--; 469 } 470 } 471 472 if (((unsigned long)buf & 0x3) != 0) { 473 if (len >= 2) { 474 writew(*(u16 *)buf, nand); 475 buf += 2; 476 len -= 2; 477 } 478 } 479 } 480 481 while (len >= 4) { 482 writel(*(u32 *)buf, nand); 483 buf += 4; 484 len -= 4; 485 } 486 487 if (len) { 488 if (len >= 2) { 489 writew(*(u16 *)buf, nand); 490 buf += 2; 491 len -= 2; 492 } 493 494 if (len) 495 writeb(*buf, nand); 496 } 497 } 498 499 static int arasan_nand_write_page_hwecc(struct mtd_info *mtd, 500 struct nand_chip *chip, const u8 *buf, int oob_required, 501 int page) 502 { 503 u32 reg_val, i, pktsize, pktnum; 504 const u32 *bufptr = (const u32 *)buf; 505 u32 timeout = ARASAN_NAND_POLL_TIMEOUT; 506 u32 size = mtd->writesize; 507 u32 rdcount = 0; 508 u8 column_addr_cycles; 509 struct arasan_nand_info *nand = nand_get_controller_data(chip); 510 511 if (chip->ecc_step_ds >= ARASAN_NAND_PKTSIZE_1K) 512 pktsize = ARASAN_NAND_PKTSIZE_1K; 513 else 514 pktsize = ARASAN_NAND_PKTSIZE_512; 515 516 if (size % pktsize) 517 pktnum = size/pktsize + 1; 518 else 519 pktnum = size/pktsize; 520 521 reg_val = readl(&arasan_nand_base->pkt_reg); 522 reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK | 523 ARASAN_NAND_PKT_REG_PKT_SIZE_MASK); 524 reg_val |= (pktnum << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | pktsize; 525 writel(reg_val, &arasan_nand_base->pkt_reg); 526 527 if (!nand->on_die_ecc_enabled) { 528 arasan_nand_enable_ecc(); 529 column_addr_cycles = (chip->onfi_params.addr_cycles & 530 ARASAN_NAND_COL_ADDR_CYCL_MASK) >> 531 ARASAN_NAND_COL_ADDR_CYCL_SHIFT; 532 writel((NAND_CMD_RNDIN | (column_addr_cycles << 28)), 533 &arasan_nand_base->ecc_sprcmd_reg); 534 } 535 writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg); 536 537 while (rdcount < pktnum) { 538 timeout = ARASAN_NAND_POLL_TIMEOUT; 539 while (!(readl(&arasan_nand_base->intsts_reg) & 540 ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK) && timeout) { 541 udelay(1); 542 timeout--; 543 } 544 545 if (!timeout) { 546 puts("arasan_write_page: timedout:Buff RDY\n"); 547 return -ETIMEDOUT; 548 } 549 550 rdcount++; 551 552 if (pktnum == rdcount) { 553 reg_val = readl(&arasan_nand_base->intsts_enr); 554 reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK; 555 writel(reg_val, &arasan_nand_base->intsts_enr); 556 } else { 557 reg_val = readl(&arasan_nand_base->intsts_enr); 558 writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK, 559 &arasan_nand_base->intsts_enr); 560 } 561 562 reg_val = readl(&arasan_nand_base->intsts_reg); 563 writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK, 564 &arasan_nand_base->intsts_reg); 565 566 for (i = 0; i < pktsize/4; i++) 567 writel(bufptr[i], &arasan_nand_base->buf_dataport); 568 569 bufptr += pktsize/4; 570 571 if (rdcount >= pktnum) 572 break; 573 574 writel(ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK, 575 &arasan_nand_base->intsts_enr); 576 } 577 578 timeout = ARASAN_NAND_POLL_TIMEOUT; 579 580 while (!(readl(&arasan_nand_base->intsts_reg) & 581 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) { 582 udelay(1); 583 timeout--; 584 } 585 if (!timeout) { 586 puts("arasan write_page timedout:Xfer CMPLT\n"); 587 return -ETIMEDOUT; 588 } 589 590 reg_val = readl(&arasan_nand_base->intsts_enr); 591 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, 592 &arasan_nand_base->intsts_enr); 593 reg_val = readl(&arasan_nand_base->intsts_reg); 594 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, 595 &arasan_nand_base->intsts_reg); 596 597 if (oob_required) 598 chip->ecc.write_oob(mtd, chip, nand->page); 599 600 return 0; 601 } 602 603 static int arasan_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip, 604 int page) 605 { 606 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); 607 chip->read_buf(mtd, chip->oob_poi, (mtd->oobsize)); 608 609 return 0; 610 } 611 612 static int arasan_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip, 613 int page) 614 { 615 int status = 0; 616 const u8 *buf = chip->oob_poi; 617 618 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); 619 chip->write_buf(mtd, buf, mtd->oobsize); 620 621 return status; 622 } 623 624 static int arasan_nand_reset(struct arasan_nand_command_format *curr_cmd) 625 { 626 u32 timeout = ARASAN_NAND_POLL_TIMEOUT; 627 u32 cmd_reg = 0; 628 629 writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, 630 &arasan_nand_base->intsts_enr); 631 cmd_reg = readl(&arasan_nand_base->cmd_reg); 632 cmd_reg &= ~ARASAN_NAND_CMD_CMD12_MASK; 633 634 cmd_reg |= curr_cmd->cmd1 | 635 (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT); 636 writel(cmd_reg, &arasan_nand_base->cmd_reg); 637 writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg); 638 639 while (!(readl(&arasan_nand_base->intsts_reg) & 640 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) { 641 udelay(1); 642 timeout--; 643 } 644 if (!timeout) { 645 printf("ERROR:%s timedout\n", __func__); 646 return -ETIMEDOUT; 647 } 648 649 writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, 650 &arasan_nand_base->intsts_enr); 651 652 writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, 653 &arasan_nand_base->intsts_reg); 654 655 return 0; 656 } 657 658 static u8 arasan_nand_page(struct mtd_info *mtd) 659 { 660 u8 page_val = 0; 661 662 switch (mtd->writesize) { 663 case 512: 664 page_val = 0; 665 break; 666 case 2048: 667 page_val = 1; 668 break; 669 case 4096: 670 page_val = 2; 671 break; 672 case 8192: 673 page_val = 3; 674 break; 675 case 16384: 676 page_val = 4; 677 break; 678 case 1024: 679 page_val = 5; 680 break; 681 default: 682 printf("%s:Pagesize>16K\n", __func__); 683 break; 684 } 685 686 return page_val; 687 } 688 689 static int arasan_nand_send_wrcmd(struct arasan_nand_command_format *curr_cmd, 690 int column, int page_addr, struct mtd_info *mtd) 691 { 692 u32 reg_val, page; 693 u8 page_val, addr_cycles; 694 695 writel(ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK, 696 &arasan_nand_base->intsts_enr); 697 reg_val = readl(&arasan_nand_base->cmd_reg); 698 reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK; 699 reg_val |= curr_cmd->cmd1 | 700 (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT); 701 if (curr_cmd->cmd1 == NAND_CMD_SEQIN) { 702 reg_val &= ~ARASAN_NAND_CMD_PG_SIZE_MASK; 703 page_val = arasan_nand_page(mtd); 704 reg_val |= (page_val << ARASAN_NAND_CMD_PG_SIZE_SHIFT); 705 } 706 707 reg_val &= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK; 708 addr_cycles = arasan_nand_get_addrcycle(mtd); 709 710 if (addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL) 711 return ERR_ADDR_CYCLE; 712 713 reg_val |= (addr_cycles << 714 ARASAN_NAND_CMD_ADDR_CYCL_SHIFT); 715 writel(reg_val, &arasan_nand_base->cmd_reg); 716 717 if (page_addr == -1) 718 page_addr = 0; 719 720 page = (page_addr << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) & 721 ARASAN_NAND_MEM_ADDR1_PAGE_MASK; 722 column &= ARASAN_NAND_MEM_ADDR1_COL_MASK; 723 writel(page|column, &arasan_nand_base->memadr_reg1); 724 725 reg_val = readl(&arasan_nand_base->memadr_reg2); 726 reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK; 727 reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT); 728 writel(reg_val, &arasan_nand_base->memadr_reg2); 729 730 return 0; 731 } 732 733 static void arasan_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len) 734 { 735 u32 reg_val; 736 u32 timeout = ARASAN_NAND_POLL_TIMEOUT; 737 738 reg_val = readl(&arasan_nand_base->pkt_reg); 739 reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK | 740 ARASAN_NAND_PKT_REG_PKT_SIZE_MASK); 741 742 reg_val |= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | len; 743 writel(reg_val, &arasan_nand_base->pkt_reg); 744 writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg); 745 746 while (!(readl(&arasan_nand_base->intsts_reg) & 747 ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK) && timeout) { 748 udelay(1); 749 timeout--; 750 } 751 752 if (!timeout) 753 puts("ERROR:arasan_nand_write_buf timedout:Buff RDY\n"); 754 755 reg_val = readl(&arasan_nand_base->intsts_enr); 756 reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK; 757 writel(reg_val, &arasan_nand_base->intsts_enr); 758 writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK, 759 &arasan_nand_base->intsts_enr); 760 reg_val = readl(&arasan_nand_base->intsts_reg); 761 writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK, 762 &arasan_nand_base->intsts_reg); 763 764 arasan_nand_fill_tx(buf, len); 765 766 timeout = ARASAN_NAND_POLL_TIMEOUT; 767 while (!(readl(&arasan_nand_base->intsts_reg) & 768 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) { 769 udelay(1); 770 timeout--; 771 } 772 if (!timeout) 773 puts("ERROR:arasan_nand_write_buf timedout:Xfer CMPLT\n"); 774 775 writel(readl(&arasan_nand_base->intsts_enr) | 776 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, 777 &arasan_nand_base->intsts_enr); 778 writel(readl(&arasan_nand_base->intsts_reg) | 779 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, 780 &arasan_nand_base->intsts_reg); 781 } 782 783 static int arasan_nand_erase(struct arasan_nand_command_format *curr_cmd, 784 int column, int page_addr, struct mtd_info *mtd) 785 { 786 u32 reg_val, page; 787 u32 timeout = ARASAN_NAND_POLL_TIMEOUT; 788 u8 row_addr_cycles; 789 790 writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, 791 &arasan_nand_base->intsts_enr); 792 reg_val = readl(&arasan_nand_base->cmd_reg); 793 reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK; 794 reg_val |= curr_cmd->cmd1 | 795 (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT); 796 row_addr_cycles = arasan_nand_get_addrcycle(mtd); 797 798 if (row_addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL) 799 return ERR_ADDR_CYCLE; 800 801 reg_val &= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK; 802 reg_val |= (row_addr_cycles << 803 ARASAN_NAND_CMD_ADDR_CYCL_SHIFT); 804 805 writel(reg_val, &arasan_nand_base->cmd_reg); 806 807 page = (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) & 808 ARASAN_NAND_MEM_ADDR1_COL_MASK; 809 column = page_addr & ARASAN_NAND_MEM_ADDR1_COL_MASK; 810 writel(column | (page << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT), 811 &arasan_nand_base->memadr_reg1); 812 813 reg_val = readl(&arasan_nand_base->memadr_reg2); 814 reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK; 815 reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT); 816 writel(reg_val, &arasan_nand_base->memadr_reg2); 817 writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg); 818 819 while (!(readl(&arasan_nand_base->intsts_reg) & 820 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) { 821 udelay(1); 822 timeout--; 823 } 824 if (!timeout) { 825 printf("ERROR:%s timedout:Xfer CMPLT\n", __func__); 826 return -ETIMEDOUT; 827 } 828 829 reg_val = readl(&arasan_nand_base->intsts_enr); 830 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, 831 &arasan_nand_base->intsts_enr); 832 reg_val = readl(&arasan_nand_base->intsts_reg); 833 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, 834 &arasan_nand_base->intsts_reg); 835 836 return 0; 837 } 838 839 static int arasan_nand_read_status(struct arasan_nand_command_format *curr_cmd, 840 int column, int page_addr, struct mtd_info *mtd) 841 { 842 u32 reg_val; 843 u32 timeout = ARASAN_NAND_POLL_TIMEOUT; 844 u8 addr_cycles; 845 846 writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, 847 &arasan_nand_base->intsts_enr); 848 reg_val = readl(&arasan_nand_base->cmd_reg); 849 reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK; 850 reg_val |= curr_cmd->cmd1 | 851 (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT); 852 addr_cycles = arasan_nand_get_addrcycle(mtd); 853 854 if (addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL) 855 return ERR_ADDR_CYCLE; 856 857 reg_val &= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK; 858 reg_val |= (addr_cycles << 859 ARASAN_NAND_CMD_ADDR_CYCL_SHIFT); 860 861 writel(reg_val, &arasan_nand_base->cmd_reg); 862 863 reg_val = readl(&arasan_nand_base->pkt_reg); 864 reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK | 865 ARASAN_NAND_PKT_REG_PKT_SIZE_MASK); 866 reg_val |= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | 1; 867 writel(reg_val, &arasan_nand_base->pkt_reg); 868 869 writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg); 870 while (!(readl(&arasan_nand_base->intsts_reg) & 871 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) { 872 udelay(1); 873 timeout--; 874 } 875 876 if (!timeout) { 877 printf("ERROR:%s: timedout:Xfer CMPLT\n", __func__); 878 return -ETIMEDOUT; 879 } 880 881 reg_val = readl(&arasan_nand_base->intsts_enr); 882 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, 883 &arasan_nand_base->intsts_enr); 884 reg_val = readl(&arasan_nand_base->intsts_reg); 885 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, 886 &arasan_nand_base->intsts_reg); 887 888 return 0; 889 } 890 891 static int arasan_nand_send_rdcmd(struct arasan_nand_command_format *curr_cmd, 892 int column, int page_addr, struct mtd_info *mtd) 893 { 894 u32 reg_val, addr_cycles, page; 895 u8 page_val; 896 897 reg_val = readl(&arasan_nand_base->intsts_enr); 898 writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK, 899 &arasan_nand_base->intsts_enr); 900 901 reg_val = readl(&arasan_nand_base->cmd_reg); 902 reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK; 903 reg_val |= curr_cmd->cmd1 | 904 (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT); 905 906 if (curr_cmd->cmd1 == NAND_CMD_RNDOUT || 907 curr_cmd->cmd1 == NAND_CMD_READ0) { 908 reg_val &= ~ARASAN_NAND_CMD_PG_SIZE_MASK; 909 page_val = arasan_nand_page(mtd); 910 reg_val |= (page_val << ARASAN_NAND_CMD_PG_SIZE_SHIFT); 911 } 912 913 reg_val &= ~ARASAN_NAND_CMD_ECC_ON_MASK; 914 915 reg_val &= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK; 916 917 addr_cycles = arasan_nand_get_addrcycle(mtd); 918 919 if (addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL) 920 return ERR_ADDR_CYCLE; 921 922 reg_val |= (addr_cycles << 28); 923 writel(reg_val, &arasan_nand_base->cmd_reg); 924 925 if (page_addr == -1) 926 page_addr = 0; 927 928 page = (page_addr << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) & 929 ARASAN_NAND_MEM_ADDR1_PAGE_MASK; 930 column &= ARASAN_NAND_MEM_ADDR1_COL_MASK; 931 writel(page | column, &arasan_nand_base->memadr_reg1); 932 933 reg_val = readl(&arasan_nand_base->memadr_reg2); 934 reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK; 935 reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT); 936 writel(reg_val, &arasan_nand_base->memadr_reg2); 937 938 buf_index = 0; 939 940 return 0; 941 } 942 943 static void arasan_nand_read_buf(struct mtd_info *mtd, u8 *buf, int size) 944 { 945 u32 reg_val, i; 946 u32 *bufptr = (u32 *)buf; 947 u32 timeout = ARASAN_NAND_POLL_TIMEOUT; 948 949 reg_val = readl(&arasan_nand_base->pkt_reg); 950 reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK | 951 ARASAN_NAND_PKT_REG_PKT_SIZE_MASK); 952 reg_val |= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | size; 953 writel(reg_val, &arasan_nand_base->pkt_reg); 954 955 writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg); 956 957 while (!(readl(&arasan_nand_base->intsts_reg) & 958 ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK) && timeout) { 959 udelay(1); 960 timeout--; 961 } 962 963 if (!timeout) 964 puts("ERROR:arasan_nand_read_buf timedout:Buff RDY\n"); 965 966 reg_val = readl(&arasan_nand_base->intsts_enr); 967 reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK; 968 writel(reg_val, &arasan_nand_base->intsts_enr); 969 970 writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK, 971 &arasan_nand_base->intsts_enr); 972 reg_val = readl(&arasan_nand_base->intsts_reg); 973 writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK, 974 &arasan_nand_base->intsts_reg); 975 976 buf_index = 0; 977 for (i = 0; i < size / 4; i++) 978 bufptr[i] = readl(&arasan_nand_base->buf_dataport); 979 980 if (size & 0x03) 981 bufptr[i] = readl(&arasan_nand_base->buf_dataport); 982 983 timeout = ARASAN_NAND_POLL_TIMEOUT; 984 985 while (!(readl(&arasan_nand_base->intsts_reg) & 986 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) { 987 udelay(1); 988 timeout--; 989 } 990 991 if (!timeout) 992 puts("ERROR:arasan_nand_read_buf timedout:Xfer CMPLT\n"); 993 994 reg_val = readl(&arasan_nand_base->intsts_enr); 995 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, 996 &arasan_nand_base->intsts_enr); 997 reg_val = readl(&arasan_nand_base->intsts_reg); 998 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, 999 &arasan_nand_base->intsts_reg); 1000 } 1001 1002 static u8 arasan_nand_read_byte(struct mtd_info *mtd) 1003 { 1004 struct nand_chip *chip = mtd_to_nand(mtd); 1005 u32 size; 1006 u8 val; 1007 struct nand_onfi_params *p; 1008 1009 if (buf_index == 0) { 1010 p = &chip->onfi_params; 1011 if (curr_cmd->cmd1 == NAND_CMD_READID) 1012 size = 4; 1013 else if (curr_cmd->cmd1 == NAND_CMD_PARAM) 1014 size = sizeof(struct nand_onfi_params); 1015 else if (curr_cmd->cmd1 == NAND_CMD_RNDOUT) 1016 size = le16_to_cpu(p->ext_param_page_length) * 16; 1017 else if (curr_cmd->cmd1 == NAND_CMD_GET_FEATURES) 1018 size = 4; 1019 else if (curr_cmd->cmd1 == NAND_CMD_STATUS) 1020 return readb(&arasan_nand_base->flash_sts_reg); 1021 else 1022 size = 8; 1023 chip->read_buf(mtd, &buf_data[0], size); 1024 } 1025 1026 val = *(&buf_data[0] + buf_index); 1027 buf_index++; 1028 1029 return val; 1030 } 1031 1032 static void arasan_nand_cmd_function(struct mtd_info *mtd, unsigned int command, 1033 int column, int page_addr) 1034 { 1035 u32 i, ret = 0; 1036 struct nand_chip *chip = mtd_to_nand(mtd); 1037 struct arasan_nand_info *nand = nand_get_controller_data(chip); 1038 1039 curr_cmd = NULL; 1040 writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, 1041 &arasan_nand_base->intsts_enr); 1042 1043 if ((command == NAND_CMD_READOOB) && 1044 (mtd->writesize > 512)) { 1045 column += mtd->writesize; 1046 command = NAND_CMD_READ0; 1047 } 1048 1049 /* Get the command format */ 1050 for (i = 0; (arasan_nand_commands[i].cmd1 != NAND_CMD_NONE || 1051 arasan_nand_commands[i].cmd2 != NAND_CMD_NONE); i++) { 1052 if (command == arasan_nand_commands[i].cmd1) { 1053 curr_cmd = &arasan_nand_commands[i]; 1054 break; 1055 } 1056 } 1057 1058 if (curr_cmd == NULL) { 1059 printf("Unsupported Command; 0x%x\n", command); 1060 return; 1061 } 1062 1063 if (curr_cmd->cmd1 == NAND_CMD_RESET) 1064 ret = arasan_nand_reset(curr_cmd); 1065 1066 if ((curr_cmd->cmd1 == NAND_CMD_READID) || 1067 (curr_cmd->cmd1 == NAND_CMD_PARAM) || 1068 (curr_cmd->cmd1 == NAND_CMD_RNDOUT) || 1069 (curr_cmd->cmd1 == NAND_CMD_GET_FEATURES) || 1070 (curr_cmd->cmd1 == NAND_CMD_READ0)) 1071 ret = arasan_nand_send_rdcmd(curr_cmd, column, page_addr, mtd); 1072 1073 if ((curr_cmd->cmd1 == NAND_CMD_SET_FEATURES) || 1074 (curr_cmd->cmd1 == NAND_CMD_SEQIN)) { 1075 nand->page = page_addr; 1076 ret = arasan_nand_send_wrcmd(curr_cmd, column, page_addr, mtd); 1077 } 1078 1079 if (curr_cmd->cmd1 == NAND_CMD_ERASE1) 1080 ret = arasan_nand_erase(curr_cmd, column, page_addr, mtd); 1081 1082 if (curr_cmd->cmd1 == NAND_CMD_STATUS) 1083 ret = arasan_nand_read_status(curr_cmd, column, page_addr, mtd); 1084 1085 if (ret != 0) 1086 printf("ERROR:%s:command:0x%x\n", __func__, curr_cmd->cmd1); 1087 } 1088 1089 static void arasan_check_ondie(struct mtd_info *mtd) 1090 { 1091 struct nand_chip *nand_chip = mtd_to_nand(mtd); 1092 struct arasan_nand_info *nand = nand_get_controller_data(nand_chip); 1093 u8 maf_id, dev_id; 1094 u8 get_feature[4]; 1095 u8 set_feature[4] = {ENABLE_ONDIE_ECC, 0x00, 0x00, 0x00}; 1096 u32 i; 1097 1098 /* Send the command for reading device ID */ 1099 nand_chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); 1100 nand_chip->cmdfunc(mtd, NAND_CMD_READID, 0, -1); 1101 1102 /* Read manufacturer and device IDs */ 1103 maf_id = nand_chip->read_byte(mtd); 1104 dev_id = nand_chip->read_byte(mtd); 1105 1106 if ((maf_id == NAND_MFR_MICRON) && 1107 ((dev_id == 0xf1) || (dev_id == 0xa1) || (dev_id == 0xb1) || 1108 (dev_id == 0xaa) || (dev_id == 0xba) || (dev_id == 0xda) || 1109 (dev_id == 0xca) || (dev_id == 0xac) || (dev_id == 0xbc) || 1110 (dev_id == 0xdc) || (dev_id == 0xcc) || (dev_id == 0xa3) || 1111 (dev_id == 0xb3) || (dev_id == 0xd3) || (dev_id == 0xc3))) { 1112 nand_chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, 1113 ONDIE_ECC_FEATURE_ADDR, -1); 1114 1115 nand_chip->write_buf(mtd, &set_feature[0], 4); 1116 nand_chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, 1117 ONDIE_ECC_FEATURE_ADDR, -1); 1118 1119 for (i = 0; i < 4; i++) 1120 get_feature[i] = nand_chip->read_byte(mtd); 1121 1122 if (get_feature[0] & ENABLE_ONDIE_ECC) 1123 nand->on_die_ecc_enabled = true; 1124 else 1125 printf("%s: Unable to enable OnDie ECC\n", __func__); 1126 1127 /* Use the BBT pattern descriptors */ 1128 nand_chip->bbt_td = &bbt_main_descr; 1129 nand_chip->bbt_md = &bbt_mirror_descr; 1130 } 1131 } 1132 1133 static int arasan_nand_ecc_init(struct mtd_info *mtd) 1134 { 1135 int found = -1; 1136 u32 regval, eccpos_start, i, eccaddr; 1137 struct nand_chip *nand_chip = mtd_to_nand(mtd); 1138 1139 for (i = 0; i < ARRAY_SIZE(ecc_matrix); i++) { 1140 if ((ecc_matrix[i].pagesize == mtd->writesize) && 1141 (ecc_matrix[i].ecc_codeword_size >= 1142 nand_chip->ecc_step_ds)) { 1143 if (ecc_matrix[i].eccbits >= 1144 nand_chip->ecc_strength_ds) { 1145 found = i; 1146 break; 1147 } 1148 found = i; 1149 } 1150 } 1151 1152 if (found < 0) 1153 return 1; 1154 1155 eccaddr = mtd->writesize + mtd->oobsize - 1156 ecc_matrix[found].eccsize; 1157 1158 regval = eccaddr | 1159 (ecc_matrix[found].eccsize << ARASAN_NAND_ECC_SIZE_SHIFT) | 1160 (ecc_matrix[found].bch << ARASAN_NAND_ECC_BCH_SHIFT); 1161 writel(regval, &arasan_nand_base->ecc_reg); 1162 1163 if (ecc_matrix[found].bch) { 1164 regval = readl(&arasan_nand_base->memadr_reg2); 1165 regval &= ~ARASAN_NAND_MEM_ADDR2_BCH_MASK; 1166 regval |= (ecc_matrix[found].bchval << 1167 ARASAN_NAND_MEM_ADDR2_BCH_SHIFT); 1168 writel(regval, &arasan_nand_base->memadr_reg2); 1169 } 1170 1171 nand_oob.eccbytes = ecc_matrix[found].eccsize; 1172 eccpos_start = mtd->oobsize - nand_oob.eccbytes; 1173 1174 for (i = 0; i < nand_oob.eccbytes; i++) 1175 nand_oob.eccpos[i] = eccpos_start + i; 1176 1177 nand_oob.oobfree[0].offset = 2; 1178 nand_oob.oobfree[0].length = eccpos_start - 2; 1179 1180 nand_chip->ecc.size = ecc_matrix[found].ecc_codeword_size; 1181 nand_chip->ecc.strength = ecc_matrix[found].eccbits; 1182 nand_chip->ecc.bytes = ecc_matrix[found].eccsize; 1183 nand_chip->ecc.layout = &nand_oob; 1184 1185 return 0; 1186 } 1187 1188 static int arasan_nand_init(struct nand_chip *nand_chip, int devnum) 1189 { 1190 struct arasan_nand_info *nand; 1191 struct mtd_info *mtd; 1192 int err = -1; 1193 1194 nand = calloc(1, sizeof(struct arasan_nand_info)); 1195 if (!nand) { 1196 printf("%s: failed to allocate\n", __func__); 1197 return err; 1198 } 1199 1200 nand->nand_base = arasan_nand_base; 1201 mtd = nand_to_mtd(nand_chip); 1202 nand_set_controller_data(nand_chip, nand); 1203 1204 #ifdef CONFIG_SYS_NAND_NO_SUBPAGE_WRITE 1205 nand_chip->options |= NAND_NO_SUBPAGE_WRITE; 1206 #endif 1207 1208 /* Set the driver entry points for MTD */ 1209 nand_chip->cmdfunc = arasan_nand_cmd_function; 1210 nand_chip->select_chip = arasan_nand_select_chip; 1211 nand_chip->read_byte = arasan_nand_read_byte; 1212 1213 /* Buffer read/write routines */ 1214 nand_chip->read_buf = arasan_nand_read_buf; 1215 nand_chip->write_buf = arasan_nand_write_buf; 1216 nand_chip->bbt_options = NAND_BBT_USE_FLASH; 1217 1218 writel(0x0, &arasan_nand_base->cmd_reg); 1219 writel(0x0, &arasan_nand_base->pgm_reg); 1220 1221 /* first scan to find the device and get the page size */ 1222 if (nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL)) { 1223 printf("%s: nand_scan_ident failed\n", __func__); 1224 goto fail; 1225 } 1226 1227 nand_chip->ecc.mode = NAND_ECC_HW; 1228 nand_chip->ecc.hwctl = NULL; 1229 nand_chip->ecc.read_page = arasan_nand_read_page_hwecc; 1230 nand_chip->ecc.write_page = arasan_nand_write_page_hwecc; 1231 nand_chip->ecc.read_oob = arasan_nand_read_oob; 1232 nand_chip->ecc.write_oob = arasan_nand_write_oob; 1233 1234 arasan_check_ondie(mtd); 1235 1236 /* 1237 * If on die supported, then give priority to on-die ecc and use 1238 * it instead of controller ecc. 1239 */ 1240 if (nand->on_die_ecc_enabled) { 1241 nand_chip->ecc.strength = 1; 1242 nand_chip->ecc.size = mtd->writesize; 1243 nand_chip->ecc.bytes = 0; 1244 nand_chip->ecc.layout = &ondie_nand_oob_64; 1245 } else { 1246 if (arasan_nand_ecc_init(mtd)) { 1247 printf("%s: nand_ecc_init failed\n", __func__); 1248 goto fail; 1249 } 1250 } 1251 1252 if (nand_scan_tail(mtd)) { 1253 printf("%s: nand_scan_tail failed\n", __func__); 1254 goto fail; 1255 } 1256 1257 if (nand_register(devnum, mtd)) { 1258 printf("Nand Register Fail\n"); 1259 goto fail; 1260 } 1261 1262 return 0; 1263 fail: 1264 free(nand); 1265 return err; 1266 } 1267 1268 void board_nand_init(void) 1269 { 1270 struct nand_chip *nand = &nand_chip[0]; 1271 1272 if (arasan_nand_init(nand, 0)) 1273 puts("NAND init failed\n"); 1274 } 1275