1 /* 2 * Copyright 2011, Marvell Semiconductor Inc. 3 * Lei Wen <leiwen@marvell.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 * 7 * Back ported to the 8xx platform (from the 8260 platform) by 8 * Murray.Jensen@cmst.csiro.au, 27-Jan-01. 9 */ 10 11 #include <common.h> 12 #include <errno.h> 13 #include <malloc.h> 14 #include <mmc.h> 15 #include <sdhci.h> 16 17 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER) 18 void *aligned_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER; 19 #else 20 void *aligned_buffer; 21 #endif 22 23 static void sdhci_reset(struct sdhci_host *host, u8 mask) 24 { 25 unsigned long timeout; 26 27 /* Wait max 100 ms */ 28 timeout = 100; 29 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); 30 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { 31 if (timeout == 0) { 32 printf("%s: Reset 0x%x never completed.\n", 33 __func__, (int)mask); 34 return; 35 } 36 timeout--; 37 udelay(1000); 38 } 39 } 40 41 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd) 42 { 43 int i; 44 if (cmd->resp_type & MMC_RSP_136) { 45 /* CRC is stripped so we need to do some shifting. */ 46 for (i = 0; i < 4; i++) { 47 cmd->response[i] = sdhci_readl(host, 48 SDHCI_RESPONSE + (3-i)*4) << 8; 49 if (i != 3) 50 cmd->response[i] |= sdhci_readb(host, 51 SDHCI_RESPONSE + (3-i)*4-1); 52 } 53 } else { 54 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE); 55 } 56 } 57 58 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data) 59 { 60 int i; 61 char *offs; 62 for (i = 0; i < data->blocksize; i += 4) { 63 offs = data->dest + i; 64 if (data->flags == MMC_DATA_READ) 65 *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER); 66 else 67 sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER); 68 } 69 } 70 71 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data, 72 unsigned int start_addr) 73 { 74 unsigned int stat, rdy, mask, timeout, block = 0; 75 bool transfer_done = false; 76 #ifdef CONFIG_MMC_SDHCI_SDMA 77 unsigned char ctrl; 78 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 79 ctrl &= ~SDHCI_CTRL_DMA_MASK; 80 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 81 #endif 82 83 timeout = 1000000; 84 rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL; 85 mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE; 86 do { 87 stat = sdhci_readl(host, SDHCI_INT_STATUS); 88 if (stat & SDHCI_INT_ERROR) { 89 printf("%s: Error detected in status(0x%X)!\n", 90 __func__, stat); 91 return -EIO; 92 } 93 if (!transfer_done && (stat & rdy)) { 94 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask)) 95 continue; 96 sdhci_writel(host, rdy, SDHCI_INT_STATUS); 97 sdhci_transfer_pio(host, data); 98 data->dest += data->blocksize; 99 if (++block >= data->blocks) { 100 /* Keep looping until the SDHCI_INT_DATA_END is 101 * cleared, even if we finished sending all the 102 * blocks. 103 */ 104 transfer_done = true; 105 continue; 106 } 107 } 108 #ifdef CONFIG_MMC_SDHCI_SDMA 109 if (!transfer_done && (stat & SDHCI_INT_DMA_END)) { 110 sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS); 111 start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1); 112 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE; 113 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); 114 } 115 #endif 116 if (timeout-- > 0) 117 udelay(10); 118 else { 119 printf("%s: Transfer data timeout\n", __func__); 120 return -ETIMEDOUT; 121 } 122 } while (!(stat & SDHCI_INT_DATA_END)); 123 return 0; 124 } 125 126 /* 127 * No command will be sent by driver if card is busy, so driver must wait 128 * for card ready state. 129 * Every time when card is busy after timeout then (last) timeout value will be 130 * increased twice but only if it doesn't exceed global defined maximum. 131 * Each function call will use last timeout value. 132 */ 133 #define SDHCI_CMD_MAX_TIMEOUT 3200 134 #define SDHCI_CMD_DEFAULT_TIMEOUT 100 135 #define SDHCI_READ_STATUS_TIMEOUT 1000 136 137 #ifdef CONFIG_DM_MMC 138 static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd, 139 struct mmc_data *data) 140 { 141 struct mmc *mmc = mmc_get_mmc_dev(dev); 142 143 #else 144 static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, 145 struct mmc_data *data) 146 { 147 #endif 148 struct sdhci_host *host = mmc->priv; 149 unsigned int stat = 0; 150 int ret = 0; 151 int trans_bytes = 0, is_aligned = 1; 152 u32 mask, flags, mode; 153 unsigned int time = 0, start_addr = 0; 154 int mmc_dev = mmc_get_blk_desc(mmc)->devnum; 155 unsigned start = get_timer(0); 156 157 /* Timeout unit - ms */ 158 static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT; 159 160 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); 161 mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT; 162 163 /* We shouldn't wait for data inihibit for stop commands, even 164 though they might use busy signaling */ 165 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 166 mask &= ~SDHCI_DATA_INHIBIT; 167 168 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 169 if (time >= cmd_timeout) { 170 printf("%s: MMC: %d busy ", __func__, mmc_dev); 171 if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) { 172 cmd_timeout += cmd_timeout; 173 printf("timeout increasing to: %u ms.\n", 174 cmd_timeout); 175 } else { 176 puts("timeout.\n"); 177 return -ECOMM; 178 } 179 } 180 time++; 181 udelay(1000); 182 } 183 184 mask = SDHCI_INT_RESPONSE; 185 if (!(cmd->resp_type & MMC_RSP_PRESENT)) 186 flags = SDHCI_CMD_RESP_NONE; 187 else if (cmd->resp_type & MMC_RSP_136) 188 flags = SDHCI_CMD_RESP_LONG; 189 else if (cmd->resp_type & MMC_RSP_BUSY) { 190 flags = SDHCI_CMD_RESP_SHORT_BUSY; 191 if (data) 192 mask |= SDHCI_INT_DATA_END; 193 } else 194 flags = SDHCI_CMD_RESP_SHORT; 195 196 if (cmd->resp_type & MMC_RSP_CRC) 197 flags |= SDHCI_CMD_CRC; 198 if (cmd->resp_type & MMC_RSP_OPCODE) 199 flags |= SDHCI_CMD_INDEX; 200 if (data) 201 flags |= SDHCI_CMD_DATA; 202 203 /* Set Transfer mode regarding to data flag */ 204 if (data != 0) { 205 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); 206 mode = SDHCI_TRNS_BLK_CNT_EN; 207 trans_bytes = data->blocks * data->blocksize; 208 if (data->blocks > 1) 209 mode |= SDHCI_TRNS_MULTI; 210 211 if (data->flags == MMC_DATA_READ) 212 mode |= SDHCI_TRNS_READ; 213 214 #ifdef CONFIG_MMC_SDHCI_SDMA 215 if (data->flags == MMC_DATA_READ) 216 start_addr = (unsigned long)data->dest; 217 else 218 start_addr = (unsigned long)data->src; 219 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && 220 (start_addr & 0x7) != 0x0) { 221 is_aligned = 0; 222 start_addr = (unsigned long)aligned_buffer; 223 if (data->flags != MMC_DATA_READ) 224 memcpy(aligned_buffer, data->src, trans_bytes); 225 } 226 227 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER) 228 /* 229 * Always use this bounce-buffer when 230 * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined 231 */ 232 is_aligned = 0; 233 start_addr = (unsigned long)aligned_buffer; 234 if (data->flags != MMC_DATA_READ) 235 memcpy(aligned_buffer, data->src, trans_bytes); 236 #endif 237 238 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); 239 mode |= SDHCI_TRNS_DMA; 240 #endif 241 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 242 data->blocksize), 243 SDHCI_BLOCK_SIZE); 244 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); 245 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); 246 } else if (cmd->resp_type & MMC_RSP_BUSY) { 247 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); 248 } 249 250 sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT); 251 #ifdef CONFIG_MMC_SDHCI_SDMA 252 if (data != 0) { 253 trans_bytes = ALIGN(trans_bytes, CONFIG_SYS_CACHELINE_SIZE); 254 flush_cache(start_addr, trans_bytes); 255 } 256 #endif 257 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND); 258 start = get_timer(0); 259 do { 260 stat = sdhci_readl(host, SDHCI_INT_STATUS); 261 if (stat & SDHCI_INT_ERROR) 262 break; 263 264 if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) { 265 if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) { 266 return 0; 267 } else { 268 printf("%s: Timeout for status update!\n", 269 __func__); 270 return -ETIMEDOUT; 271 } 272 } 273 } while ((stat & mask) != mask); 274 275 if ((stat & (SDHCI_INT_ERROR | mask)) == mask) { 276 sdhci_cmd_done(host, cmd); 277 sdhci_writel(host, mask, SDHCI_INT_STATUS); 278 } else 279 ret = -1; 280 281 if (!ret && data) 282 ret = sdhci_transfer_data(host, data, start_addr); 283 284 if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD) 285 udelay(1000); 286 287 stat = sdhci_readl(host, SDHCI_INT_STATUS); 288 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); 289 if (!ret) { 290 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && 291 !is_aligned && (data->flags == MMC_DATA_READ)) 292 memcpy(data->dest, aligned_buffer, trans_bytes); 293 return 0; 294 } 295 296 sdhci_reset(host, SDHCI_RESET_CMD); 297 sdhci_reset(host, SDHCI_RESET_DATA); 298 if (stat & SDHCI_INT_TIMEOUT) 299 return -ETIMEDOUT; 300 else 301 return -ECOMM; 302 } 303 304 static int sdhci_set_clock(struct mmc *mmc, unsigned int clock) 305 { 306 struct sdhci_host *host = mmc->priv; 307 unsigned int div, clk = 0, timeout; 308 309 /* Wait max 20 ms */ 310 timeout = 200; 311 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & 312 (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) { 313 if (timeout == 0) { 314 printf("%s: Timeout to wait cmd & data inhibit\n", 315 __func__); 316 return -EBUSY; 317 } 318 319 timeout--; 320 udelay(100); 321 } 322 323 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 324 325 if (clock == 0) 326 return 0; 327 328 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { 329 /* 330 * Check if the Host Controller supports Programmable Clock 331 * Mode. 332 */ 333 if (host->clk_mul) { 334 for (div = 1; div <= 1024; div++) { 335 if ((host->max_clk / div) <= clock) 336 break; 337 } 338 339 /* 340 * Set Programmable Clock Mode in the Clock 341 * Control register. 342 */ 343 clk = SDHCI_PROG_CLOCK_MODE; 344 div--; 345 } else { 346 /* Version 3.00 divisors must be a multiple of 2. */ 347 if (host->max_clk <= clock) { 348 div = 1; 349 } else { 350 for (div = 2; 351 div < SDHCI_MAX_DIV_SPEC_300; 352 div += 2) { 353 if ((host->max_clk / div) <= clock) 354 break; 355 } 356 } 357 div >>= 1; 358 } 359 } else { 360 /* Version 2.00 divisors must be a power of 2. */ 361 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { 362 if ((host->max_clk / div) <= clock) 363 break; 364 } 365 div >>= 1; 366 } 367 368 if (host->ops && host->ops->set_clock) 369 host->ops->set_clock(host, div); 370 371 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; 372 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) 373 << SDHCI_DIVIDER_HI_SHIFT; 374 clk |= SDHCI_CLOCK_INT_EN; 375 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 376 377 /* Wait max 20 ms */ 378 timeout = 20; 379 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 380 & SDHCI_CLOCK_INT_STABLE)) { 381 if (timeout == 0) { 382 printf("%s: Internal clock never stabilised.\n", 383 __func__); 384 return -EBUSY; 385 } 386 timeout--; 387 udelay(1000); 388 } 389 390 clk |= SDHCI_CLOCK_CARD_EN; 391 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 392 return 0; 393 } 394 395 static void sdhci_set_power(struct sdhci_host *host, unsigned short power) 396 { 397 u8 pwr = 0; 398 399 if (power != (unsigned short)-1) { 400 switch (1 << power) { 401 case MMC_VDD_165_195: 402 pwr = SDHCI_POWER_180; 403 break; 404 case MMC_VDD_29_30: 405 case MMC_VDD_30_31: 406 pwr = SDHCI_POWER_300; 407 break; 408 case MMC_VDD_32_33: 409 case MMC_VDD_33_34: 410 pwr = SDHCI_POWER_330; 411 break; 412 } 413 } 414 415 if (pwr == 0) { 416 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 417 return; 418 } 419 420 pwr |= SDHCI_POWER_ON; 421 422 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 423 } 424 425 #ifdef CONFIG_DM_MMC 426 static bool sdhci_card_busy(struct udevice *dev) 427 { 428 struct mmc *mmc = mmc_get_mmc_dev(dev); 429 #else 430 static bool sdhci_card_busy(struct mmc *mmc) 431 { 432 #endif 433 struct sdhci_host *host = mmc->priv; 434 u32 present_state; 435 436 /* Check whether DAT[0] is 0 */ 437 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); 438 439 return !(present_state & SDHCI_DATA_0_LVL); 440 } 441 442 #ifdef CONFIG_DM_MMC 443 static int sdhci_set_ios(struct udevice *dev) 444 { 445 struct mmc *mmc = mmc_get_mmc_dev(dev); 446 #else 447 static int sdhci_set_ios(struct mmc *mmc) 448 { 449 #endif 450 u32 ctrl; 451 struct sdhci_host *host = mmc->priv; 452 453 if (host->ops && host->ops->set_control_reg) 454 host->ops->set_control_reg(host); 455 456 if (mmc->clock != host->clock) 457 sdhci_set_clock(mmc, mmc->clock); 458 459 /* Set bus width */ 460 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 461 if (mmc->bus_width == 8) { 462 ctrl &= ~SDHCI_CTRL_4BITBUS; 463 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) || 464 (host->quirks & SDHCI_QUIRK_USE_WIDE8)) 465 ctrl |= SDHCI_CTRL_8BITBUS; 466 } else { 467 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) || 468 (host->quirks & SDHCI_QUIRK_USE_WIDE8)) 469 ctrl &= ~SDHCI_CTRL_8BITBUS; 470 if (mmc->bus_width == 4) 471 ctrl |= SDHCI_CTRL_4BITBUS; 472 else 473 ctrl &= ~SDHCI_CTRL_4BITBUS; 474 } 475 476 if (!(mmc->timing == MMC_TIMING_LEGACY) && 477 !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) 478 ctrl |= SDHCI_CTRL_HISPD; 479 else 480 ctrl &= ~SDHCI_CTRL_HISPD; 481 482 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 483 484 /* If available, call the driver specific "post" set_ios() function */ 485 if (host->ops && host->ops->set_ios_post) 486 host->ops->set_ios_post(host); 487 488 return 0; 489 } 490 491 static int sdhci_init(struct mmc *mmc) 492 { 493 struct sdhci_host *host = mmc->priv; 494 495 sdhci_reset(host, SDHCI_RESET_ALL); 496 497 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) { 498 aligned_buffer = memalign(8, 512*1024); 499 if (!aligned_buffer) { 500 printf("%s: Aligned buffer alloc failed!!!\n", 501 __func__); 502 return -ENOMEM; 503 } 504 } 505 506 sdhci_set_power(host, fls(mmc->cfg->voltages) - 1); 507 508 if (host->ops && host->ops->get_cd) 509 host->ops->get_cd(host); 510 511 /* Enable only interrupts served by the SD controller */ 512 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK, 513 SDHCI_INT_ENABLE); 514 /* Mask all sdhci interrupt sources */ 515 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE); 516 517 return 0; 518 } 519 520 #ifdef CONFIG_DM_MMC 521 int sdhci_probe(struct udevice *dev) 522 { 523 struct mmc *mmc = mmc_get_mmc_dev(dev); 524 525 return sdhci_init(mmc); 526 } 527 528 const struct dm_mmc_ops sdhci_ops = { 529 .card_busy = sdhci_card_busy, 530 .send_cmd = sdhci_send_command, 531 .set_ios = sdhci_set_ios, 532 }; 533 #else 534 static const struct mmc_ops sdhci_ops = { 535 .card_busy = sdhci_card_busy, 536 .send_cmd = sdhci_send_command, 537 .set_ios = sdhci_set_ios, 538 .init = sdhci_init, 539 }; 540 #endif 541 542 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, 543 u32 f_max, u32 f_min) 544 { 545 u32 caps, caps_1; 546 547 caps = sdhci_readl(host, SDHCI_CAPABILITIES); 548 549 #ifdef CONFIG_MMC_SDHCI_SDMA 550 if (!(caps & SDHCI_CAN_DO_SDMA)) { 551 printf("%s: Your controller doesn't support SDMA!!\n", 552 __func__); 553 return -EINVAL; 554 } 555 #endif 556 if (host->quirks & SDHCI_QUIRK_REG32_RW) 557 host->version = 558 sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16; 559 else 560 host->version = sdhci_readw(host, SDHCI_HOST_VERSION); 561 562 cfg->name = host->name; 563 #ifndef CONFIG_DM_MMC 564 cfg->ops = &sdhci_ops; 565 #endif 566 567 /* Check whether the clock multiplier is supported or not */ 568 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { 569 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); 570 host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >> 571 SDHCI_CLOCK_MUL_SHIFT; 572 } 573 574 if (host->max_clk == 0) { 575 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) 576 host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> 577 SDHCI_CLOCK_BASE_SHIFT; 578 else 579 host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >> 580 SDHCI_CLOCK_BASE_SHIFT; 581 host->max_clk *= 1000000; 582 if (host->clk_mul) 583 host->max_clk *= host->clk_mul; 584 } 585 if (host->max_clk == 0) { 586 printf("%s: Hardware doesn't specify base clock frequency\n", 587 __func__); 588 return -EINVAL; 589 } 590 if (f_max && (f_max < host->max_clk)) 591 cfg->f_max = f_max; 592 else 593 cfg->f_max = host->max_clk; 594 if (f_min) 595 cfg->f_min = f_min; 596 else { 597 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) 598 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300; 599 else 600 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200; 601 } 602 cfg->voltages = 0; 603 if (caps & SDHCI_CAN_VDD_330) 604 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34; 605 if (caps & SDHCI_CAN_VDD_300) 606 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31; 607 if (caps & SDHCI_CAN_VDD_180) 608 cfg->voltages |= MMC_VDD_165_195; 609 610 if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE) 611 cfg->voltages |= host->voltages; 612 613 cfg->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT; 614 615 /* Since Host Controller Version3.0 */ 616 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { 617 if (!(caps & SDHCI_CAN_DO_8BIT)) 618 cfg->host_caps &= ~MMC_MODE_8BIT; 619 } 620 621 if (host->host_caps) 622 cfg->host_caps |= host->host_caps; 623 624 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 625 626 return 0; 627 } 628 629 #ifdef CONFIG_BLK 630 int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg) 631 { 632 return mmc_bind(dev, mmc, cfg); 633 } 634 #else 635 int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min) 636 { 637 int ret; 638 639 ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min); 640 if (ret) 641 return ret; 642 643 host->mmc = mmc_create(&host->cfg, host); 644 if (host->mmc == NULL) { 645 printf("%s: mmc create fail!\n", __func__); 646 return -ENOMEM; 647 } 648 649 return 0; 650 } 651 #endif 652