1 /* 2 * Copyright 2011, Marvell Semiconductor Inc. 3 * Lei Wen <leiwen@marvell.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 * 7 * Back ported to the 8xx platform (from the 8260 platform) by 8 * Murray.Jensen@cmst.csiro.au, 27-Jan-01. 9 */ 10 11 #include <common.h> 12 #include <errno.h> 13 #include <malloc.h> 14 #include <mmc.h> 15 #include <sdhci.h> 16 17 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER) 18 void *aligned_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER; 19 #else 20 void *aligned_buffer; 21 #endif 22 23 static void sdhci_reset(struct sdhci_host *host, u8 mask) 24 { 25 unsigned long timeout; 26 27 /* Wait max 100 ms */ 28 timeout = 100; 29 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); 30 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { 31 if (timeout == 0) { 32 printf("%s: Reset 0x%x never completed.\n", 33 __func__, (int)mask); 34 return; 35 } 36 timeout--; 37 udelay(1000); 38 } 39 } 40 41 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd) 42 { 43 int i; 44 if (cmd->resp_type & MMC_RSP_136) { 45 /* CRC is stripped so we need to do some shifting. */ 46 for (i = 0; i < 4; i++) { 47 cmd->response[i] = sdhci_readl(host, 48 SDHCI_RESPONSE + (3-i)*4) << 8; 49 if (i != 3) 50 cmd->response[i] |= sdhci_readb(host, 51 SDHCI_RESPONSE + (3-i)*4-1); 52 } 53 } else { 54 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE); 55 } 56 } 57 58 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data) 59 { 60 int i; 61 char *offs; 62 for (i = 0; i < data->blocksize; i += 4) { 63 offs = data->dest + i; 64 if (data->flags == MMC_DATA_READ) 65 *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER); 66 else 67 sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER); 68 } 69 } 70 71 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data, 72 unsigned int start_addr) 73 { 74 unsigned int stat, rdy, mask, timeout, block = 0; 75 bool transfer_done = false; 76 #ifdef CONFIG_MMC_SDHCI_SDMA 77 unsigned char ctrl; 78 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 79 ctrl &= ~SDHCI_CTRL_DMA_MASK; 80 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 81 #endif 82 83 timeout = 1000000; 84 rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL; 85 mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE; 86 do { 87 stat = sdhci_readl(host, SDHCI_INT_STATUS); 88 if (stat & SDHCI_INT_ERROR) { 89 printf("%s: Error detected in status(0x%X)!\n", 90 __func__, stat); 91 return -EIO; 92 } 93 if (!transfer_done && (stat & rdy)) { 94 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask)) 95 continue; 96 sdhci_writel(host, rdy, SDHCI_INT_STATUS); 97 sdhci_transfer_pio(host, data); 98 data->dest += data->blocksize; 99 if (++block >= data->blocks) { 100 /* Keep looping until the SDHCI_INT_DATA_END is 101 * cleared, even if we finished sending all the 102 * blocks. 103 */ 104 transfer_done = true; 105 continue; 106 } 107 } 108 #ifdef CONFIG_MMC_SDHCI_SDMA 109 if (!transfer_done && (stat & SDHCI_INT_DMA_END)) { 110 sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS); 111 start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1); 112 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE; 113 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); 114 } 115 #endif 116 if (timeout-- > 0) 117 udelay(10); 118 else { 119 printf("%s: Transfer data timeout\n", __func__); 120 return -ETIMEDOUT; 121 } 122 } while (!(stat & SDHCI_INT_DATA_END)); 123 return 0; 124 } 125 126 /* 127 * No command will be sent by driver if card is busy, so driver must wait 128 * for card ready state. 129 * Every time when card is busy after timeout then (last) timeout value will be 130 * increased twice but only if it doesn't exceed global defined maximum. 131 * Each function call will use last timeout value. 132 */ 133 #define SDHCI_CMD_MAX_TIMEOUT 3200 134 #define SDHCI_CMD_DEFAULT_TIMEOUT 100 135 #define SDHCI_READ_STATUS_TIMEOUT 1000 136 137 #ifdef CONFIG_DM_MMC 138 static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd, 139 struct mmc_data *data) 140 { 141 struct mmc *mmc = mmc_get_mmc_dev(dev); 142 143 #else 144 static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, 145 struct mmc_data *data) 146 { 147 #endif 148 struct sdhci_host *host = mmc->priv; 149 unsigned int stat = 0; 150 int ret = 0; 151 int trans_bytes = 0, is_aligned = 1; 152 u32 mask, flags, mode; 153 unsigned int time = 0, start_addr = 0; 154 int mmc_dev = mmc_get_blk_desc(mmc)->devnum; 155 unsigned start = get_timer(0); 156 157 /* Timeout unit - ms */ 158 static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT; 159 160 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); 161 mask = SDHCI_CMD_INHIBIT; 162 163 if (data) 164 mask |= SDHCI_DATA_INHIBIT; 165 166 /* We shouldn't wait for data inihibit for stop commands, even 167 though they might use busy signaling */ 168 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 169 mask &= ~SDHCI_DATA_INHIBIT; 170 171 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 172 if (time >= cmd_timeout) { 173 printf("%s: MMC: %d busy ", __func__, mmc_dev); 174 if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) { 175 cmd_timeout += cmd_timeout; 176 printf("timeout increasing to: %u ms.\n", 177 cmd_timeout); 178 } else { 179 puts("timeout.\n"); 180 return -ECOMM; 181 } 182 } 183 time++; 184 udelay(1000); 185 } 186 187 mask = SDHCI_INT_RESPONSE; 188 if (!(cmd->resp_type & MMC_RSP_PRESENT)) 189 flags = SDHCI_CMD_RESP_NONE; 190 else if (cmd->resp_type & MMC_RSP_136) 191 flags = SDHCI_CMD_RESP_LONG; 192 else if (cmd->resp_type & MMC_RSP_BUSY) { 193 flags = SDHCI_CMD_RESP_SHORT_BUSY; 194 if (data) 195 mask |= SDHCI_INT_DATA_END; 196 } else 197 flags = SDHCI_CMD_RESP_SHORT; 198 199 if (cmd->resp_type & MMC_RSP_CRC) 200 flags |= SDHCI_CMD_CRC; 201 if (cmd->resp_type & MMC_RSP_OPCODE) 202 flags |= SDHCI_CMD_INDEX; 203 if (data) 204 flags |= SDHCI_CMD_DATA; 205 206 if (cmd->cmdidx == MMC_SEND_TUNING_BLOCK || 207 cmd->cmdidx == MMC_SEND_TUNING_BLOCK_HS200) { 208 mask &= ~SDHCI_INT_RESPONSE; 209 mask |= SDHCI_INT_DATA_AVAIL; 210 flags |= SDHCI_CMD_DATA; 211 } 212 213 /* Set Transfer mode regarding to data flag */ 214 if (data != 0) { 215 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); 216 mode = SDHCI_TRNS_BLK_CNT_EN; 217 trans_bytes = data->blocks * data->blocksize; 218 if (data->blocks > 1) 219 mode |= SDHCI_TRNS_MULTI; 220 221 if (data->flags == MMC_DATA_READ) 222 mode |= SDHCI_TRNS_READ; 223 224 #ifdef CONFIG_MMC_SDHCI_SDMA 225 if (data->flags == MMC_DATA_READ) 226 start_addr = (unsigned long)data->dest; 227 else 228 start_addr = (unsigned long)data->src; 229 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && 230 (start_addr & 0x7) != 0x0) { 231 is_aligned = 0; 232 start_addr = (unsigned long)aligned_buffer; 233 if (data->flags != MMC_DATA_READ) 234 memcpy(aligned_buffer, data->src, trans_bytes); 235 } 236 237 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER) 238 /* 239 * Always use this bounce-buffer when 240 * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined 241 */ 242 is_aligned = 0; 243 start_addr = (unsigned long)aligned_buffer; 244 if (data->flags != MMC_DATA_READ) 245 memcpy(aligned_buffer, data->src, trans_bytes); 246 #endif 247 248 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); 249 mode |= SDHCI_TRNS_DMA; 250 #endif 251 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 252 data->blocksize), 253 SDHCI_BLOCK_SIZE); 254 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); 255 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); 256 } else if (cmd->resp_type & MMC_RSP_BUSY) { 257 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); 258 } 259 260 sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT); 261 #ifdef CONFIG_MMC_SDHCI_SDMA 262 if (data != 0) { 263 trans_bytes = ALIGN(trans_bytes, CONFIG_SYS_CACHELINE_SIZE); 264 flush_cache(start_addr, trans_bytes); 265 } 266 #endif 267 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND); 268 start = get_timer(0); 269 do { 270 stat = sdhci_readl(host, SDHCI_INT_STATUS); 271 if (stat & SDHCI_INT_ERROR) 272 break; 273 274 if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) { 275 if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) { 276 return 0; 277 } else { 278 printf("%s: Timeout for status update!\n", 279 __func__); 280 return -ETIMEDOUT; 281 } 282 } 283 } while ((stat & mask) != mask); 284 285 if ((stat & (SDHCI_INT_ERROR | mask)) == mask) { 286 sdhci_cmd_done(host, cmd); 287 sdhci_writel(host, mask, SDHCI_INT_STATUS); 288 } else 289 ret = -1; 290 291 if (!ret && data) 292 ret = sdhci_transfer_data(host, data, start_addr); 293 294 if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD) 295 udelay(1000); 296 297 stat = sdhci_readl(host, SDHCI_INT_STATUS); 298 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); 299 if (!ret) { 300 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && 301 !is_aligned && (data->flags == MMC_DATA_READ)) 302 memcpy(data->dest, aligned_buffer, trans_bytes); 303 return 0; 304 } 305 306 sdhci_reset(host, SDHCI_RESET_CMD); 307 sdhci_reset(host, SDHCI_RESET_DATA); 308 if (stat & SDHCI_INT_TIMEOUT) 309 return -ETIMEDOUT; 310 else 311 return -ECOMM; 312 } 313 314 int sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 315 { 316 unsigned int div, clk = 0, timeout; 317 318 /* Wait max 20 ms */ 319 timeout = 200; 320 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & 321 (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) { 322 if (timeout == 0) { 323 printf("%s: Timeout to wait cmd & data inhibit\n", 324 __func__); 325 return -EBUSY; 326 } 327 328 timeout--; 329 udelay(100); 330 } 331 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 332 333 if (clock == 0) 334 return 0; 335 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { 336 /* 337 * Check if the Host Controller supports Programmable Clock 338 * Mode. 339 */ 340 if (host->clk_mul) { 341 for (div = 1; div <= 1024; div++) { 342 if ((host->max_clk / div) <= clock) 343 break; 344 } 345 346 /* 347 * Set Programmable Clock Mode in the Clock 348 * Control register. 349 */ 350 clk = SDHCI_PROG_CLOCK_MODE; 351 div--; 352 } else { 353 /* Version 3.00 divisors must be a multiple of 2. */ 354 if (host->max_clk <= clock) { 355 div = 1; 356 } else { 357 for (div = 2; 358 div < SDHCI_MAX_DIV_SPEC_300; 359 div += 2) { 360 if ((host->max_clk / div) <= clock) 361 break; 362 } 363 } 364 div >>= 1; 365 } 366 } else { 367 /* Version 2.00 divisors must be a power of 2. */ 368 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { 369 if ((host->max_clk / div) <= clock) 370 break; 371 } 372 div >>= 1; 373 } 374 if (host->ops && host->ops->set_clock_ext) 375 host->ops->set_clock_ext(host, div); 376 377 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; 378 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) 379 << SDHCI_DIVIDER_HI_SHIFT; 380 clk |= SDHCI_CLOCK_INT_EN; 381 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 382 383 /* Wait max 20 ms */ 384 timeout = 20; 385 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 386 & SDHCI_CLOCK_INT_STABLE)) { 387 if (timeout == 0) { 388 printf("%s: Internal clock never stabilised.\n", 389 __func__); 390 return -EBUSY; 391 } 392 timeout--; 393 udelay(1000); 394 } 395 clk |= SDHCI_CLOCK_CARD_EN; 396 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 397 398 host->clock = clock; 399 return 0; 400 } 401 402 static void sdhci_set_power(struct sdhci_host *host, unsigned short power) 403 { 404 u8 pwr = 0; 405 406 if (power != (unsigned short)-1) { 407 switch (1 << power) { 408 case MMC_VDD_165_195: 409 pwr = SDHCI_POWER_180; 410 break; 411 case MMC_VDD_29_30: 412 case MMC_VDD_30_31: 413 pwr = SDHCI_POWER_300; 414 break; 415 case MMC_VDD_32_33: 416 case MMC_VDD_33_34: 417 pwr = SDHCI_POWER_330; 418 break; 419 } 420 } 421 422 if (pwr == 0) { 423 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 424 return; 425 } 426 427 pwr |= SDHCI_POWER_ON; 428 429 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 430 } 431 432 static void sdhci_set_uhs_signaling(struct sdhci_host *host) 433 { 434 u16 ctrl_2; 435 u32 timing = host->mmc->timing; 436 437 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 438 /* Select Bus Speed Mode for host */ 439 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 440 441 if ((timing != MMC_TIMING_LEGACY) && 442 (timing != MMC_TIMING_MMC_HS) && 443 (timing != MMC_TIMING_SD_HS)) 444 ctrl_2 |= SDHCI_CTRL_VDD_180; 445 446 if ((timing == MMC_TIMING_MMC_HS200) || 447 (timing == MMC_TIMING_UHS_SDR104)) 448 ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_DRV_TYPE_A; 449 else if (timing == MMC_TIMING_UHS_SDR12) 450 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 451 else if (timing == MMC_TIMING_UHS_SDR25) 452 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 453 else if (timing == MMC_TIMING_UHS_SDR50) 454 ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 455 else if ((timing == MMC_TIMING_UHS_DDR50) || 456 (timing == MMC_TIMING_MMC_DDR52)) 457 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 458 else if (timing == MMC_TIMING_MMC_HS400 || 459 timing == MMC_TIMING_MMC_HS400ES) 460 ctrl_2 |= SDHCI_CTRL_HS400 | SDHCI_CTRL_DRV_TYPE_A; 461 462 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 463 } 464 465 #ifdef CONFIG_DM_MMC 466 static bool sdhci_card_busy(struct udevice *dev) 467 { 468 struct mmc *mmc = mmc_get_mmc_dev(dev); 469 #else 470 static bool sdhci_card_busy(struct mmc *mmc) 471 { 472 #endif 473 struct sdhci_host *host = mmc->priv; 474 u32 present_state; 475 476 /* Check whether DAT[0] is 0 */ 477 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); 478 479 return !(present_state & SDHCI_DATA_0_LVL); 480 } 481 482 #ifdef CONFIG_DM_MMC 483 static int sdhci_set_ios(struct udevice *dev) 484 { 485 struct mmc *mmc = mmc_get_mmc_dev(dev); 486 #else 487 static int sdhci_set_ios(struct mmc *mmc) 488 { 489 #endif 490 u32 ctrl; 491 struct sdhci_host *host = mmc->priv; 492 493 if (host->ops && host->ops->set_control_reg) 494 host->ops->set_control_reg(host); 495 496 if (mmc->clock != host->clock) { 497 if (host->ops && host->ops->set_clock) 498 host->ops->set_clock(host, mmc->clock); 499 else 500 sdhci_set_clock(host, mmc->clock); 501 } 502 503 /* Set bus width */ 504 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 505 if (mmc->bus_width == 8) { 506 ctrl &= ~SDHCI_CTRL_4BITBUS; 507 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) || 508 (host->quirks & SDHCI_QUIRK_USE_WIDE8)) 509 ctrl |= SDHCI_CTRL_8BITBUS; 510 } else { 511 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) || 512 (host->quirks & SDHCI_QUIRK_USE_WIDE8)) 513 ctrl &= ~SDHCI_CTRL_8BITBUS; 514 if (mmc->bus_width == 4) 515 ctrl |= SDHCI_CTRL_4BITBUS; 516 else 517 ctrl &= ~SDHCI_CTRL_4BITBUS; 518 } 519 520 if (!(mmc->timing == MMC_TIMING_LEGACY) && 521 !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) 522 ctrl |= SDHCI_CTRL_HISPD; 523 else 524 ctrl &= ~SDHCI_CTRL_HISPD; 525 526 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 527 528 if ((mmc->timing != MMC_TIMING_LEGACY) && 529 (mmc->timing != MMC_TIMING_MMC_HS) && 530 (mmc->timing != MMC_TIMING_SD_HS)) 531 sdhci_set_power(host, MMC_VDD_165_195_SHIFT); 532 533 sdhci_set_uhs_signaling(host); 534 535 /* If available, call the driver specific "post" set_ios() function */ 536 if (host->ops && host->ops->set_ios_post) 537 host->ops->set_ios_post(host); 538 539 return 0; 540 } 541 542 static int sdhci_init(struct mmc *mmc) 543 { 544 struct sdhci_host *host = mmc->priv; 545 546 sdhci_reset(host, SDHCI_RESET_ALL); 547 548 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) { 549 aligned_buffer = memalign(8, 512*1024); 550 if (!aligned_buffer) { 551 printf("%s: Aligned buffer alloc failed!!!\n", 552 __func__); 553 return -ENOMEM; 554 } 555 } 556 557 sdhci_set_power(host, fls(mmc->cfg->voltages) - 1); 558 559 if (host->ops && host->ops->get_cd) 560 host->ops->get_cd(host); 561 562 /* Enable only interrupts served by the SD controller */ 563 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK, 564 SDHCI_INT_ENABLE); 565 /* Mask all sdhci interrupt sources */ 566 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE); 567 568 return 0; 569 } 570 571 static int sdhci_send_tuning(struct sdhci_host *host, u32 opcode) 572 { 573 struct mmc_cmd cmd; 574 575 cmd.cmdidx = opcode; 576 cmd.resp_type = MMC_RSP_R1; 577 cmd.cmdarg = 0; 578 /* 579 * In response to CMD19, the card sends 64 bytes of tuning 580 * block to the Host Controller. So we set the block size 581 * to 64 here. 582 */ 583 if (opcode == MMC_SEND_TUNING_BLOCK_HS200 && 584 host->mmc->bus_width == MMC_BUS_WIDTH_8BIT) 585 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128), SDHCI_BLOCK_SIZE); 586 else 587 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE); 588 589 /* 590 * The tuning block is sent by the card to the host controller. 591 * So we set the TRNS_READ bit in the Transfer Mode register. 592 * This also takes care of setting DMA Enable and Multi Block 593 * Select in the same register to 0. 594 */ 595 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); 596 597 #ifdef CONFIG_DM_MMC 598 return sdhci_send_command(host->mmc->dev, &cmd, NULL); 599 #else 600 return sdhci_send_command(host->mmc, &cmd, NULL); 601 #endif 602 } 603 604 #define MAX_TUNING_LOOP 40 605 static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) 606 { 607 int i; 608 int ret; 609 610 /* 611 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number 612 * of loops reaches 40 times. 613 */ 614 for (i = 0; i < MAX_TUNING_LOOP; i++) { 615 u16 ctrl; 616 617 ret = sdhci_send_tuning(host, opcode); 618 619 if (ret) 620 return ret; 621 622 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 623 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) { 624 if (ctrl & SDHCI_CTRL_TUNED_CLK) 625 /* Tuning successfully */ 626 return 0; 627 break; 628 } 629 } 630 631 return -ETIMEDOUT; 632 } 633 634 #ifdef CONFIG_DM_MMC 635 static int sdhci_execute_tuning(struct udevice *dev, u32 opcode) 636 { 637 struct mmc *mmc = mmc_get_mmc_dev(dev); 638 #else 639 static int sdhci_execute_tuning(struct mmc *mmc, u32 opcode) 640 { 641 #endif 642 struct sdhci_host *host = mmc->priv; 643 u16 ctrl; 644 645 /* 646 * The Host Controller needs tuning in case of SDR104 and DDR50 647 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in 648 * the Capabilities register. 649 * If the Host Controller supports the HS200 mode then the 650 * tuning function has to be executed. 651 */ 652 switch (mmc->timing) { 653 /* HS400 tuning is done in HS200 mode */ 654 case MMC_TIMING_MMC_HS400: 655 return -EINVAL; 656 case MMC_TIMING_MMC_HS200: 657 /* 658 * Periodic re-tuning for HS400 is not expected to be needed, so 659 * disable it here. 660 */ 661 break; 662 default: 663 return -EINVAL; 664 } 665 666 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 667 ctrl |= SDHCI_CTRL_EXEC_TUNING; 668 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 669 670 return __sdhci_execute_tuning(host, opcode); 671 } 672 673 #ifdef CONFIG_DM_MMC 674 int sdhci_probe(struct udevice *dev) 675 { 676 struct mmc *mmc = mmc_get_mmc_dev(dev); 677 678 return sdhci_init(mmc); 679 } 680 681 const struct dm_mmc_ops sdhci_ops = { 682 .card_busy = sdhci_card_busy, 683 .send_cmd = sdhci_send_command, 684 .set_ios = sdhci_set_ios, 685 .execute_tuning = sdhci_execute_tuning, 686 }; 687 #else 688 static const struct mmc_ops sdhci_ops = { 689 .card_busy = sdhci_card_busy, 690 .send_cmd = sdhci_send_command, 691 .set_ios = sdhci_set_ios, 692 .init = sdhci_init, 693 .execute_tuning = sdhci_execute_tuning, 694 }; 695 #endif 696 697 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, 698 u32 f_max, u32 f_min) 699 { 700 u32 caps, caps_1; 701 702 caps = sdhci_readl(host, SDHCI_CAPABILITIES); 703 704 #ifdef CONFIG_MMC_SDHCI_SDMA 705 if (!(caps & SDHCI_CAN_DO_SDMA)) { 706 printf("%s: Your controller doesn't support SDMA!!\n", 707 __func__); 708 return -EINVAL; 709 } 710 #endif 711 if (host->quirks & SDHCI_QUIRK_REG32_RW) 712 host->version = 713 sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16; 714 else 715 host->version = sdhci_readw(host, SDHCI_HOST_VERSION); 716 717 cfg->name = host->name; 718 #ifndef CONFIG_DM_MMC 719 cfg->ops = &sdhci_ops; 720 #endif 721 722 /* Check whether the clock multiplier is supported or not */ 723 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { 724 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); 725 host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >> 726 SDHCI_CLOCK_MUL_SHIFT; 727 } 728 729 if (host->max_clk == 0) { 730 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) 731 host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> 732 SDHCI_CLOCK_BASE_SHIFT; 733 else 734 host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >> 735 SDHCI_CLOCK_BASE_SHIFT; 736 host->max_clk *= 1000000; 737 if (host->clk_mul) 738 host->max_clk *= host->clk_mul; 739 } 740 if (host->max_clk == 0) { 741 printf("%s: Hardware doesn't specify base clock frequency\n", 742 __func__); 743 return -EINVAL; 744 } 745 if (f_max && (f_max < host->max_clk)) 746 cfg->f_max = f_max; 747 else 748 cfg->f_max = host->max_clk; 749 if (f_min) 750 cfg->f_min = f_min; 751 else { 752 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) 753 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300; 754 else 755 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200; 756 } 757 cfg->voltages = 0; 758 if (caps & SDHCI_CAN_VDD_330) 759 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34; 760 if (caps & SDHCI_CAN_VDD_300) 761 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31; 762 if (caps & SDHCI_CAN_VDD_180) 763 cfg->voltages |= MMC_VDD_165_195; 764 765 if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE) 766 cfg->voltages |= host->voltages; 767 768 cfg->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT; 769 770 /* Since Host Controller Version3.0 */ 771 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { 772 if (!(caps & SDHCI_CAN_DO_8BIT)) 773 cfg->host_caps &= ~MMC_MODE_8BIT; 774 } 775 776 if (host->host_caps) 777 cfg->host_caps |= host->host_caps; 778 779 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 780 781 return 0; 782 } 783 784 #ifdef CONFIG_BLK 785 int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg) 786 { 787 return mmc_bind(dev, mmc, cfg); 788 } 789 #else 790 int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min) 791 { 792 int ret; 793 794 ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min); 795 if (ret) 796 return ret; 797 798 host->mmc = mmc_create(&host->cfg, host); 799 if (host->mmc == NULL) { 800 printf("%s: mmc create fail!\n", __func__); 801 return -ENOMEM; 802 } 803 804 return 0; 805 } 806 #endif 807