1 /* 2 * Copyright 2011, Marvell Semiconductor Inc. 3 * Lei Wen <leiwen@marvell.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 * 7 * Back ported to the 8xx platform (from the 8260 platform) by 8 * Murray.Jensen@cmst.csiro.au, 27-Jan-01. 9 */ 10 11 #include <common.h> 12 #include <errno.h> 13 #include <malloc.h> 14 #include <mmc.h> 15 #include <sdhci.h> 16 17 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER) 18 void *aligned_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER; 19 #else 20 void *aligned_buffer; 21 #endif 22 23 static void sdhci_reset(struct sdhci_host *host, u8 mask) 24 { 25 unsigned long timeout; 26 27 /* Wait max 100 ms */ 28 timeout = 100; 29 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); 30 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { 31 if (timeout == 0) { 32 printf("%s: Reset 0x%x never completed.\n", 33 __func__, (int)mask); 34 return; 35 } 36 timeout--; 37 udelay(1000); 38 } 39 } 40 41 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd) 42 { 43 int i; 44 if (cmd->resp_type & MMC_RSP_136) { 45 /* CRC is stripped so we need to do some shifting. */ 46 for (i = 0; i < 4; i++) { 47 cmd->response[i] = sdhci_readl(host, 48 SDHCI_RESPONSE + (3-i)*4) << 8; 49 if (i != 3) 50 cmd->response[i] |= sdhci_readb(host, 51 SDHCI_RESPONSE + (3-i)*4-1); 52 } 53 } else { 54 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE); 55 } 56 } 57 58 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data) 59 { 60 int i; 61 char *offs; 62 for (i = 0; i < data->blocksize; i += 4) { 63 offs = data->dest + i; 64 if (data->flags == MMC_DATA_READ) 65 *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER); 66 else 67 sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER); 68 } 69 } 70 71 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data, 72 unsigned int start_addr) 73 { 74 unsigned int stat, rdy, mask, timeout, block = 0; 75 bool transfer_done = false; 76 #ifdef CONFIG_MMC_SDHCI_SDMA 77 unsigned char ctrl; 78 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 79 ctrl &= ~SDHCI_CTRL_DMA_MASK; 80 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 81 #endif 82 83 timeout = 1000000; 84 rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL; 85 mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE; 86 do { 87 stat = sdhci_readl(host, SDHCI_INT_STATUS); 88 if (stat & SDHCI_INT_ERROR) { 89 printf("%s: Error detected in status(0x%X)!\n", 90 __func__, stat); 91 return -EIO; 92 } 93 if (!transfer_done && (stat & rdy)) { 94 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask)) 95 continue; 96 sdhci_writel(host, rdy, SDHCI_INT_STATUS); 97 sdhci_transfer_pio(host, data); 98 data->dest += data->blocksize; 99 if (++block >= data->blocks) { 100 /* Keep looping until the SDHCI_INT_DATA_END is 101 * cleared, even if we finished sending all the 102 * blocks. 103 */ 104 transfer_done = true; 105 continue; 106 } 107 } 108 #ifdef CONFIG_MMC_SDHCI_SDMA 109 if (!transfer_done && (stat & SDHCI_INT_DMA_END)) { 110 sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS); 111 start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1); 112 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE; 113 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); 114 } 115 #endif 116 if (timeout-- > 0) 117 udelay(10); 118 else { 119 printf("%s: Transfer data timeout\n", __func__); 120 return -ETIMEDOUT; 121 } 122 } while (!(stat & SDHCI_INT_DATA_END)); 123 return 0; 124 } 125 126 /* 127 * No command will be sent by driver if card is busy, so driver must wait 128 * for card ready state. 129 * Every time when card is busy after timeout then (last) timeout value will be 130 * increased twice but only if it doesn't exceed global defined maximum. 131 * Each function call will use last timeout value. 132 */ 133 #define SDHCI_CMD_MAX_TIMEOUT 3200 134 #define SDHCI_CMD_DEFAULT_TIMEOUT 100 135 #define SDHCI_READ_STATUS_TIMEOUT 1000 136 137 #ifdef CONFIG_DM_MMC 138 static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd, 139 struct mmc_data *data) 140 { 141 struct mmc *mmc = mmc_get_mmc_dev(dev); 142 143 #else 144 static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, 145 struct mmc_data *data) 146 { 147 #endif 148 struct sdhci_host *host = mmc->priv; 149 unsigned int stat = 0; 150 int ret = 0; 151 int trans_bytes = 0, is_aligned = 1; 152 u32 mask, flags, mode; 153 unsigned int time = 0, start_addr = 0; 154 int mmc_dev = mmc_get_blk_desc(mmc)->devnum; 155 unsigned start = get_timer(0); 156 157 /* Timeout unit - ms */ 158 static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT; 159 160 mask = SDHCI_CMD_INHIBIT; 161 162 if (data) 163 mask |= SDHCI_DATA_INHIBIT; 164 165 /* We shouldn't wait for data inihibit for stop commands, even 166 though they might use busy signaling */ 167 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 168 mask &= ~SDHCI_DATA_INHIBIT; 169 170 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 171 if (time >= cmd_timeout) { 172 printf("%s: MMC: %d busy ", __func__, mmc_dev); 173 if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) { 174 cmd_timeout += cmd_timeout; 175 printf("timeout increasing to: %u ms.\n", 176 cmd_timeout); 177 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); 178 } else { 179 puts("timeout.\n"); 180 /* remove timeout return error and try to send command */ 181 break; 182 } 183 } 184 time++; 185 udelay(1000); 186 } 187 188 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); 189 190 mask = SDHCI_INT_RESPONSE; 191 if (!(cmd->resp_type & MMC_RSP_PRESENT)) 192 flags = SDHCI_CMD_RESP_NONE; 193 else if (cmd->resp_type & MMC_RSP_136) 194 flags = SDHCI_CMD_RESP_LONG; 195 else if (cmd->resp_type & MMC_RSP_BUSY) { 196 flags = SDHCI_CMD_RESP_SHORT_BUSY; 197 if (data) 198 mask |= SDHCI_INT_DATA_END; 199 } else 200 flags = SDHCI_CMD_RESP_SHORT; 201 202 if (cmd->resp_type & MMC_RSP_CRC) 203 flags |= SDHCI_CMD_CRC; 204 if (cmd->resp_type & MMC_RSP_OPCODE) 205 flags |= SDHCI_CMD_INDEX; 206 if (data) 207 flags |= SDHCI_CMD_DATA; 208 209 if (cmd->cmdidx == MMC_SEND_TUNING_BLOCK || 210 cmd->cmdidx == MMC_SEND_TUNING_BLOCK_HS200) { 211 mask &= ~SDHCI_INT_RESPONSE; 212 mask |= SDHCI_INT_DATA_AVAIL; 213 flags |= SDHCI_CMD_DATA; 214 } 215 216 /* Set Transfer mode regarding to data flag */ 217 if (data != 0) { 218 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); 219 mode = SDHCI_TRNS_BLK_CNT_EN; 220 trans_bytes = data->blocks * data->blocksize; 221 if (data->blocks > 1) 222 mode |= SDHCI_TRNS_MULTI; 223 224 if (data->flags == MMC_DATA_READ) 225 mode |= SDHCI_TRNS_READ; 226 227 #ifdef CONFIG_MMC_SDHCI_SDMA 228 if (data->flags == MMC_DATA_READ) 229 start_addr = (unsigned long)data->dest; 230 else 231 start_addr = (unsigned long)data->src; 232 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && 233 (start_addr & 0x7) != 0x0) { 234 is_aligned = 0; 235 start_addr = (unsigned long)aligned_buffer; 236 if (data->flags != MMC_DATA_READ) 237 memcpy(aligned_buffer, data->src, trans_bytes); 238 } 239 240 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER) 241 /* 242 * Always use this bounce-buffer when 243 * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined 244 */ 245 is_aligned = 0; 246 start_addr = (unsigned long)aligned_buffer; 247 if (data->flags != MMC_DATA_READ) 248 memcpy(aligned_buffer, data->src, trans_bytes); 249 #endif 250 251 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); 252 mode |= SDHCI_TRNS_DMA; 253 #endif 254 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 255 data->blocksize), 256 SDHCI_BLOCK_SIZE); 257 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); 258 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); 259 } else if (cmd->resp_type & MMC_RSP_BUSY) { 260 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); 261 } 262 263 sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT); 264 #ifdef CONFIG_MMC_SDHCI_SDMA 265 if (data != 0) { 266 trans_bytes = ALIGN(trans_bytes, CONFIG_SYS_CACHELINE_SIZE); 267 flush_cache(start_addr, trans_bytes); 268 } 269 #endif 270 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND); 271 start = get_timer(0); 272 do { 273 stat = sdhci_readl(host, SDHCI_INT_STATUS); 274 if (stat & SDHCI_INT_ERROR) 275 break; 276 277 if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) { 278 if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) { 279 return 0; 280 } else { 281 printf("%s: Timeout for status update!\n", 282 __func__); 283 return -ETIMEDOUT; 284 } 285 } 286 } while ((stat & mask) != mask); 287 288 if ((stat & (SDHCI_INT_ERROR | mask)) == mask) { 289 sdhci_cmd_done(host, cmd); 290 sdhci_writel(host, mask, SDHCI_INT_STATUS); 291 } else 292 ret = -1; 293 294 if (!ret && data) 295 ret = sdhci_transfer_data(host, data, start_addr); 296 297 if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD) 298 udelay(1000); 299 300 stat = sdhci_readl(host, SDHCI_INT_STATUS); 301 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); 302 if (!ret) { 303 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && 304 !is_aligned && (data->flags == MMC_DATA_READ)) 305 memcpy(data->dest, aligned_buffer, trans_bytes); 306 return 0; 307 } 308 309 sdhci_reset(host, SDHCI_RESET_CMD); 310 sdhci_reset(host, SDHCI_RESET_DATA); 311 if (stat & SDHCI_INT_TIMEOUT) 312 return -ETIMEDOUT; 313 else 314 return -ECOMM; 315 } 316 317 int sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 318 { 319 unsigned int div, clk = 0, timeout; 320 321 /* Wait max 20 ms */ 322 timeout = 200; 323 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & 324 (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) { 325 if (timeout == 0) { 326 printf("%s: Timeout to wait cmd & data inhibit\n", 327 __func__); 328 return -EBUSY; 329 } 330 331 timeout--; 332 udelay(100); 333 } 334 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 335 336 if (clock == 0) 337 return 0; 338 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { 339 /* 340 * Check if the Host Controller supports Programmable Clock 341 * Mode. 342 */ 343 if (host->clk_mul) { 344 for (div = 1; div <= 1024; div++) { 345 if ((host->max_clk / div) <= clock) 346 break; 347 } 348 349 /* 350 * Set Programmable Clock Mode in the Clock 351 * Control register. 352 */ 353 clk = SDHCI_PROG_CLOCK_MODE; 354 div--; 355 } else { 356 /* Version 3.00 divisors must be a multiple of 2. */ 357 if (host->max_clk <= clock) { 358 div = 1; 359 } else { 360 for (div = 2; 361 div < SDHCI_MAX_DIV_SPEC_300; 362 div += 2) { 363 if ((host->max_clk / div) <= clock) 364 break; 365 } 366 } 367 div >>= 1; 368 } 369 } else { 370 /* Version 2.00 divisors must be a power of 2. */ 371 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { 372 if ((host->max_clk / div) <= clock) 373 break; 374 } 375 div >>= 1; 376 } 377 if (host->ops && host->ops->set_clock_ext) 378 host->ops->set_clock_ext(host, div); 379 380 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; 381 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) 382 << SDHCI_DIVIDER_HI_SHIFT; 383 clk |= SDHCI_CLOCK_INT_EN; 384 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 385 386 /* Wait max 20 ms */ 387 timeout = 20; 388 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 389 & SDHCI_CLOCK_INT_STABLE)) { 390 if (timeout == 0) { 391 printf("%s: Internal clock never stabilised.\n", 392 __func__); 393 return -EBUSY; 394 } 395 timeout--; 396 udelay(1000); 397 } 398 clk |= SDHCI_CLOCK_CARD_EN; 399 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 400 401 host->clock = clock; 402 return 0; 403 } 404 405 static void sdhci_set_power(struct sdhci_host *host, unsigned short power) 406 { 407 u8 pwr = 0; 408 409 if (power != (unsigned short)-1) { 410 switch (1 << power) { 411 case MMC_VDD_165_195: 412 pwr = SDHCI_POWER_180; 413 break; 414 case MMC_VDD_29_30: 415 case MMC_VDD_30_31: 416 pwr = SDHCI_POWER_300; 417 break; 418 case MMC_VDD_32_33: 419 case MMC_VDD_33_34: 420 pwr = SDHCI_POWER_330; 421 break; 422 } 423 } 424 425 if (pwr == 0) { 426 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 427 return; 428 } 429 430 pwr |= SDHCI_POWER_ON; 431 432 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 433 } 434 435 static void sdhci_set_uhs_signaling(struct sdhci_host *host) 436 { 437 u16 ctrl_2; 438 u32 timing = host->mmc->timing; 439 440 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 441 /* Select Bus Speed Mode for host */ 442 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 443 444 if ((timing != MMC_TIMING_LEGACY) && 445 (timing != MMC_TIMING_MMC_HS) && 446 (timing != MMC_TIMING_SD_HS)) 447 ctrl_2 |= SDHCI_CTRL_VDD_180; 448 449 if ((timing == MMC_TIMING_MMC_HS200) || 450 (timing == MMC_TIMING_UHS_SDR104)) 451 ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_DRV_TYPE_A; 452 else if (timing == MMC_TIMING_UHS_SDR12) 453 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 454 else if (timing == MMC_TIMING_UHS_SDR25) 455 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 456 else if ((timing == MMC_TIMING_UHS_SDR50) || 457 (timing == MMC_TIMING_MMC_HS)) 458 ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 459 else if ((timing == MMC_TIMING_UHS_DDR50) || 460 (timing == MMC_TIMING_MMC_DDR52)) 461 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 462 else if (timing == MMC_TIMING_MMC_HS400 || 463 timing == MMC_TIMING_MMC_HS400ES) 464 ctrl_2 |= SDHCI_CTRL_HS400 | SDHCI_CTRL_DRV_TYPE_A; 465 466 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 467 } 468 469 #ifdef CONFIG_DM_MMC 470 static bool sdhci_card_busy(struct udevice *dev) 471 { 472 struct mmc *mmc = mmc_get_mmc_dev(dev); 473 #else 474 static bool sdhci_card_busy(struct mmc *mmc) 475 { 476 #endif 477 struct sdhci_host *host = mmc->priv; 478 u32 present_state; 479 480 /* Check whether DAT[0] is 0 */ 481 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); 482 483 return !(present_state & SDHCI_DATA_0_LVL); 484 } 485 486 #ifdef CONFIG_DM_MMC 487 static int sdhci_set_ios(struct udevice *dev) 488 { 489 struct mmc *mmc = mmc_get_mmc_dev(dev); 490 #else 491 static int sdhci_set_ios(struct mmc *mmc) 492 { 493 #endif 494 u32 ctrl; 495 struct sdhci_host *host = mmc->priv; 496 497 if (host->ops && host->ops->set_control_reg) 498 host->ops->set_control_reg(host); 499 500 if (mmc->clock != host->clock) { 501 if (host->ops && host->ops->set_clock) 502 host->ops->set_clock(host, mmc->clock); 503 else 504 sdhci_set_clock(host, mmc->clock); 505 } 506 507 /* Set bus width */ 508 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 509 if (mmc->bus_width == 8) { 510 ctrl &= ~SDHCI_CTRL_4BITBUS; 511 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) || 512 (host->quirks & SDHCI_QUIRK_USE_WIDE8)) 513 ctrl |= SDHCI_CTRL_8BITBUS; 514 } else { 515 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) || 516 (host->quirks & SDHCI_QUIRK_USE_WIDE8)) 517 ctrl &= ~SDHCI_CTRL_8BITBUS; 518 if (mmc->bus_width == 4) 519 ctrl |= SDHCI_CTRL_4BITBUS; 520 else 521 ctrl &= ~SDHCI_CTRL_4BITBUS; 522 } 523 524 if (!(mmc->timing == MMC_TIMING_LEGACY) && 525 !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) 526 ctrl |= SDHCI_CTRL_HISPD; 527 else 528 ctrl &= ~SDHCI_CTRL_HISPD; 529 530 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 531 532 if ((mmc->timing != MMC_TIMING_LEGACY) && 533 (mmc->timing != MMC_TIMING_MMC_HS) && 534 (mmc->timing != MMC_TIMING_SD_HS)) 535 sdhci_set_power(host, MMC_VDD_165_195_SHIFT); 536 537 sdhci_set_uhs_signaling(host); 538 539 /* If available, call the driver specific "post" set_ios() function */ 540 if (host->ops && host->ops->set_ios_post) 541 host->ops->set_ios_post(host); 542 543 return 0; 544 } 545 546 static int sdhci_init(struct mmc *mmc) 547 { 548 struct sdhci_host *host = mmc->priv; 549 550 sdhci_reset(host, SDHCI_RESET_ALL); 551 552 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) { 553 aligned_buffer = memalign(8, 512*1024); 554 if (!aligned_buffer) { 555 printf("%s: Aligned buffer alloc failed!!!\n", 556 __func__); 557 return -ENOMEM; 558 } 559 } 560 561 sdhci_set_power(host, fls(mmc->cfg->voltages) - 1); 562 563 if (host->ops && host->ops->get_cd) 564 host->ops->get_cd(host); 565 566 /* Enable only interrupts served by the SD controller */ 567 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK, 568 SDHCI_INT_ENABLE); 569 /* Mask all sdhci interrupt sources */ 570 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE); 571 572 return 0; 573 } 574 575 static int sdhci_send_tuning(struct sdhci_host *host, u32 opcode) 576 { 577 struct mmc_cmd cmd; 578 579 cmd.cmdidx = opcode; 580 cmd.resp_type = MMC_RSP_R1; 581 cmd.cmdarg = 0; 582 /* 583 * In response to CMD19, the card sends 64 bytes of tuning 584 * block to the Host Controller. So we set the block size 585 * to 64 here. 586 */ 587 if (opcode == MMC_SEND_TUNING_BLOCK_HS200 && 588 host->mmc->bus_width == MMC_BUS_WIDTH_8BIT) 589 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128), SDHCI_BLOCK_SIZE); 590 else 591 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE); 592 593 /* 594 * The tuning block is sent by the card to the host controller. 595 * So we set the TRNS_READ bit in the Transfer Mode register. 596 * This also takes care of setting DMA Enable and Multi Block 597 * Select in the same register to 0. 598 */ 599 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); 600 601 #ifdef CONFIG_DM_MMC 602 return sdhci_send_command(host->mmc->dev, &cmd, NULL); 603 #else 604 return sdhci_send_command(host->mmc, &cmd, NULL); 605 #endif 606 } 607 608 #define MAX_TUNING_LOOP 40 609 static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) 610 { 611 int i; 612 int ret; 613 614 /* 615 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number 616 * of loops reaches 40 times. 617 */ 618 for (i = 0; i < MAX_TUNING_LOOP; i++) { 619 u16 ctrl; 620 621 ret = sdhci_send_tuning(host, opcode); 622 623 if (ret) 624 return ret; 625 626 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 627 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) { 628 if (ctrl & SDHCI_CTRL_TUNED_CLK) 629 /* Tuning successfully */ 630 return 0; 631 break; 632 } 633 } 634 635 return -ETIMEDOUT; 636 } 637 638 #ifdef CONFIG_DM_MMC 639 static int sdhci_execute_tuning(struct udevice *dev, u32 opcode) 640 { 641 struct mmc *mmc = mmc_get_mmc_dev(dev); 642 #else 643 static int sdhci_execute_tuning(struct mmc *mmc, u32 opcode) 644 { 645 #endif 646 struct sdhci_host *host = mmc->priv; 647 int ret; 648 u16 ctrl; 649 650 /* 651 * The Host Controller needs tuning in case of SDR104 and DDR50 652 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in 653 * the Capabilities register. 654 * If the Host Controller supports the HS200 mode then the 655 * tuning function has to be executed. 656 */ 657 switch (mmc->timing) { 658 /* HS400 tuning is done in HS200 mode */ 659 case MMC_TIMING_MMC_HS400: 660 return -EINVAL; 661 case MMC_TIMING_MMC_HS200: 662 /* 663 * Periodic re-tuning for HS400 is not expected to be needed, so 664 * disable it here. 665 */ 666 break; 667 default: 668 return -EINVAL; 669 } 670 671 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 672 ctrl |= SDHCI_CTRL_EXEC_TUNING; 673 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 674 675 ret = __sdhci_execute_tuning(host, opcode); 676 677 if (!ret && host->ops && host->ops->execute_tuning_end) 678 host->ops->execute_tuning_end(host); 679 680 return ret; 681 } 682 683 #ifdef CONFIG_DM_MMC 684 int sdhci_probe(struct udevice *dev) 685 { 686 struct mmc *mmc = mmc_get_mmc_dev(dev); 687 688 return sdhci_init(mmc); 689 } 690 691 static int sdhci_set_enhanced_strobe(struct udevice *dev) 692 { 693 struct mmc *mmc = mmc_get_mmc_dev(dev); 694 struct sdhci_host *host = mmc->priv; 695 696 if (host->ops && host->ops->set_enhanced_strobe) 697 return host->ops->set_enhanced_strobe(host); 698 699 return -ENOTSUPP; 700 } 701 702 const struct dm_mmc_ops sdhci_ops = { 703 .card_busy = sdhci_card_busy, 704 .send_cmd = sdhci_send_command, 705 .set_ios = sdhci_set_ios, 706 .execute_tuning = sdhci_execute_tuning, 707 .set_enhanced_strobe = sdhci_set_enhanced_strobe, 708 }; 709 #else 710 static const struct mmc_ops sdhci_ops = { 711 .card_busy = sdhci_card_busy, 712 .send_cmd = sdhci_send_command, 713 .set_ios = sdhci_set_ios, 714 .init = sdhci_init, 715 .execute_tuning = sdhci_execute_tuning, 716 }; 717 #endif 718 719 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, 720 u32 f_max, u32 f_min) 721 { 722 u32 caps, caps_1; 723 724 caps = sdhci_readl(host, SDHCI_CAPABILITIES); 725 726 #ifdef CONFIG_MMC_SDHCI_SDMA 727 if (!(caps & SDHCI_CAN_DO_SDMA)) { 728 printf("%s: Your controller doesn't support SDMA!!\n", 729 __func__); 730 return -EINVAL; 731 } 732 #endif 733 if (host->quirks & SDHCI_QUIRK_REG32_RW) 734 host->version = 735 sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16; 736 else 737 host->version = sdhci_readw(host, SDHCI_HOST_VERSION); 738 739 cfg->name = host->name; 740 #ifndef CONFIG_DM_MMC 741 cfg->ops = &sdhci_ops; 742 #endif 743 744 /* Check whether the clock multiplier is supported or not */ 745 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { 746 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); 747 host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >> 748 SDHCI_CLOCK_MUL_SHIFT; 749 } 750 751 if (host->max_clk == 0) { 752 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) 753 host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> 754 SDHCI_CLOCK_BASE_SHIFT; 755 else 756 host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >> 757 SDHCI_CLOCK_BASE_SHIFT; 758 host->max_clk *= 1000000; 759 if (host->clk_mul) 760 host->max_clk *= host->clk_mul; 761 } 762 if (host->max_clk == 0) { 763 printf("%s: Hardware doesn't specify base clock frequency\n", 764 __func__); 765 return -EINVAL; 766 } 767 if (f_max && (f_max < host->max_clk)) 768 cfg->f_max = f_max; 769 else 770 cfg->f_max = host->max_clk; 771 if (f_min) 772 cfg->f_min = f_min; 773 else { 774 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) 775 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300; 776 else 777 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200; 778 } 779 cfg->voltages = 0; 780 if (caps & SDHCI_CAN_VDD_330) 781 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34; 782 if (caps & SDHCI_CAN_VDD_300) 783 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31; 784 if (caps & SDHCI_CAN_VDD_180) 785 cfg->voltages |= MMC_VDD_165_195; 786 787 if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE) 788 cfg->voltages |= host->voltages; 789 790 cfg->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT; 791 792 /* Since Host Controller Version3.0 */ 793 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { 794 if (!(caps & SDHCI_CAN_DO_8BIT)) 795 cfg->host_caps &= ~MMC_MODE_8BIT; 796 } 797 798 if (host->host_caps) 799 cfg->host_caps |= host->host_caps; 800 801 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 802 803 return 0; 804 } 805 806 #ifdef CONFIG_BLK 807 int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg) 808 { 809 return mmc_bind(dev, mmc, cfg); 810 } 811 #else 812 int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min) 813 { 814 int ret; 815 816 ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min); 817 if (ret) 818 return ret; 819 820 host->mmc = mmc_create(&host->cfg, host); 821 if (host->mmc == NULL) { 822 printf("%s: mmc create fail!\n", __func__); 823 return -ENOMEM; 824 } 825 826 return 0; 827 } 828 #endif 829