1 /* 2 * Copyright 2011, Marvell Semiconductor Inc. 3 * Lei Wen <leiwen@marvell.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 * 7 * Back ported to the 8xx platform (from the 8260 platform) by 8 * Murray.Jensen@cmst.csiro.au, 27-Jan-01. 9 */ 10 11 #include <common.h> 12 #include <errno.h> 13 #include <malloc.h> 14 #include <mmc.h> 15 #include <sdhci.h> 16 17 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER) 18 void *aligned_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER; 19 #else 20 void *aligned_buffer; 21 #endif 22 23 static void sdhci_reset(struct sdhci_host *host, u8 mask) 24 { 25 unsigned long timeout; 26 27 /* Wait max 100 ms */ 28 timeout = 100; 29 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); 30 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { 31 if (timeout == 0) { 32 printf("%s: Reset 0x%x never completed.\n", 33 __func__, (int)mask); 34 return; 35 } 36 timeout--; 37 udelay(1000); 38 } 39 } 40 41 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd) 42 { 43 int i; 44 if (cmd->resp_type & MMC_RSP_136) { 45 /* CRC is stripped so we need to do some shifting. */ 46 for (i = 0; i < 4; i++) { 47 cmd->response[i] = sdhci_readl(host, 48 SDHCI_RESPONSE + (3-i)*4) << 8; 49 if (i != 3) 50 cmd->response[i] |= sdhci_readb(host, 51 SDHCI_RESPONSE + (3-i)*4-1); 52 } 53 } else { 54 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE); 55 } 56 } 57 58 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data) 59 { 60 int i; 61 char *offs; 62 for (i = 0; i < data->blocksize; i += 4) { 63 offs = data->dest + i; 64 if (data->flags == MMC_DATA_READ) 65 *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER); 66 else 67 sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER); 68 } 69 } 70 71 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data, 72 unsigned int start_addr) 73 { 74 unsigned int stat, rdy, mask, timeout, block = 0; 75 bool transfer_done = false; 76 #ifdef CONFIG_MMC_SDHCI_SDMA 77 unsigned char ctrl; 78 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 79 ctrl &= ~SDHCI_CTRL_DMA_MASK; 80 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 81 #endif 82 83 timeout = 1000000; 84 rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL; 85 mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE; 86 do { 87 stat = sdhci_readl(host, SDHCI_INT_STATUS); 88 if (stat & SDHCI_INT_ERROR) { 89 printf("%s: Error detected in status(0x%X)!\n", 90 __func__, stat); 91 return -EIO; 92 } 93 if (!transfer_done && (stat & rdy)) { 94 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask)) 95 continue; 96 sdhci_writel(host, rdy, SDHCI_INT_STATUS); 97 sdhci_transfer_pio(host, data); 98 data->dest += data->blocksize; 99 if (++block >= data->blocks) { 100 /* Keep looping until the SDHCI_INT_DATA_END is 101 * cleared, even if we finished sending all the 102 * blocks. 103 */ 104 transfer_done = true; 105 continue; 106 } 107 } 108 #ifdef CONFIG_MMC_SDHCI_SDMA 109 if (!transfer_done && (stat & SDHCI_INT_DMA_END)) { 110 sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS); 111 start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1); 112 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE; 113 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); 114 } 115 #endif 116 if (timeout-- > 0) 117 udelay(10); 118 else { 119 printf("%s: Transfer data timeout\n", __func__); 120 return -ETIMEDOUT; 121 } 122 } while (!(stat & SDHCI_INT_DATA_END)); 123 return 0; 124 } 125 126 /* 127 * No command will be sent by driver if card is busy, so driver must wait 128 * for card ready state. 129 * Every time when card is busy after timeout then (last) timeout value will be 130 * increased twice but only if it doesn't exceed global defined maximum. 131 * Each function call will use last timeout value. 132 */ 133 #define SDHCI_CMD_MAX_TIMEOUT 3200 134 #define SDHCI_CMD_DEFAULT_TIMEOUT 100 135 #define SDHCI_READ_STATUS_TIMEOUT 1000 136 137 #ifdef CONFIG_DM_MMC 138 static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd, 139 struct mmc_data *data) 140 { 141 struct mmc *mmc = mmc_get_mmc_dev(dev); 142 143 #else 144 static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, 145 struct mmc_data *data) 146 { 147 #endif 148 struct sdhci_host *host = mmc->priv; 149 unsigned int stat = 0; 150 int ret = 0; 151 int trans_bytes = 0, is_aligned = 1; 152 u32 mask, flags, mode; 153 unsigned int time = 0, start_addr = 0; 154 int mmc_dev = mmc_get_blk_desc(mmc)->devnum; 155 unsigned start = get_timer(0); 156 157 /* Timeout unit - ms */ 158 static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT; 159 160 mask = SDHCI_CMD_INHIBIT; 161 162 if (data) 163 mask |= SDHCI_DATA_INHIBIT; 164 165 /* We shouldn't wait for data inihibit for stop commands, even 166 though they might use busy signaling */ 167 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 168 mask &= ~SDHCI_DATA_INHIBIT; 169 170 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 171 if (time >= cmd_timeout) { 172 printf("%s: MMC: %d busy ", __func__, mmc_dev); 173 if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) { 174 cmd_timeout += cmd_timeout; 175 printf("timeout increasing to: %u ms.\n", 176 cmd_timeout); 177 } else { 178 puts("timeout.\n"); 179 return -ECOMM; 180 } 181 } 182 time++; 183 udelay(1000); 184 } 185 186 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); 187 188 mask = SDHCI_INT_RESPONSE; 189 if (!(cmd->resp_type & MMC_RSP_PRESENT)) 190 flags = SDHCI_CMD_RESP_NONE; 191 else if (cmd->resp_type & MMC_RSP_136) 192 flags = SDHCI_CMD_RESP_LONG; 193 else if (cmd->resp_type & MMC_RSP_BUSY) { 194 flags = SDHCI_CMD_RESP_SHORT_BUSY; 195 if (data) 196 mask |= SDHCI_INT_DATA_END; 197 } else 198 flags = SDHCI_CMD_RESP_SHORT; 199 200 if (cmd->resp_type & MMC_RSP_CRC) 201 flags |= SDHCI_CMD_CRC; 202 if (cmd->resp_type & MMC_RSP_OPCODE) 203 flags |= SDHCI_CMD_INDEX; 204 if (data) 205 flags |= SDHCI_CMD_DATA; 206 207 if (cmd->cmdidx == MMC_SEND_TUNING_BLOCK || 208 cmd->cmdidx == MMC_SEND_TUNING_BLOCK_HS200) { 209 mask &= ~SDHCI_INT_RESPONSE; 210 mask |= SDHCI_INT_DATA_AVAIL; 211 flags |= SDHCI_CMD_DATA; 212 } 213 214 /* Set Transfer mode regarding to data flag */ 215 if (data != 0) { 216 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); 217 mode = SDHCI_TRNS_BLK_CNT_EN; 218 trans_bytes = data->blocks * data->blocksize; 219 if (data->blocks > 1) 220 mode |= SDHCI_TRNS_MULTI; 221 222 if (data->flags == MMC_DATA_READ) 223 mode |= SDHCI_TRNS_READ; 224 225 #ifdef CONFIG_MMC_SDHCI_SDMA 226 if (data->flags == MMC_DATA_READ) 227 start_addr = (unsigned long)data->dest; 228 else 229 start_addr = (unsigned long)data->src; 230 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && 231 (start_addr & 0x7) != 0x0) { 232 is_aligned = 0; 233 start_addr = (unsigned long)aligned_buffer; 234 if (data->flags != MMC_DATA_READ) 235 memcpy(aligned_buffer, data->src, trans_bytes); 236 } 237 238 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER) 239 /* 240 * Always use this bounce-buffer when 241 * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined 242 */ 243 is_aligned = 0; 244 start_addr = (unsigned long)aligned_buffer; 245 if (data->flags != MMC_DATA_READ) 246 memcpy(aligned_buffer, data->src, trans_bytes); 247 #endif 248 249 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); 250 mode |= SDHCI_TRNS_DMA; 251 #endif 252 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 253 data->blocksize), 254 SDHCI_BLOCK_SIZE); 255 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); 256 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); 257 } else if (cmd->resp_type & MMC_RSP_BUSY) { 258 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); 259 } 260 261 sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT); 262 #ifdef CONFIG_MMC_SDHCI_SDMA 263 if (data != 0) { 264 trans_bytes = ALIGN(trans_bytes, CONFIG_SYS_CACHELINE_SIZE); 265 flush_cache(start_addr, trans_bytes); 266 } 267 #endif 268 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND); 269 start = get_timer(0); 270 do { 271 stat = sdhci_readl(host, SDHCI_INT_STATUS); 272 if (stat & SDHCI_INT_ERROR) 273 break; 274 275 if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) { 276 if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) { 277 return 0; 278 } else { 279 printf("%s: Timeout for status update!\n", 280 __func__); 281 return -ETIMEDOUT; 282 } 283 } 284 } while ((stat & mask) != mask); 285 286 if ((stat & (SDHCI_INT_ERROR | mask)) == mask) { 287 sdhci_cmd_done(host, cmd); 288 sdhci_writel(host, mask, SDHCI_INT_STATUS); 289 } else 290 ret = -1; 291 292 if (!ret && data) 293 ret = sdhci_transfer_data(host, data, start_addr); 294 295 if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD) 296 udelay(1000); 297 298 stat = sdhci_readl(host, SDHCI_INT_STATUS); 299 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); 300 if (!ret) { 301 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && 302 !is_aligned && (data->flags == MMC_DATA_READ)) 303 memcpy(data->dest, aligned_buffer, trans_bytes); 304 return 0; 305 } 306 307 sdhci_reset(host, SDHCI_RESET_CMD); 308 sdhci_reset(host, SDHCI_RESET_DATA); 309 if (stat & SDHCI_INT_TIMEOUT) 310 return -ETIMEDOUT; 311 else 312 return -ECOMM; 313 } 314 315 int sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 316 { 317 unsigned int div, clk = 0, timeout; 318 319 /* Wait max 20 ms */ 320 timeout = 200; 321 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & 322 (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) { 323 if (timeout == 0) { 324 printf("%s: Timeout to wait cmd & data inhibit\n", 325 __func__); 326 return -EBUSY; 327 } 328 329 timeout--; 330 udelay(100); 331 } 332 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 333 334 if (clock == 0) 335 return 0; 336 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { 337 /* 338 * Check if the Host Controller supports Programmable Clock 339 * Mode. 340 */ 341 if (host->clk_mul) { 342 for (div = 1; div <= 1024; div++) { 343 if ((host->max_clk / div) <= clock) 344 break; 345 } 346 347 /* 348 * Set Programmable Clock Mode in the Clock 349 * Control register. 350 */ 351 clk = SDHCI_PROG_CLOCK_MODE; 352 div--; 353 } else { 354 /* Version 3.00 divisors must be a multiple of 2. */ 355 if (host->max_clk <= clock) { 356 div = 1; 357 } else { 358 for (div = 2; 359 div < SDHCI_MAX_DIV_SPEC_300; 360 div += 2) { 361 if ((host->max_clk / div) <= clock) 362 break; 363 } 364 } 365 div >>= 1; 366 } 367 } else { 368 /* Version 2.00 divisors must be a power of 2. */ 369 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { 370 if ((host->max_clk / div) <= clock) 371 break; 372 } 373 div >>= 1; 374 } 375 if (host->ops && host->ops->set_clock_ext) 376 host->ops->set_clock_ext(host, div); 377 378 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; 379 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) 380 << SDHCI_DIVIDER_HI_SHIFT; 381 clk |= SDHCI_CLOCK_INT_EN; 382 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 383 384 /* Wait max 20 ms */ 385 timeout = 20; 386 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 387 & SDHCI_CLOCK_INT_STABLE)) { 388 if (timeout == 0) { 389 printf("%s: Internal clock never stabilised.\n", 390 __func__); 391 return -EBUSY; 392 } 393 timeout--; 394 udelay(1000); 395 } 396 clk |= SDHCI_CLOCK_CARD_EN; 397 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 398 399 host->clock = clock; 400 return 0; 401 } 402 403 static void sdhci_set_power(struct sdhci_host *host, unsigned short power) 404 { 405 u8 pwr = 0; 406 407 if (power != (unsigned short)-1) { 408 switch (1 << power) { 409 case MMC_VDD_165_195: 410 pwr = SDHCI_POWER_180; 411 break; 412 case MMC_VDD_29_30: 413 case MMC_VDD_30_31: 414 pwr = SDHCI_POWER_300; 415 break; 416 case MMC_VDD_32_33: 417 case MMC_VDD_33_34: 418 pwr = SDHCI_POWER_330; 419 break; 420 } 421 } 422 423 if (pwr == 0) { 424 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 425 return; 426 } 427 428 pwr |= SDHCI_POWER_ON; 429 430 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 431 } 432 433 static void sdhci_set_uhs_signaling(struct sdhci_host *host) 434 { 435 u16 ctrl_2; 436 u32 timing = host->mmc->timing; 437 438 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 439 /* Select Bus Speed Mode for host */ 440 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 441 442 if ((timing != MMC_TIMING_LEGACY) && 443 (timing != MMC_TIMING_MMC_HS) && 444 (timing != MMC_TIMING_SD_HS)) 445 ctrl_2 |= SDHCI_CTRL_VDD_180; 446 447 if ((timing == MMC_TIMING_MMC_HS200) || 448 (timing == MMC_TIMING_UHS_SDR104)) 449 ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_DRV_TYPE_A; 450 else if (timing == MMC_TIMING_UHS_SDR12) 451 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 452 else if (timing == MMC_TIMING_UHS_SDR25) 453 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 454 else if ((timing == MMC_TIMING_UHS_SDR50) || 455 (timing == MMC_TIMING_MMC_HS)) 456 ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 457 else if ((timing == MMC_TIMING_UHS_DDR50) || 458 (timing == MMC_TIMING_MMC_DDR52)) 459 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 460 else if (timing == MMC_TIMING_MMC_HS400 || 461 timing == MMC_TIMING_MMC_HS400ES) 462 ctrl_2 |= SDHCI_CTRL_HS400 | SDHCI_CTRL_DRV_TYPE_A; 463 464 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 465 } 466 467 #ifdef CONFIG_DM_MMC 468 static bool sdhci_card_busy(struct udevice *dev) 469 { 470 struct mmc *mmc = mmc_get_mmc_dev(dev); 471 #else 472 static bool sdhci_card_busy(struct mmc *mmc) 473 { 474 #endif 475 struct sdhci_host *host = mmc->priv; 476 u32 present_state; 477 478 /* Check whether DAT[0] is 0 */ 479 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); 480 481 return !(present_state & SDHCI_DATA_0_LVL); 482 } 483 484 #ifdef CONFIG_DM_MMC 485 static int sdhci_set_ios(struct udevice *dev) 486 { 487 struct mmc *mmc = mmc_get_mmc_dev(dev); 488 #else 489 static int sdhci_set_ios(struct mmc *mmc) 490 { 491 #endif 492 u32 ctrl; 493 struct sdhci_host *host = mmc->priv; 494 495 if (host->ops && host->ops->set_control_reg) 496 host->ops->set_control_reg(host); 497 498 if (mmc->clock != host->clock) { 499 if (host->ops && host->ops->set_clock) 500 host->ops->set_clock(host, mmc->clock); 501 else 502 sdhci_set_clock(host, mmc->clock); 503 } 504 505 /* Set bus width */ 506 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 507 if (mmc->bus_width == 8) { 508 ctrl &= ~SDHCI_CTRL_4BITBUS; 509 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) || 510 (host->quirks & SDHCI_QUIRK_USE_WIDE8)) 511 ctrl |= SDHCI_CTRL_8BITBUS; 512 } else { 513 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) || 514 (host->quirks & SDHCI_QUIRK_USE_WIDE8)) 515 ctrl &= ~SDHCI_CTRL_8BITBUS; 516 if (mmc->bus_width == 4) 517 ctrl |= SDHCI_CTRL_4BITBUS; 518 else 519 ctrl &= ~SDHCI_CTRL_4BITBUS; 520 } 521 522 if (!(mmc->timing == MMC_TIMING_LEGACY) && 523 !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) 524 ctrl |= SDHCI_CTRL_HISPD; 525 else 526 ctrl &= ~SDHCI_CTRL_HISPD; 527 528 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 529 530 if ((mmc->timing != MMC_TIMING_LEGACY) && 531 (mmc->timing != MMC_TIMING_MMC_HS) && 532 (mmc->timing != MMC_TIMING_SD_HS)) 533 sdhci_set_power(host, MMC_VDD_165_195_SHIFT); 534 535 sdhci_set_uhs_signaling(host); 536 537 /* If available, call the driver specific "post" set_ios() function */ 538 if (host->ops && host->ops->set_ios_post) 539 host->ops->set_ios_post(host); 540 541 return 0; 542 } 543 544 static int sdhci_init(struct mmc *mmc) 545 { 546 struct sdhci_host *host = mmc->priv; 547 548 sdhci_reset(host, SDHCI_RESET_ALL); 549 550 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) { 551 aligned_buffer = memalign(8, 512*1024); 552 if (!aligned_buffer) { 553 printf("%s: Aligned buffer alloc failed!!!\n", 554 __func__); 555 return -ENOMEM; 556 } 557 } 558 559 sdhci_set_power(host, fls(mmc->cfg->voltages) - 1); 560 561 if (host->ops && host->ops->get_cd) 562 host->ops->get_cd(host); 563 564 /* Enable only interrupts served by the SD controller */ 565 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK, 566 SDHCI_INT_ENABLE); 567 /* Mask all sdhci interrupt sources */ 568 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE); 569 570 return 0; 571 } 572 573 static int sdhci_send_tuning(struct sdhci_host *host, u32 opcode) 574 { 575 struct mmc_cmd cmd; 576 577 cmd.cmdidx = opcode; 578 cmd.resp_type = MMC_RSP_R1; 579 cmd.cmdarg = 0; 580 /* 581 * In response to CMD19, the card sends 64 bytes of tuning 582 * block to the Host Controller. So we set the block size 583 * to 64 here. 584 */ 585 if (opcode == MMC_SEND_TUNING_BLOCK_HS200 && 586 host->mmc->bus_width == MMC_BUS_WIDTH_8BIT) 587 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128), SDHCI_BLOCK_SIZE); 588 else 589 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE); 590 591 /* 592 * The tuning block is sent by the card to the host controller. 593 * So we set the TRNS_READ bit in the Transfer Mode register. 594 * This also takes care of setting DMA Enable and Multi Block 595 * Select in the same register to 0. 596 */ 597 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); 598 599 #ifdef CONFIG_DM_MMC 600 return sdhci_send_command(host->mmc->dev, &cmd, NULL); 601 #else 602 return sdhci_send_command(host->mmc, &cmd, NULL); 603 #endif 604 } 605 606 #define MAX_TUNING_LOOP 40 607 static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) 608 { 609 int i; 610 int ret; 611 612 /* 613 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number 614 * of loops reaches 40 times. 615 */ 616 for (i = 0; i < MAX_TUNING_LOOP; i++) { 617 u16 ctrl; 618 619 ret = sdhci_send_tuning(host, opcode); 620 621 if (ret) 622 return ret; 623 624 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 625 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) { 626 if (ctrl & SDHCI_CTRL_TUNED_CLK) 627 /* Tuning successfully */ 628 return 0; 629 break; 630 } 631 } 632 633 return -ETIMEDOUT; 634 } 635 636 #ifdef CONFIG_DM_MMC 637 static int sdhci_execute_tuning(struct udevice *dev, u32 opcode) 638 { 639 struct mmc *mmc = mmc_get_mmc_dev(dev); 640 #else 641 static int sdhci_execute_tuning(struct mmc *mmc, u32 opcode) 642 { 643 #endif 644 struct sdhci_host *host = mmc->priv; 645 u16 ctrl; 646 647 /* 648 * The Host Controller needs tuning in case of SDR104 and DDR50 649 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in 650 * the Capabilities register. 651 * If the Host Controller supports the HS200 mode then the 652 * tuning function has to be executed. 653 */ 654 switch (mmc->timing) { 655 /* HS400 tuning is done in HS200 mode */ 656 case MMC_TIMING_MMC_HS400: 657 return -EINVAL; 658 case MMC_TIMING_MMC_HS200: 659 /* 660 * Periodic re-tuning for HS400 is not expected to be needed, so 661 * disable it here. 662 */ 663 break; 664 default: 665 return -EINVAL; 666 } 667 668 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 669 ctrl |= SDHCI_CTRL_EXEC_TUNING; 670 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 671 672 return __sdhci_execute_tuning(host, opcode); 673 } 674 675 #ifdef CONFIG_DM_MMC 676 int sdhci_probe(struct udevice *dev) 677 { 678 struct mmc *mmc = mmc_get_mmc_dev(dev); 679 680 return sdhci_init(mmc); 681 } 682 683 const struct dm_mmc_ops sdhci_ops = { 684 .card_busy = sdhci_card_busy, 685 .send_cmd = sdhci_send_command, 686 .set_ios = sdhci_set_ios, 687 .execute_tuning = sdhci_execute_tuning, 688 }; 689 #else 690 static const struct mmc_ops sdhci_ops = { 691 .card_busy = sdhci_card_busy, 692 .send_cmd = sdhci_send_command, 693 .set_ios = sdhci_set_ios, 694 .init = sdhci_init, 695 .execute_tuning = sdhci_execute_tuning, 696 }; 697 #endif 698 699 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, 700 u32 f_max, u32 f_min) 701 { 702 u32 caps, caps_1; 703 704 caps = sdhci_readl(host, SDHCI_CAPABILITIES); 705 706 #ifdef CONFIG_MMC_SDHCI_SDMA 707 if (!(caps & SDHCI_CAN_DO_SDMA)) { 708 printf("%s: Your controller doesn't support SDMA!!\n", 709 __func__); 710 return -EINVAL; 711 } 712 #endif 713 if (host->quirks & SDHCI_QUIRK_REG32_RW) 714 host->version = 715 sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16; 716 else 717 host->version = sdhci_readw(host, SDHCI_HOST_VERSION); 718 719 cfg->name = host->name; 720 #ifndef CONFIG_DM_MMC 721 cfg->ops = &sdhci_ops; 722 #endif 723 724 /* Check whether the clock multiplier is supported or not */ 725 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { 726 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); 727 host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >> 728 SDHCI_CLOCK_MUL_SHIFT; 729 } 730 731 if (host->max_clk == 0) { 732 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) 733 host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> 734 SDHCI_CLOCK_BASE_SHIFT; 735 else 736 host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >> 737 SDHCI_CLOCK_BASE_SHIFT; 738 host->max_clk *= 1000000; 739 if (host->clk_mul) 740 host->max_clk *= host->clk_mul; 741 } 742 if (host->max_clk == 0) { 743 printf("%s: Hardware doesn't specify base clock frequency\n", 744 __func__); 745 return -EINVAL; 746 } 747 if (f_max && (f_max < host->max_clk)) 748 cfg->f_max = f_max; 749 else 750 cfg->f_max = host->max_clk; 751 if (f_min) 752 cfg->f_min = f_min; 753 else { 754 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) 755 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300; 756 else 757 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200; 758 } 759 cfg->voltages = 0; 760 if (caps & SDHCI_CAN_VDD_330) 761 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34; 762 if (caps & SDHCI_CAN_VDD_300) 763 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31; 764 if (caps & SDHCI_CAN_VDD_180) 765 cfg->voltages |= MMC_VDD_165_195; 766 767 if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE) 768 cfg->voltages |= host->voltages; 769 770 cfg->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT; 771 772 /* Since Host Controller Version3.0 */ 773 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { 774 if (!(caps & SDHCI_CAN_DO_8BIT)) 775 cfg->host_caps &= ~MMC_MODE_8BIT; 776 } 777 778 if (host->host_caps) 779 cfg->host_caps |= host->host_caps; 780 781 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 782 783 return 0; 784 } 785 786 #ifdef CONFIG_BLK 787 int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg) 788 { 789 return mmc_bind(dev, mmc, cfg); 790 } 791 #else 792 int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min) 793 { 794 int ret; 795 796 ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min); 797 if (ret) 798 return ret; 799 800 host->mmc = mmc_create(&host->cfg, host); 801 if (host->mmc == NULL) { 802 printf("%s: mmc create fail!\n", __func__); 803 return -ENOMEM; 804 } 805 806 return 0; 807 } 808 #endif 809