1 /* 2 * Copyright 2011, Marvell Semiconductor Inc. 3 * Lei Wen <leiwen@marvell.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 * 7 * Back ported to the 8xx platform (from the 8260 platform) by 8 * Murray.Jensen@cmst.csiro.au, 27-Jan-01. 9 */ 10 11 #include <common.h> 12 #include <errno.h> 13 #include <malloc.h> 14 #include <mmc.h> 15 #include <sdhci.h> 16 17 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER) 18 void *aligned_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER; 19 #else 20 void *aligned_buffer; 21 #endif 22 23 static void sdhci_reset(struct sdhci_host *host, u8 mask) 24 { 25 unsigned long timeout; 26 27 /* Wait max 100 ms */ 28 timeout = 100; 29 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); 30 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { 31 if (timeout == 0) { 32 printf("%s: Reset 0x%x never completed.\n", 33 __func__, (int)mask); 34 return; 35 } 36 timeout--; 37 udelay(1000); 38 } 39 } 40 41 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd) 42 { 43 int i; 44 if (cmd->resp_type & MMC_RSP_136) { 45 /* CRC is stripped so we need to do some shifting. */ 46 for (i = 0; i < 4; i++) { 47 cmd->response[i] = sdhci_readl(host, 48 SDHCI_RESPONSE + (3-i)*4) << 8; 49 if (i != 3) 50 cmd->response[i] |= sdhci_readb(host, 51 SDHCI_RESPONSE + (3-i)*4-1); 52 } 53 } else { 54 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE); 55 } 56 } 57 58 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data) 59 { 60 int i; 61 char *offs; 62 for (i = 0; i < data->blocksize; i += 4) { 63 offs = data->dest + i; 64 if (data->flags == MMC_DATA_READ) 65 *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER); 66 else 67 sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER); 68 } 69 } 70 71 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data, 72 unsigned int start_addr) 73 { 74 unsigned int stat, rdy, mask, timeout, block = 0; 75 bool transfer_done = false; 76 #ifdef CONFIG_MMC_SDHCI_SDMA 77 unsigned char ctrl; 78 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 79 ctrl &= ~SDHCI_CTRL_DMA_MASK; 80 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 81 #endif 82 83 timeout = 1000000; 84 rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL; 85 mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE; 86 do { 87 stat = sdhci_readl(host, SDHCI_INT_STATUS); 88 if (stat & SDHCI_INT_ERROR) { 89 printf("%s: Error detected in status(0x%X)!\n", 90 __func__, stat); 91 return -EIO; 92 } 93 if (!transfer_done && (stat & rdy)) { 94 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask)) 95 continue; 96 sdhci_writel(host, rdy, SDHCI_INT_STATUS); 97 sdhci_transfer_pio(host, data); 98 data->dest += data->blocksize; 99 if (++block >= data->blocks) { 100 /* Keep looping until the SDHCI_INT_DATA_END is 101 * cleared, even if we finished sending all the 102 * blocks. 103 */ 104 transfer_done = true; 105 continue; 106 } 107 } 108 #ifdef CONFIG_MMC_SDHCI_SDMA 109 if (!transfer_done && (stat & SDHCI_INT_DMA_END)) { 110 sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS); 111 start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1); 112 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE; 113 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); 114 } 115 #endif 116 if (timeout-- > 0) 117 udelay(10); 118 else { 119 printf("%s: Transfer data timeout\n", __func__); 120 return -ETIMEDOUT; 121 } 122 } while (!(stat & SDHCI_INT_DATA_END)); 123 return 0; 124 } 125 126 /* 127 * No command will be sent by driver if card is busy, so driver must wait 128 * for card ready state. 129 * Every time when card is busy after timeout then (last) timeout value will be 130 * increased twice but only if it doesn't exceed global defined maximum. 131 * Each function call will use last timeout value. 132 */ 133 #define SDHCI_CMD_MAX_TIMEOUT 3200 134 #define SDHCI_CMD_DEFAULT_TIMEOUT 100 135 #define SDHCI_READ_STATUS_TIMEOUT 1000 136 137 #ifdef CONFIG_DM_MMC 138 static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd, 139 struct mmc_data *data) 140 { 141 struct mmc *mmc = mmc_get_mmc_dev(dev); 142 143 #else 144 static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, 145 struct mmc_data *data) 146 { 147 #endif 148 struct sdhci_host *host = mmc->priv; 149 unsigned int stat = 0; 150 int ret = 0; 151 int trans_bytes = 0, is_aligned = 1; 152 u32 mask, flags, mode; 153 unsigned int time = 0, start_addr = 0; 154 int mmc_dev = mmc_get_blk_desc(mmc)->devnum; 155 unsigned start = get_timer(0); 156 157 /* Timeout unit - ms */ 158 static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT; 159 160 mask = SDHCI_CMD_INHIBIT; 161 162 if (data) 163 mask |= SDHCI_DATA_INHIBIT; 164 165 /* We shouldn't wait for data inihibit for stop commands, even 166 though they might use busy signaling */ 167 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 168 mask &= ~SDHCI_DATA_INHIBIT; 169 170 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { 171 if (time >= cmd_timeout) { 172 printf("%s: MMC: %d busy ", __func__, mmc_dev); 173 if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) { 174 cmd_timeout += cmd_timeout; 175 printf("timeout increasing to: %u ms.\n", 176 cmd_timeout); 177 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); 178 } else { 179 puts("timeout.\n"); 180 /* remove timeout return error and try to send command */ 181 } 182 } 183 time++; 184 udelay(1000); 185 } 186 187 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); 188 189 mask = SDHCI_INT_RESPONSE; 190 if (!(cmd->resp_type & MMC_RSP_PRESENT)) 191 flags = SDHCI_CMD_RESP_NONE; 192 else if (cmd->resp_type & MMC_RSP_136) 193 flags = SDHCI_CMD_RESP_LONG; 194 else if (cmd->resp_type & MMC_RSP_BUSY) { 195 flags = SDHCI_CMD_RESP_SHORT_BUSY; 196 if (data) 197 mask |= SDHCI_INT_DATA_END; 198 } else 199 flags = SDHCI_CMD_RESP_SHORT; 200 201 if (cmd->resp_type & MMC_RSP_CRC) 202 flags |= SDHCI_CMD_CRC; 203 if (cmd->resp_type & MMC_RSP_OPCODE) 204 flags |= SDHCI_CMD_INDEX; 205 if (data) 206 flags |= SDHCI_CMD_DATA; 207 208 if (cmd->cmdidx == MMC_SEND_TUNING_BLOCK || 209 cmd->cmdidx == MMC_SEND_TUNING_BLOCK_HS200) { 210 mask &= ~SDHCI_INT_RESPONSE; 211 mask |= SDHCI_INT_DATA_AVAIL; 212 flags |= SDHCI_CMD_DATA; 213 } 214 215 /* Set Transfer mode regarding to data flag */ 216 if (data != 0) { 217 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); 218 mode = SDHCI_TRNS_BLK_CNT_EN; 219 trans_bytes = data->blocks * data->blocksize; 220 if (data->blocks > 1) 221 mode |= SDHCI_TRNS_MULTI; 222 223 if (data->flags == MMC_DATA_READ) 224 mode |= SDHCI_TRNS_READ; 225 226 #ifdef CONFIG_MMC_SDHCI_SDMA 227 if (data->flags == MMC_DATA_READ) 228 start_addr = (unsigned long)data->dest; 229 else 230 start_addr = (unsigned long)data->src; 231 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && 232 (start_addr & 0x7) != 0x0) { 233 is_aligned = 0; 234 start_addr = (unsigned long)aligned_buffer; 235 if (data->flags != MMC_DATA_READ) 236 memcpy(aligned_buffer, data->src, trans_bytes); 237 } 238 239 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER) 240 /* 241 * Always use this bounce-buffer when 242 * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined 243 */ 244 is_aligned = 0; 245 start_addr = (unsigned long)aligned_buffer; 246 if (data->flags != MMC_DATA_READ) 247 memcpy(aligned_buffer, data->src, trans_bytes); 248 #endif 249 250 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); 251 mode |= SDHCI_TRNS_DMA; 252 #endif 253 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 254 data->blocksize), 255 SDHCI_BLOCK_SIZE); 256 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); 257 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); 258 } else if (cmd->resp_type & MMC_RSP_BUSY) { 259 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); 260 } 261 262 sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT); 263 #ifdef CONFIG_MMC_SDHCI_SDMA 264 if (data != 0) { 265 trans_bytes = ALIGN(trans_bytes, CONFIG_SYS_CACHELINE_SIZE); 266 flush_cache(start_addr, trans_bytes); 267 } 268 #endif 269 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND); 270 start = get_timer(0); 271 do { 272 stat = sdhci_readl(host, SDHCI_INT_STATUS); 273 if (stat & SDHCI_INT_ERROR) 274 break; 275 276 if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) { 277 if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) { 278 return 0; 279 } else { 280 printf("%s: Timeout for status update!\n", 281 __func__); 282 return -ETIMEDOUT; 283 } 284 } 285 } while ((stat & mask) != mask); 286 287 if ((stat & (SDHCI_INT_ERROR | mask)) == mask) { 288 sdhci_cmd_done(host, cmd); 289 sdhci_writel(host, mask, SDHCI_INT_STATUS); 290 } else 291 ret = -1; 292 293 if (!ret && data) 294 ret = sdhci_transfer_data(host, data, start_addr); 295 296 if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD) 297 udelay(1000); 298 299 stat = sdhci_readl(host, SDHCI_INT_STATUS); 300 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); 301 if (!ret) { 302 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && 303 !is_aligned && (data->flags == MMC_DATA_READ)) 304 memcpy(data->dest, aligned_buffer, trans_bytes); 305 return 0; 306 } 307 308 sdhci_reset(host, SDHCI_RESET_CMD); 309 sdhci_reset(host, SDHCI_RESET_DATA); 310 if (stat & SDHCI_INT_TIMEOUT) 311 return -ETIMEDOUT; 312 else 313 return -ECOMM; 314 } 315 316 int sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 317 { 318 unsigned int div, clk = 0, timeout; 319 320 /* Wait max 20 ms */ 321 timeout = 200; 322 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & 323 (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) { 324 if (timeout == 0) { 325 printf("%s: Timeout to wait cmd & data inhibit\n", 326 __func__); 327 return -EBUSY; 328 } 329 330 timeout--; 331 udelay(100); 332 } 333 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 334 335 if (clock == 0) 336 return 0; 337 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { 338 /* 339 * Check if the Host Controller supports Programmable Clock 340 * Mode. 341 */ 342 if (host->clk_mul) { 343 for (div = 1; div <= 1024; div++) { 344 if ((host->max_clk / div) <= clock) 345 break; 346 } 347 348 /* 349 * Set Programmable Clock Mode in the Clock 350 * Control register. 351 */ 352 clk = SDHCI_PROG_CLOCK_MODE; 353 div--; 354 } else { 355 /* Version 3.00 divisors must be a multiple of 2. */ 356 if (host->max_clk <= clock) { 357 div = 1; 358 } else { 359 for (div = 2; 360 div < SDHCI_MAX_DIV_SPEC_300; 361 div += 2) { 362 if ((host->max_clk / div) <= clock) 363 break; 364 } 365 } 366 div >>= 1; 367 } 368 } else { 369 /* Version 2.00 divisors must be a power of 2. */ 370 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { 371 if ((host->max_clk / div) <= clock) 372 break; 373 } 374 div >>= 1; 375 } 376 if (host->ops && host->ops->set_clock_ext) 377 host->ops->set_clock_ext(host, div); 378 379 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; 380 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) 381 << SDHCI_DIVIDER_HI_SHIFT; 382 clk |= SDHCI_CLOCK_INT_EN; 383 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 384 385 /* Wait max 20 ms */ 386 timeout = 20; 387 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 388 & SDHCI_CLOCK_INT_STABLE)) { 389 if (timeout == 0) { 390 printf("%s: Internal clock never stabilised.\n", 391 __func__); 392 return -EBUSY; 393 } 394 timeout--; 395 udelay(1000); 396 } 397 clk |= SDHCI_CLOCK_CARD_EN; 398 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 399 400 host->clock = clock; 401 return 0; 402 } 403 404 static void sdhci_set_power(struct sdhci_host *host, unsigned short power) 405 { 406 u8 pwr = 0; 407 408 if (power != (unsigned short)-1) { 409 switch (1 << power) { 410 case MMC_VDD_165_195: 411 pwr = SDHCI_POWER_180; 412 break; 413 case MMC_VDD_29_30: 414 case MMC_VDD_30_31: 415 pwr = SDHCI_POWER_300; 416 break; 417 case MMC_VDD_32_33: 418 case MMC_VDD_33_34: 419 pwr = SDHCI_POWER_330; 420 break; 421 } 422 } 423 424 if (pwr == 0) { 425 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 426 return; 427 } 428 429 pwr |= SDHCI_POWER_ON; 430 431 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 432 } 433 434 static void sdhci_set_uhs_signaling(struct sdhci_host *host) 435 { 436 u16 ctrl_2; 437 u32 timing = host->mmc->timing; 438 439 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 440 /* Select Bus Speed Mode for host */ 441 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 442 443 if ((timing != MMC_TIMING_LEGACY) && 444 (timing != MMC_TIMING_MMC_HS) && 445 (timing != MMC_TIMING_SD_HS)) 446 ctrl_2 |= SDHCI_CTRL_VDD_180; 447 448 if ((timing == MMC_TIMING_MMC_HS200) || 449 (timing == MMC_TIMING_UHS_SDR104)) 450 ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_DRV_TYPE_A; 451 else if (timing == MMC_TIMING_UHS_SDR12) 452 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 453 else if (timing == MMC_TIMING_UHS_SDR25) 454 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 455 else if ((timing == MMC_TIMING_UHS_SDR50) || 456 (timing == MMC_TIMING_MMC_HS)) 457 ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 458 else if ((timing == MMC_TIMING_UHS_DDR50) || 459 (timing == MMC_TIMING_MMC_DDR52)) 460 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 461 else if (timing == MMC_TIMING_MMC_HS400 || 462 timing == MMC_TIMING_MMC_HS400ES) 463 ctrl_2 |= SDHCI_CTRL_HS400 | SDHCI_CTRL_DRV_TYPE_A; 464 465 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 466 } 467 468 #ifdef CONFIG_DM_MMC 469 static bool sdhci_card_busy(struct udevice *dev) 470 { 471 struct mmc *mmc = mmc_get_mmc_dev(dev); 472 #else 473 static bool sdhci_card_busy(struct mmc *mmc) 474 { 475 #endif 476 struct sdhci_host *host = mmc->priv; 477 u32 present_state; 478 479 /* Check whether DAT[0] is 0 */ 480 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); 481 482 return !(present_state & SDHCI_DATA_0_LVL); 483 } 484 485 #ifdef CONFIG_DM_MMC 486 static int sdhci_set_ios(struct udevice *dev) 487 { 488 struct mmc *mmc = mmc_get_mmc_dev(dev); 489 #else 490 static int sdhci_set_ios(struct mmc *mmc) 491 { 492 #endif 493 u32 ctrl; 494 struct sdhci_host *host = mmc->priv; 495 496 if (host->ops && host->ops->set_control_reg) 497 host->ops->set_control_reg(host); 498 499 if (mmc->clock != host->clock) { 500 if (host->ops && host->ops->set_clock) 501 host->ops->set_clock(host, mmc->clock); 502 else 503 sdhci_set_clock(host, mmc->clock); 504 } 505 506 /* Set bus width */ 507 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 508 if (mmc->bus_width == 8) { 509 ctrl &= ~SDHCI_CTRL_4BITBUS; 510 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) || 511 (host->quirks & SDHCI_QUIRK_USE_WIDE8)) 512 ctrl |= SDHCI_CTRL_8BITBUS; 513 } else { 514 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) || 515 (host->quirks & SDHCI_QUIRK_USE_WIDE8)) 516 ctrl &= ~SDHCI_CTRL_8BITBUS; 517 if (mmc->bus_width == 4) 518 ctrl |= SDHCI_CTRL_4BITBUS; 519 else 520 ctrl &= ~SDHCI_CTRL_4BITBUS; 521 } 522 523 if (!(mmc->timing == MMC_TIMING_LEGACY) && 524 !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) 525 ctrl |= SDHCI_CTRL_HISPD; 526 else 527 ctrl &= ~SDHCI_CTRL_HISPD; 528 529 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 530 531 if ((mmc->timing != MMC_TIMING_LEGACY) && 532 (mmc->timing != MMC_TIMING_MMC_HS) && 533 (mmc->timing != MMC_TIMING_SD_HS)) 534 sdhci_set_power(host, MMC_VDD_165_195_SHIFT); 535 536 sdhci_set_uhs_signaling(host); 537 538 /* If available, call the driver specific "post" set_ios() function */ 539 if (host->ops && host->ops->set_ios_post) 540 host->ops->set_ios_post(host); 541 542 return 0; 543 } 544 545 static int sdhci_init(struct mmc *mmc) 546 { 547 struct sdhci_host *host = mmc->priv; 548 549 sdhci_reset(host, SDHCI_RESET_ALL); 550 551 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) { 552 aligned_buffer = memalign(8, 512*1024); 553 if (!aligned_buffer) { 554 printf("%s: Aligned buffer alloc failed!!!\n", 555 __func__); 556 return -ENOMEM; 557 } 558 } 559 560 sdhci_set_power(host, fls(mmc->cfg->voltages) - 1); 561 562 if (host->ops && host->ops->get_cd) 563 host->ops->get_cd(host); 564 565 /* Enable only interrupts served by the SD controller */ 566 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK, 567 SDHCI_INT_ENABLE); 568 /* Mask all sdhci interrupt sources */ 569 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE); 570 571 return 0; 572 } 573 574 static int sdhci_send_tuning(struct sdhci_host *host, u32 opcode) 575 { 576 struct mmc_cmd cmd; 577 578 cmd.cmdidx = opcode; 579 cmd.resp_type = MMC_RSP_R1; 580 cmd.cmdarg = 0; 581 /* 582 * In response to CMD19, the card sends 64 bytes of tuning 583 * block to the Host Controller. So we set the block size 584 * to 64 here. 585 */ 586 if (opcode == MMC_SEND_TUNING_BLOCK_HS200 && 587 host->mmc->bus_width == MMC_BUS_WIDTH_8BIT) 588 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128), SDHCI_BLOCK_SIZE); 589 else 590 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE); 591 592 /* 593 * The tuning block is sent by the card to the host controller. 594 * So we set the TRNS_READ bit in the Transfer Mode register. 595 * This also takes care of setting DMA Enable and Multi Block 596 * Select in the same register to 0. 597 */ 598 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); 599 600 #ifdef CONFIG_DM_MMC 601 return sdhci_send_command(host->mmc->dev, &cmd, NULL); 602 #else 603 return sdhci_send_command(host->mmc, &cmd, NULL); 604 #endif 605 } 606 607 #define MAX_TUNING_LOOP 40 608 static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) 609 { 610 int i; 611 int ret; 612 613 /* 614 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number 615 * of loops reaches 40 times. 616 */ 617 for (i = 0; i < MAX_TUNING_LOOP; i++) { 618 u16 ctrl; 619 620 ret = sdhci_send_tuning(host, opcode); 621 622 if (ret) 623 return ret; 624 625 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 626 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) { 627 if (ctrl & SDHCI_CTRL_TUNED_CLK) 628 /* Tuning successfully */ 629 return 0; 630 break; 631 } 632 } 633 634 return -ETIMEDOUT; 635 } 636 637 #ifdef CONFIG_DM_MMC 638 static int sdhci_execute_tuning(struct udevice *dev, u32 opcode) 639 { 640 struct mmc *mmc = mmc_get_mmc_dev(dev); 641 #else 642 static int sdhci_execute_tuning(struct mmc *mmc, u32 opcode) 643 { 644 #endif 645 struct sdhci_host *host = mmc->priv; 646 u16 ctrl; 647 648 /* 649 * The Host Controller needs tuning in case of SDR104 and DDR50 650 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in 651 * the Capabilities register. 652 * If the Host Controller supports the HS200 mode then the 653 * tuning function has to be executed. 654 */ 655 switch (mmc->timing) { 656 /* HS400 tuning is done in HS200 mode */ 657 case MMC_TIMING_MMC_HS400: 658 return -EINVAL; 659 case MMC_TIMING_MMC_HS200: 660 /* 661 * Periodic re-tuning for HS400 is not expected to be needed, so 662 * disable it here. 663 */ 664 break; 665 default: 666 return -EINVAL; 667 } 668 669 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 670 ctrl |= SDHCI_CTRL_EXEC_TUNING; 671 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 672 673 return __sdhci_execute_tuning(host, opcode); 674 } 675 676 #ifdef CONFIG_DM_MMC 677 int sdhci_probe(struct udevice *dev) 678 { 679 struct mmc *mmc = mmc_get_mmc_dev(dev); 680 681 return sdhci_init(mmc); 682 } 683 684 const struct dm_mmc_ops sdhci_ops = { 685 .card_busy = sdhci_card_busy, 686 .send_cmd = sdhci_send_command, 687 .set_ios = sdhci_set_ios, 688 .execute_tuning = sdhci_execute_tuning, 689 }; 690 #else 691 static const struct mmc_ops sdhci_ops = { 692 .card_busy = sdhci_card_busy, 693 .send_cmd = sdhci_send_command, 694 .set_ios = sdhci_set_ios, 695 .init = sdhci_init, 696 .execute_tuning = sdhci_execute_tuning, 697 }; 698 #endif 699 700 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, 701 u32 f_max, u32 f_min) 702 { 703 u32 caps, caps_1; 704 705 caps = sdhci_readl(host, SDHCI_CAPABILITIES); 706 707 #ifdef CONFIG_MMC_SDHCI_SDMA 708 if (!(caps & SDHCI_CAN_DO_SDMA)) { 709 printf("%s: Your controller doesn't support SDMA!!\n", 710 __func__); 711 return -EINVAL; 712 } 713 #endif 714 if (host->quirks & SDHCI_QUIRK_REG32_RW) 715 host->version = 716 sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16; 717 else 718 host->version = sdhci_readw(host, SDHCI_HOST_VERSION); 719 720 cfg->name = host->name; 721 #ifndef CONFIG_DM_MMC 722 cfg->ops = &sdhci_ops; 723 #endif 724 725 /* Check whether the clock multiplier is supported or not */ 726 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { 727 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); 728 host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >> 729 SDHCI_CLOCK_MUL_SHIFT; 730 } 731 732 if (host->max_clk == 0) { 733 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) 734 host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> 735 SDHCI_CLOCK_BASE_SHIFT; 736 else 737 host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >> 738 SDHCI_CLOCK_BASE_SHIFT; 739 host->max_clk *= 1000000; 740 if (host->clk_mul) 741 host->max_clk *= host->clk_mul; 742 } 743 if (host->max_clk == 0) { 744 printf("%s: Hardware doesn't specify base clock frequency\n", 745 __func__); 746 return -EINVAL; 747 } 748 if (f_max && (f_max < host->max_clk)) 749 cfg->f_max = f_max; 750 else 751 cfg->f_max = host->max_clk; 752 if (f_min) 753 cfg->f_min = f_min; 754 else { 755 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) 756 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300; 757 else 758 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200; 759 } 760 cfg->voltages = 0; 761 if (caps & SDHCI_CAN_VDD_330) 762 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34; 763 if (caps & SDHCI_CAN_VDD_300) 764 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31; 765 if (caps & SDHCI_CAN_VDD_180) 766 cfg->voltages |= MMC_VDD_165_195; 767 768 if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE) 769 cfg->voltages |= host->voltages; 770 771 cfg->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT; 772 773 /* Since Host Controller Version3.0 */ 774 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { 775 if (!(caps & SDHCI_CAN_DO_8BIT)) 776 cfg->host_caps &= ~MMC_MODE_8BIT; 777 } 778 779 if (host->host_caps) 780 cfg->host_caps |= host->host_caps; 781 782 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 783 784 return 0; 785 } 786 787 #ifdef CONFIG_BLK 788 int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg) 789 { 790 return mmc_bind(dev, mmc, cfg); 791 } 792 #else 793 int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min) 794 { 795 int ret; 796 797 ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min); 798 if (ret) 799 return ret; 800 801 host->mmc = mmc_create(&host->cfg, host); 802 if (host->mmc == NULL) { 803 printf("%s: mmc create fail!\n", __func__); 804 return -ENOMEM; 805 } 806 807 return 0; 808 } 809 #endif 810