1 /* 2 * (C) Copyright 2016 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * Rockchip SD Host Controller Interface 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <asm/arch/hardware.h> 10 #include <common.h> 11 #include <dm.h> 12 #include <dt-structs.h> 13 #include <linux/libfdt.h> 14 #include <malloc.h> 15 #include <mapmem.h> 16 #include <sdhci.h> 17 #include <clk.h> 18 #include <syscon.h> 19 #include <dm/ofnode.h> 20 #include <asm/arch/clock.h> 21 22 DECLARE_GLOBAL_DATA_PTR; 23 /* 400KHz is max freq for card ID etc. Use that as min */ 24 #define EMMC_MIN_FREQ 400000 25 #define KHz (1000) 26 #define MHz (1000 * KHz) 27 28 #define PHYCTRL_CALDONE_MASK 0x1 29 #define PHYCTRL_CALDONE_SHIFT 0x6 30 #define PHYCTRL_CALDONE_DONE 0x1 31 #define PHYCTRL_DLLRDY_MASK 0x1 32 #define PHYCTRL_DLLRDY_SHIFT 0x5 33 #define PHYCTRL_DLLRDY_DONE 0x1 34 #define PHYCTRL_FREQSEL_200M 0x0 35 #define PHYCTRL_FREQSEL_50M 0x1 36 #define PHYCTRL_FREQSEL_100M 0x2 37 #define PHYCTRL_FREQSEL_150M 0x3 38 #define PHYCTRL_DLL_LOCK_WO_TMOUT(x) \ 39 ((((x) >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK) ==\ 40 PHYCTRL_DLLRDY_DONE) 41 42 /* Rockchip specific Registers */ 43 #define DWCMSHC_EMMC_DLL_CTRL 0x800 44 #define DWCMSHC_EMMC_DLL_CTRL_RESET BIT(1) 45 #define DWCMSHC_EMMC_DLL_RXCLK 0x804 46 #define DWCMSHC_EMMC_DLL_TXCLK 0x808 47 #define DWCMSHC_EMMC_DLL_STRBIN 0x80c 48 #define DECMSHC_EMMC_DLL_CMDOUT 0x810 49 #define DWCMSHC_EMMC_DLL_STATUS0 0x840 50 #define DWCMSHC_EMMC_DLL_STATUS1 0x844 51 #define DWCMSHC_EMMC_DLL_START BIT(0) 52 #define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL 29 53 #define DWCMSHC_EMMC_DLL_START_POINT 16 54 #define DWCMSHC_EMMC_DLL_START_DEFAULT 5 55 #define DWCMSHC_EMMC_DLL_INC_VALUE 2 56 #define DWCMSHC_EMMC_DLL_INC 8 57 #define DWCMSHC_EMMC_DLL_DLYENA BIT(27) 58 #define DLL_TXCLK_TAPNUM_DEFAULT 0x10 59 #define DLL_TXCLK_TAPNUM_90_DEGREES 0x8 60 #define DLL_STRBIN_TAPNUM_DEFAULT 0x3 61 #define DLL_TXCLK_TAPNUM_FROM_SW BIT(24) 62 #define DWCMSHC_EMMC_DLL_LOCKED BIT(8) 63 #define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9) 64 #define DLL_RXCLK_NO_INVERTER 1 65 #define DLL_RXCLK_INVERTER 0 66 #define DLL_CMDOUT_TAPNUM_90_DEGREES 0x8 67 #define DLL_CMDOUT_TAPNUM_FROM_SW BIT(24) 68 #define DLL_CMDOUT_SRC_CLK_NEG BIT(28) 69 70 #define DWCMSHC_ENHANCED_STROBE BIT(8) 71 #define DLL_LOCK_WO_TMOUT(x) \ 72 ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \ 73 (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0)) 74 #define ROCKCHIP_MAX_CLKS 3 75 76 struct rockchip_sdhc_plat { 77 #if CONFIG_IS_ENABLED(OF_PLATDATA) 78 struct dtd_rockchip_rk3399_sdhci_5_1 dtplat; 79 #endif 80 struct mmc_config cfg; 81 struct mmc mmc; 82 }; 83 84 struct rockchip_emmc_phy { 85 u32 emmcphy_con[7]; 86 u32 reserved; 87 u32 emmcphy_status; 88 }; 89 90 struct rockchip_sdhc { 91 struct sdhci_host host; 92 struct udevice *dev; 93 void *base; 94 struct rockchip_emmc_phy *phy; 95 struct clk emmc_clk; 96 }; 97 98 struct sdhci_data { 99 int (*emmc_set_clock)(struct sdhci_host *host, unsigned int clock); 100 int (*get_phy)(struct udevice *dev); 101 u32 flags; 102 #define RK_DLL_CMD_OUT BIT(1) 103 #define RK_RXCLK_NO_INVERTER BIT(2) 104 }; 105 106 static void rk3399_emmc_phy_power_on(struct rockchip_emmc_phy *phy, u32 clock) 107 { 108 u32 caldone, dllrdy, freqsel; 109 uint start; 110 111 writel(RK_CLRSETBITS(7 << 4, 0), &phy->emmcphy_con[6]); 112 writel(RK_CLRSETBITS(1 << 11, 1 << 11), &phy->emmcphy_con[0]); 113 writel(RK_CLRSETBITS(0xf << 7, 6 << 7), &phy->emmcphy_con[0]); 114 115 /* 116 * According to the user manual, calpad calibration 117 * cycle takes more than 2us without the minimal recommended 118 * value, so we may need a little margin here 119 */ 120 udelay(3); 121 writel(RK_CLRSETBITS(1, 1), &phy->emmcphy_con[6]); 122 123 /* 124 * According to the user manual, it asks driver to 125 * wait 5us for calpad busy trimming. But it seems that 126 * 5us of caldone isn't enough for all cases. 127 */ 128 udelay(500); 129 caldone = readl(&phy->emmcphy_status); 130 caldone = (caldone >> PHYCTRL_CALDONE_SHIFT) & PHYCTRL_CALDONE_MASK; 131 if (caldone != PHYCTRL_CALDONE_DONE) { 132 printf("%s: caldone timeout.\n", __func__); 133 return; 134 } 135 136 /* Set the frequency of the DLL operation */ 137 if (clock < 75 * MHz) 138 freqsel = PHYCTRL_FREQSEL_50M; 139 else if (clock < 125 * MHz) 140 freqsel = PHYCTRL_FREQSEL_100M; 141 else if (clock < 175 * MHz) 142 freqsel = PHYCTRL_FREQSEL_150M; 143 else 144 freqsel = PHYCTRL_FREQSEL_200M; 145 146 /* Set the frequency of the DLL operation */ 147 writel(RK_CLRSETBITS(3 << 12, freqsel << 12), &phy->emmcphy_con[0]); 148 writel(RK_CLRSETBITS(1 << 1, 1 << 1), &phy->emmcphy_con[6]); 149 150 /* REN Enable on STRB Line for HS400 */ 151 writel(RK_CLRSETBITS(0, 1 << 9), &phy->emmcphy_con[2]); 152 153 start = get_timer(0); 154 155 do { 156 udelay(1); 157 dllrdy = readl(&phy->emmcphy_status); 158 dllrdy = (dllrdy >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK; 159 if (dllrdy == PHYCTRL_DLLRDY_DONE) 160 break; 161 } while (get_timer(start) < 50000); 162 163 if (dllrdy != PHYCTRL_DLLRDY_DONE) 164 printf("%s: dllrdy timeout.\n", __func__); 165 } 166 167 static void rk3399_emmc_phy_power_off(struct rockchip_emmc_phy *phy) 168 { 169 writel(RK_CLRSETBITS(1, 0), &phy->emmcphy_con[6]); 170 writel(RK_CLRSETBITS(1 << 1, 0), &phy->emmcphy_con[6]); 171 } 172 173 static int rockchip_emmc_set_clock(struct sdhci_host *host, unsigned int clock) 174 { 175 unsigned int div, clk = 0, timeout; 176 unsigned int input_clk; 177 struct rockchip_sdhc *priv = 178 container_of(host, struct rockchip_sdhc, host); 179 180 /* Wait max 20 ms */ 181 timeout = 200; 182 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & 183 (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) { 184 if (timeout == 0) { 185 printf("%s: Timeout to wait cmd & data inhibit\n", 186 __func__); 187 return -EBUSY; 188 } 189 190 timeout--; 191 udelay(100); 192 } 193 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 194 195 if (clock == 0) 196 return 0; 197 198 input_clk = clk_set_rate(&priv->emmc_clk, clock); 199 if (IS_ERR_VALUE(input_clk)) 200 input_clk = host->max_clk; 201 202 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { 203 /* 204 * Check if the Host Controller supports Programmable Clock 205 * Mode. 206 */ 207 if (host->clk_mul) { 208 for (div = 1; div <= 1024; div++) { 209 if ((input_clk / div) <= clock) 210 break; 211 } 212 213 /* 214 * Set Programmable Clock Mode in the Clock 215 * Control register. 216 */ 217 clk = SDHCI_PROG_CLOCK_MODE; 218 div--; 219 } else { 220 /* Version 3.00 divisors must be a multiple of 2. */ 221 if (input_clk <= clock) { 222 div = 1; 223 } else { 224 for (div = 2; 225 div < SDHCI_MAX_DIV_SPEC_300; 226 div += 2) { 227 if ((input_clk / div) <= clock) 228 break; 229 } 230 } 231 div >>= 1; 232 } 233 } else { 234 /* Version 2.00 divisors must be a power of 2. */ 235 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { 236 if ((input_clk / div) <= clock) 237 break; 238 } 239 div >>= 1; 240 } 241 242 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; 243 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) 244 << SDHCI_DIVIDER_HI_SHIFT; 245 clk |= SDHCI_CLOCK_INT_EN; 246 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 247 248 /* Wait max 20 ms */ 249 timeout = 20; 250 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 251 & SDHCI_CLOCK_INT_STABLE)) { 252 if (timeout == 0) { 253 printf("%s: Internal clock never stabilised.\n", 254 __func__); 255 return -EBUSY; 256 } 257 timeout--; 258 udelay(1000); 259 } 260 clk |= SDHCI_CLOCK_CARD_EN; 261 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 262 host->clock = clock; 263 264 return 0; 265 } 266 267 static int rk3399_emmc_get_phy(struct udevice *dev) 268 { 269 struct rockchip_sdhc *priv = dev_get_priv(dev); 270 271 #if CONFIG_IS_ENABLED(OF_PLATDATA) 272 priv->phy = (struct rockchip_emmc_phy *)0xff77f780; 273 #else 274 ofnode phy_node; 275 void *grf_base; 276 u32 grf_phy_offset, phandle; 277 278 phandle = dev_read_u32_default(dev, "phys", 0); 279 phy_node = ofnode_get_by_phandle(phandle); 280 if (!ofnode_valid(phy_node)) { 281 debug("Not found emmc phy device\n"); 282 return -ENODEV; 283 } 284 285 grf_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 286 if (grf_base < 0) 287 printf("%s Get syscon grf failed", __func__); 288 grf_phy_offset = ofnode_read_u32_default(phy_node, "reg", 0); 289 290 priv->phy = (struct rockchip_emmc_phy *)(grf_base + grf_phy_offset); 291 #endif 292 return 0; 293 } 294 295 static int rk3399_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clock) 296 { 297 struct rockchip_sdhc *priv = 298 container_of(host, struct rockchip_sdhc, host); 299 int cycle_phy = host->clock != clock && 300 clock > EMMC_MIN_FREQ; 301 302 if (cycle_phy) 303 rk3399_emmc_phy_power_off(priv->phy); 304 305 rockchip_emmc_set_clock(host, clock); 306 307 if (cycle_phy) 308 rk3399_emmc_phy_power_on(priv->phy, clock); 309 310 return 0; 311 } 312 313 static int dwcmshc_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clock) 314 { 315 struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host); 316 struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev); 317 u32 txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT, extra; 318 int timeout = 500, ret; 319 320 ret = rockchip_emmc_set_clock(host, clock); 321 322 if (clock >= 100 * MHz) { 323 /* reset DLL */ 324 sdhci_writel(host, DWCMSHC_EMMC_DLL_CTRL_RESET, DWCMSHC_EMMC_DLL_CTRL); 325 udelay(1); 326 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL); 327 328 /* Init DLL settings */ 329 extra = DWCMSHC_EMMC_DLL_START_DEFAULT << DWCMSHC_EMMC_DLL_START_POINT | 330 DWCMSHC_EMMC_DLL_INC_VALUE << DWCMSHC_EMMC_DLL_INC | 331 DWCMSHC_EMMC_DLL_START; 332 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL); 333 334 while (1) { 335 if (timeout < 0) 336 return -ETIMEDOUT; 337 if (DLL_LOCK_WO_TMOUT((sdhci_readl(host, DWCMSHC_EMMC_DLL_STATUS0)))) 338 break; 339 udelay(1); 340 timeout--; 341 } 342 extra = DWCMSHC_EMMC_DLL_DLYENA; 343 if (data->flags & RK_RXCLK_NO_INVERTER) 344 extra |= DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL; 345 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK); 346 347 if ((data->flags & RK_DLL_CMD_OUT) && 348 (host->mmc->timing == MMC_TIMING_MMC_HS400 || 349 host->mmc->timing == MMC_TIMING_MMC_HS400ES)) { 350 351 txclk_tapnum = DLL_TXCLK_TAPNUM_90_DEGREES; 352 353 extra = DWCMSHC_EMMC_DLL_DLYENA | 354 DLL_CMDOUT_TAPNUM_90_DEGREES | 355 DLL_CMDOUT_TAPNUM_FROM_SW | 356 DLL_CMDOUT_SRC_CLK_NEG; 357 sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT); 358 } 359 360 extra = DWCMSHC_EMMC_DLL_DLYENA | 361 DLL_TXCLK_TAPNUM_FROM_SW | 362 txclk_tapnum; 363 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK); 364 365 extra = DWCMSHC_EMMC_DLL_DLYENA | 366 DLL_STRBIN_TAPNUM_DEFAULT; 367 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN); 368 } else { 369 /* reset the clock phase when the frequency is lower than 100MHz */ 370 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL); 371 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_RXCLK); 372 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK); 373 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN); 374 sdhci_writel(host, 0, DECMSHC_EMMC_DLL_CMDOUT); 375 } 376 377 return ret; 378 } 379 380 static int dwcmshc_emmc_get_phy(struct udevice *dev) 381 { 382 return 0; 383 } 384 385 static int rockchip_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 386 { 387 struct rockchip_sdhc *priv = 388 container_of(host, struct rockchip_sdhc, host); 389 struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev); 390 if (!data) 391 return -EINVAL; 392 393 return data->emmc_set_clock(host, clock); 394 } 395 396 static struct sdhci_ops rockchip_sdhci_ops = { 397 .set_clock = rockchip_sdhci_set_clock, 398 }; 399 400 static int rockchip_sdhci_probe(struct udevice *dev) 401 { 402 struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(dev); 403 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 404 struct rockchip_sdhc_plat *plat = dev_get_platdata(dev); 405 struct rockchip_sdhc *prv = dev_get_priv(dev); 406 struct sdhci_host *host = &prv->host; 407 int max_frequency, ret; 408 struct clk clk; 409 410 #if CONFIG_IS_ENABLED(OF_PLATDATA) 411 struct dtd_rockchip_rk3399_sdhci_5_1 *dtplat = &plat->dtplat; 412 413 host->name = dev->name; 414 host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]); 415 host->host_caps |= MMC_MODE_8BIT; 416 max_frequency = dtplat->max_frequency; 417 ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &clk); 418 #else 419 max_frequency = dev_read_u32_default(dev, "max-frequency", 0); 420 switch (dev_read_u32_default(dev, "bus-width", 4)) { 421 case 8: 422 host->host_caps |= MMC_MODE_8BIT; 423 break; 424 case 4: 425 host->host_caps |= MMC_MODE_4BIT; 426 break; 427 case 1: 428 break; 429 default: 430 printf("Invalid \"bus-width\" value\n"); 431 return -EINVAL; 432 } 433 ret = clk_get_by_index(dev, 0, &clk); 434 #endif 435 if (!ret) { 436 ret = clk_set_rate(&clk, max_frequency); 437 if (IS_ERR_VALUE(ret)) 438 printf("%s clk set rate fail!\n", __func__); 439 } else { 440 printf("%s fail to get clk\n", __func__); 441 } 442 443 prv->emmc_clk = clk; 444 prv->dev = dev; 445 ret = data->get_phy(dev); 446 if (ret) 447 return ret; 448 449 host->ops = &rockchip_sdhci_ops; 450 451 host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD; 452 host->max_clk = max_frequency; 453 454 if (dev_read_bool(dev, "mmc-hs200-1_8v")) 455 host->host_caps |= MMC_MODE_HS200; 456 else if (dev_read_bool(dev, "mmc-hs400-1_8v")) 457 host->host_caps |= MMC_MODE_HS400; 458 ret = sdhci_setup_cfg(&plat->cfg, host, 0, EMMC_MIN_FREQ); 459 460 host->mmc = &plat->mmc; 461 if (ret) 462 return ret; 463 host->mmc->priv = &prv->host; 464 host->mmc->dev = dev; 465 upriv->mmc = host->mmc; 466 467 return sdhci_probe(dev); 468 } 469 470 static int rockchip_sdhci_of_to_plat(struct udevice *dev) 471 { 472 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 473 struct sdhci_host *host = dev_get_priv(dev); 474 475 host->name = dev->name; 476 host->ioaddr = dev_read_addr_ptr(dev); 477 #endif 478 479 return 0; 480 } 481 482 static int rockchip_sdhci_bind(struct udevice *dev) 483 { 484 struct rockchip_sdhc_plat *plat = dev_get_platdata(dev); 485 486 return sdhci_bind(dev, &plat->mmc, &plat->cfg); 487 } 488 489 static const struct sdhci_data arasan_data = { 490 .emmc_set_clock = rk3399_sdhci_emmc_set_clock, 491 .get_phy = rk3399_emmc_get_phy, 492 }; 493 494 static const struct sdhci_data rk3568_data = { 495 .emmc_set_clock = dwcmshc_sdhci_emmc_set_clock, 496 .get_phy = dwcmshc_emmc_get_phy, 497 .flags = RK_RXCLK_NO_INVERTER, 498 }; 499 500 static const struct sdhci_data rk3588_data = { 501 .emmc_set_clock = dwcmshc_sdhci_emmc_set_clock, 502 .get_phy = dwcmshc_emmc_get_phy, 503 .flags = RK_DLL_CMD_OUT, 504 }; 505 506 static const struct udevice_id sdhci_ids[] = { 507 { 508 .compatible = "arasan,sdhci-5.1", 509 .data = (ulong)&arasan_data, 510 }, 511 { 512 .compatible = "snps,dwcmshc-sdhci", 513 .data = (ulong)&rk3568_data, 514 }, 515 { 516 .compatible = "rockchip,rk3588-dwcmshc", 517 .data = (ulong)&rk3588_data, 518 }, 519 { } 520 }; 521 522 U_BOOT_DRIVER(arasan_sdhci_drv) = { 523 .name = "rockchip_sdhci_5_1", 524 .id = UCLASS_MMC, 525 .of_match = sdhci_ids, 526 .ofdata_to_platdata = rockchip_sdhci_of_to_plat, 527 .ops = &sdhci_ops, 528 .bind = rockchip_sdhci_bind, 529 .probe = rockchip_sdhci_probe, 530 .priv_auto_alloc_size = sizeof(struct rockchip_sdhc), 531 .platdata_auto_alloc_size = sizeof(struct rockchip_sdhc_plat), 532 }; 533