1 /* 2 * (C) Copyright 2016 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * Rockchip SD Host Controller Interface 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <asm/arch/hardware.h> 10 #include <common.h> 11 #include <dm.h> 12 #include <dt-structs.h> 13 #include <linux/libfdt.h> 14 #include <malloc.h> 15 #include <mapmem.h> 16 #include <sdhci.h> 17 #include <clk.h> 18 #include <syscon.h> 19 #include <dm/ofnode.h> 20 #include <asm/arch/clock.h> 21 22 DECLARE_GLOBAL_DATA_PTR; 23 /* 400KHz is max freq for card ID etc. Use that as min */ 24 #define EMMC_MIN_FREQ 400000 25 #define KHz (1000) 26 #define MHz (1000 * KHz) 27 28 #define PHYCTRL_CALDONE_MASK 0x1 29 #define PHYCTRL_CALDONE_SHIFT 0x6 30 #define PHYCTRL_CALDONE_DONE 0x1 31 #define PHYCTRL_DLLRDY_MASK 0x1 32 #define PHYCTRL_DLLRDY_SHIFT 0x5 33 #define PHYCTRL_DLLRDY_DONE 0x1 34 #define PHYCTRL_FREQSEL_200M 0x0 35 #define PHYCTRL_FREQSEL_50M 0x1 36 #define PHYCTRL_FREQSEL_100M 0x2 37 #define PHYCTRL_FREQSEL_150M 0x3 38 39 /* Rockchip specific Registers */ 40 #define DWCMSHC_EMMC_DLL_CTRL 0x800 41 #define DWCMSHC_EMMC_DLL_TXCLK 0x804 42 #define DWCMSHC_EMMC_DLL_RXCLK 0x808 43 #define DWCMSHC_EMMC_DLL_STRBIN 0x80c 44 #define DWCMSHC_EMMC_DLL_STATUS0 0x820 45 #define DWCMSHC_EMMC_DLL_START BIT(0) 46 #define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL 29 47 #define DWCMSHC_EMMC_DLL_START_POINT 16 48 #define DWCMSHC_EMMC_DLL_INC 8 49 #define DWCMSHC_EMMC_DLL_DLYENA BIT(27) 50 #define DLL_RXCLK_TAPNUM_DEFAULT 0x3 51 #define DLL_STRBIN_TAPNUM_DEFAULT 0x3 52 #define DLL_RXCLK_TAPNUM_FROM_SW BIT(24) 53 #define DWCMSHC_EMMC_DLL_LOCKED BIT(8) 54 #define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9) 55 #define DLL_RXCLK_NO_INVERTER 1 56 #define DLL_RXCLK_INVERTER 0 57 #define DWCMSHC_ENHANCED_STROBE BIT(8) 58 #define DLL_LOCK_WO_TMOUT(x) \ 59 ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \ 60 (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0)) 61 #define ROCKCHIP_MAX_CLKS 3 62 63 struct rockchip_sdhc_plat { 64 #if CONFIG_IS_ENABLED(OF_PLATDATA) 65 struct dtd_rockchip_rk3399_sdhci_5_1 dtplat; 66 #endif 67 struct mmc_config cfg; 68 struct mmc mmc; 69 }; 70 71 struct rockchip_emmc_phy { 72 u32 emmcphy_con[7]; 73 u32 reserved; 74 u32 emmcphy_status; 75 }; 76 77 struct rockchip_sdhc { 78 struct sdhci_host host; 79 struct udevice *dev; 80 void *base; 81 struct rockchip_emmc_phy *phy; 82 struct clk emmc_clk; 83 }; 84 85 struct sdhci_data { 86 int (*emmc_set_clock)(struct sdhci_host *host, unsigned int clock); 87 int (*emmc_phy_init)(struct udevice *dev); 88 int (*get_phy)(struct udevice *dev); 89 }; 90 91 static int rk3399_emmc_phy_init(struct udevice *dev) 92 { 93 return 0; 94 } 95 96 static void rk3399_emmc_phy_power_on(struct rockchip_emmc_phy *phy, u32 clock) 97 { 98 u32 caldone, dllrdy, freqsel; 99 uint start; 100 101 writel(RK_CLRSETBITS(7 << 4, 0), &phy->emmcphy_con[6]); 102 writel(RK_CLRSETBITS(1 << 11, 1 << 11), &phy->emmcphy_con[0]); 103 writel(RK_CLRSETBITS(0xf << 7, 6 << 7), &phy->emmcphy_con[0]); 104 105 /* 106 * According to the user manual, calpad calibration 107 * cycle takes more than 2us without the minimal recommended 108 * value, so we may need a little margin here 109 */ 110 udelay(3); 111 writel(RK_CLRSETBITS(1, 1), &phy->emmcphy_con[6]); 112 113 /* 114 * According to the user manual, it asks driver to 115 * wait 5us for calpad busy trimming. But it seems that 116 * 5us of caldone isn't enough for all cases. 117 */ 118 udelay(500); 119 caldone = readl(&phy->emmcphy_status); 120 caldone = (caldone >> PHYCTRL_CALDONE_SHIFT) & PHYCTRL_CALDONE_MASK; 121 if (caldone != PHYCTRL_CALDONE_DONE) { 122 printf("%s: caldone timeout.\n", __func__); 123 return; 124 } 125 126 /* Set the frequency of the DLL operation */ 127 if (clock < 75 * MHz) 128 freqsel = PHYCTRL_FREQSEL_50M; 129 else if (clock < 125 * MHz) 130 freqsel = PHYCTRL_FREQSEL_100M; 131 else if (clock < 175 * MHz) 132 freqsel = PHYCTRL_FREQSEL_150M; 133 else 134 freqsel = PHYCTRL_FREQSEL_200M; 135 136 /* Set the frequency of the DLL operation */ 137 writel(RK_CLRSETBITS(3 << 12, freqsel << 12), &phy->emmcphy_con[0]); 138 writel(RK_CLRSETBITS(1 << 1, 1 << 1), &phy->emmcphy_con[6]); 139 140 start = get_timer(0); 141 142 do { 143 udelay(1); 144 dllrdy = readl(&phy->emmcphy_status); 145 dllrdy = (dllrdy >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK; 146 if (dllrdy == PHYCTRL_DLLRDY_DONE) 147 break; 148 } while (get_timer(start) < 50000); 149 150 if (dllrdy != PHYCTRL_DLLRDY_DONE) 151 printf("%s: dllrdy timeout.\n", __func__); 152 } 153 154 static void rk3399_emmc_phy_power_off(struct rockchip_emmc_phy *phy) 155 { 156 writel(RK_CLRSETBITS(1, 0), &phy->emmcphy_con[6]); 157 writel(RK_CLRSETBITS(1 << 1, 0), &phy->emmcphy_con[6]); 158 } 159 160 static int rk3399_emmc_set_clock(struct sdhci_host *host, unsigned int clock) 161 { 162 unsigned int div, clk = 0, timeout; 163 unsigned int input_clk; 164 struct rockchip_sdhc *priv = 165 container_of(host, struct rockchip_sdhc, host); 166 167 /* Wait max 20 ms */ 168 timeout = 200; 169 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & 170 (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) { 171 if (timeout == 0) { 172 printf("%s: Timeout to wait cmd & data inhibit\n", 173 __func__); 174 return -EBUSY; 175 } 176 177 timeout--; 178 udelay(100); 179 } 180 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 181 182 if (clock == 0) 183 return 0; 184 185 input_clk = clk_set_rate(&priv->emmc_clk, clock); 186 if (IS_ERR_VALUE(input_clk)) 187 input_clk = host->max_clk; 188 189 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { 190 /* 191 * Check if the Host Controller supports Programmable Clock 192 * Mode. 193 */ 194 if (host->clk_mul) { 195 for (div = 1; div <= 1024; div++) { 196 if ((input_clk / div) <= clock) 197 break; 198 } 199 200 /* 201 * Set Programmable Clock Mode in the Clock 202 * Control register. 203 */ 204 clk = SDHCI_PROG_CLOCK_MODE; 205 div--; 206 } else { 207 /* Version 3.00 divisors must be a multiple of 2. */ 208 if (input_clk <= clock) { 209 div = 1; 210 } else { 211 for (div = 2; 212 div < SDHCI_MAX_DIV_SPEC_300; 213 div += 2) { 214 if ((input_clk / div) <= clock) 215 break; 216 } 217 } 218 div >>= 1; 219 } 220 } else { 221 /* Version 2.00 divisors must be a power of 2. */ 222 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { 223 if ((input_clk / div) <= clock) 224 break; 225 } 226 div >>= 1; 227 } 228 229 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; 230 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) 231 << SDHCI_DIVIDER_HI_SHIFT; 232 clk |= SDHCI_CLOCK_INT_EN; 233 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 234 235 /* Wait max 20 ms */ 236 timeout = 20; 237 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 238 & SDHCI_CLOCK_INT_STABLE)) { 239 if (timeout == 0) { 240 printf("%s: Internal clock never stabilised.\n", 241 __func__); 242 return -EBUSY; 243 } 244 timeout--; 245 udelay(1000); 246 } 247 clk |= SDHCI_CLOCK_CARD_EN; 248 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 249 host->clock = clock; 250 251 return 0; 252 } 253 254 static int rk3399_emmc_get_phy(struct udevice *dev) 255 { 256 struct rockchip_sdhc *priv = dev_get_priv(dev); 257 258 #if CONFIG_IS_ENABLED(OF_PLATDATA) 259 priv->phy = (struct rockchip_emmc_phy *)0xff77f780; 260 #else 261 ofnode phy_node; 262 void *grf_base; 263 u32 grf_phy_offset, phandle; 264 265 phandle = dev_read_u32_default(dev, "phys", 0); 266 phy_node = ofnode_get_by_phandle(phandle); 267 if (!ofnode_valid(phy_node)) { 268 debug("Not found emmc phy device\n"); 269 return -ENODEV; 270 } 271 272 grf_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 273 if (grf_base < 0) 274 printf("%s Get syscon grf failed", __func__); 275 grf_phy_offset = ofnode_read_u32_default(phy_node, "reg", 0); 276 277 priv->phy = (struct rockchip_emmc_phy *)(grf_base + grf_phy_offset); 278 #endif 279 return 0; 280 } 281 282 static int rk3399_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clock) 283 { 284 struct rockchip_sdhc *priv = 285 container_of(host, struct rockchip_sdhc, host); 286 int cycle_phy = host->clock != clock && 287 clock > EMMC_MIN_FREQ; 288 289 if (cycle_phy) 290 rk3399_emmc_phy_power_off(priv->phy); 291 292 rk3399_emmc_set_clock(host, clock); 293 294 if (cycle_phy) 295 rk3399_emmc_phy_power_on(priv->phy, clock); 296 297 return 0; 298 } 299 300 static int rk3568_emmc_phy_init(struct udevice *dev) 301 { 302 struct rockchip_sdhc *prv = dev_get_priv(dev); 303 struct sdhci_host *host = &prv->host; 304 u32 extra; 305 int timeout = 500; 306 307 sdhci_writel(host, BIT(1), DWCMSHC_EMMC_DLL_CTRL); 308 udelay(1); 309 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL); 310 /* Init DLL settings */ 311 extra = 0x5 << DWCMSHC_EMMC_DLL_START_POINT | 312 0x2 << DWCMSHC_EMMC_DLL_INC | 313 DWCMSHC_EMMC_DLL_START; 314 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL); 315 while(1) { 316 if (timeout < 0) 317 return ETIMEDOUT; 318 if (sdhci_readl(host, DWCMSHC_EMMC_DLL_STATUS0) == DLL_LOCK_WO_TMOUT(extra)) 319 break; 320 udelay(1); 321 timeout--; 322 } 323 324 /* FixMe: clk inverter? */ 325 extra = DWCMSHC_EMMC_DLL_DLYENA | 326 DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL; 327 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK); 328 extra = DWCMSHC_EMMC_DLL_DLYENA | 329 DLL_RXCLK_TAPNUM_DEFAULT | 330 DLL_RXCLK_TAPNUM_FROM_SW; 331 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK); 332 extra = DWCMSHC_EMMC_DLL_DLYENA | 333 DLL_STRBIN_TAPNUM_DEFAULT; 334 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN); 335 336 return 0; 337 } 338 339 static int rk3568_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clock) 340 { 341 return rk3399_emmc_set_clock(host, clock); 342 } 343 344 static int rk3568_emmc_get_phy(struct udevice *dev) 345 { 346 return 0; 347 } 348 349 static int arasan_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 350 { 351 struct rockchip_sdhc *priv = 352 container_of(host, struct rockchip_sdhc, host); 353 struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev); 354 if (!data) 355 return -EINVAL; 356 357 return data->emmc_set_clock(host, clock); 358 } 359 360 static struct sdhci_ops arasan_sdhci_ops = { 361 .set_clock = arasan_sdhci_set_clock, 362 }; 363 364 static int arasan_sdhci_probe(struct udevice *dev) 365 { 366 struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(dev); 367 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 368 struct rockchip_sdhc_plat *plat = dev_get_platdata(dev); 369 struct rockchip_sdhc *prv = dev_get_priv(dev); 370 struct sdhci_host *host = &prv->host; 371 int max_frequency, ret; 372 struct clk clk; 373 374 #if CONFIG_IS_ENABLED(OF_PLATDATA) 375 struct dtd_rockchip_rk3399_sdhci_5_1 *dtplat = &plat->dtplat; 376 377 host->name = dev->name; 378 host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]); 379 host->host_caps |= MMC_MODE_8BIT; 380 max_frequency = dtplat->max_frequency; 381 ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &clk); 382 #else 383 max_frequency = dev_read_u32_default(dev, "max-frequency", 0); 384 switch (dev_read_u32_default(dev, "bus-width", 4)) { 385 case 8: 386 host->host_caps |= MMC_MODE_8BIT; 387 break; 388 case 4: 389 host->host_caps |= MMC_MODE_4BIT; 390 break; 391 case 1: 392 break; 393 default: 394 printf("Invalid \"bus-width\" value\n"); 395 return -EINVAL; 396 } 397 ret = clk_get_by_index(dev, 0, &clk); 398 #endif 399 if (!ret) { 400 ret = clk_set_rate(&clk, max_frequency); 401 if (IS_ERR_VALUE(ret)) 402 printf("%s clk set rate fail!\n", __func__); 403 } else { 404 printf("%s fail to get clk\n", __func__); 405 } 406 407 prv->emmc_clk = clk; 408 prv->dev = dev; 409 ret = data->get_phy(dev); 410 if (ret) 411 return ret; 412 413 ret = data->emmc_phy_init(dev); 414 if (ret) 415 return ret; 416 417 host->ops = &arasan_sdhci_ops; 418 419 host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD; 420 host->max_clk = max_frequency; 421 422 if (dev_read_bool(dev, "mmc-hs200-1_8v")) 423 host->host_caps |= MMC_MODE_HS200; 424 else if (dev_read_bool(dev, "mmc-hs400-1_8v")) 425 host->host_caps |= MMC_MODE_HS400; 426 ret = sdhci_setup_cfg(&plat->cfg, host, 0, EMMC_MIN_FREQ); 427 428 host->mmc = &plat->mmc; 429 if (ret) 430 return ret; 431 host->mmc->priv = &prv->host; 432 host->mmc->dev = dev; 433 upriv->mmc = host->mmc; 434 435 return sdhci_probe(dev); 436 } 437 438 static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev) 439 { 440 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 441 struct sdhci_host *host = dev_get_priv(dev); 442 443 host->name = dev->name; 444 host->ioaddr = dev_read_addr_ptr(dev); 445 #endif 446 447 return 0; 448 } 449 450 static int rockchip_sdhci_bind(struct udevice *dev) 451 { 452 struct rockchip_sdhc_plat *plat = dev_get_platdata(dev); 453 454 return sdhci_bind(dev, &plat->mmc, &plat->cfg); 455 } 456 457 static const struct sdhci_data arasan_data = { 458 .emmc_set_clock = rk3399_sdhci_emmc_set_clock, 459 .get_phy = rk3399_emmc_get_phy, 460 .emmc_phy_init = rk3399_emmc_phy_init, 461 }; 462 463 static const struct sdhci_data snps_data = { 464 .emmc_set_clock = rk3568_sdhci_emmc_set_clock, 465 .get_phy = rk3568_emmc_get_phy, 466 .emmc_phy_init = rk3568_emmc_phy_init, 467 }; 468 469 static const struct udevice_id arasan_sdhci_ids[] = { 470 { 471 .compatible = "arasan,sdhci-5.1", 472 .data = (ulong)&arasan_data, 473 }, 474 { 475 .compatible = "snps,dwcmshc-sdhci", 476 .data = (ulong)&snps_data, 477 }, 478 { } 479 }; 480 481 U_BOOT_DRIVER(arasan_sdhci_drv) = { 482 .name = "rockchip_rk3399_sdhci_5_1", 483 .id = UCLASS_MMC, 484 .of_match = arasan_sdhci_ids, 485 .ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata, 486 .ops = &sdhci_ops, 487 .bind = rockchip_sdhci_bind, 488 .probe = arasan_sdhci_probe, 489 .priv_auto_alloc_size = sizeof(struct rockchip_sdhc), 490 .platdata_auto_alloc_size = sizeof(struct rockchip_sdhc_plat), 491 }; 492