1 /* 2 * (C) Copyright 2016 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * Rockchip SD Host Controller Interface 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <asm/arch/hardware.h> 10 #include <common.h> 11 #include <dm.h> 12 #include <dt-structs.h> 13 #include <linux/libfdt.h> 14 #include <malloc.h> 15 #include <mapmem.h> 16 #include <sdhci.h> 17 #include <clk.h> 18 #include <syscon.h> 19 #include <dm/ofnode.h> 20 #include <asm/arch/clock.h> 21 22 DECLARE_GLOBAL_DATA_PTR; 23 /* 400KHz is max freq for card ID etc. Use that as min */ 24 #define EMMC_MIN_FREQ 400000 25 #define KHz (1000) 26 #define MHz (1000 * KHz) 27 28 #define PHYCTRL_CALDONE_MASK 0x1 29 #define PHYCTRL_CALDONE_SHIFT 0x6 30 #define PHYCTRL_CALDONE_DONE 0x1 31 #define PHYCTRL_DLLRDY_MASK 0x1 32 #define PHYCTRL_DLLRDY_SHIFT 0x5 33 #define PHYCTRL_DLLRDY_DONE 0x1 34 #define PHYCTRL_FREQSEL_200M 0x0 35 #define PHYCTRL_FREQSEL_50M 0x1 36 #define PHYCTRL_FREQSEL_100M 0x2 37 #define PHYCTRL_FREQSEL_150M 0x3 38 #define PHYCTRL_DLL_LOCK_WO_TMOUT(x) \ 39 ((((x) >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK) ==\ 40 PHYCTRL_DLLRDY_DONE) 41 42 #define ARASAN_VENDOR_REGISTER 0x78 43 #define ARASAN_VENDOR_ENHANCED_STROBE BIT(0) 44 45 /* DWC IP vendor area 1 pointer */ 46 #define DWCMSHC_P_VENDOR_AREA1 0xe8 47 #define DWCMSHC_AREA1_MASK GENMASK(11, 0) 48 /* Rockchip specific Registers */ 49 #define DWCMSHC_CTRL_HS400 0x7 50 #define DWCMSHC_CARD_IS_EMMC BIT(0) 51 #define DWCMSHC_ENHANCED_STROBE BIT(8) 52 53 #define DWCMSHC_HOST_CTRL3 0x508 54 #define DWCMSHC_EMMC_CONTROL 0x52c 55 #define DWCMSHC_EMMC_ATCTRL 0x540 56 #define DWCMSHC_EMMC_DLL_CTRL 0x800 57 #define DWCMSHC_EMMC_DLL_CTRL_RESET BIT(1) 58 #define DWCMSHC_EMMC_DLL_RXCLK 0x804 59 #define DWCMSHC_EMMC_DLL_TXCLK 0x808 60 #define DWCMSHC_EMMC_DLL_STRBIN 0x80c 61 #define DECMSHC_EMMC_DLL_CMDOUT 0x810 62 #define DWCMSHC_EMMC_DLL_STATUS0 0x840 63 #define DWCMSHC_EMMC_DLL_STATUS1 0x844 64 #define DWCMSHC_EMMC_DLL_START BIT(0) 65 #define DWCMSHC_EMMC_DLL_START_POINT 16 66 #define DWCMSHC_EMMC_DLL_START_DEFAULT 5 67 #define DWCMSHC_EMMC_DLL_INC_VALUE 2 68 #define DWCMSHC_EMMC_DLL_INC 8 69 #define DWCMSHC_EMMC_DLL_BYPASS BIT(24) 70 #define DWCMSHC_EMMC_DLL_DLYENA BIT(27) 71 #define DLL_TXCLK_TAPNUM_DEFAULT 0x10 72 #define DLL_TXCLK_TAPNUM_90_DEGREES 0x9 73 #define DLL_STRBIN_TAPNUM_DEFAULT 0x4 74 #define DLL_STRBIN_DELAY_NUM_OFFSET 16 75 #define DLL_STRBIN_TAPNUM_FROM_SW BIT(24) 76 #define DLL_STRBIN_DELAY_NUM_SEL BIT(26) 77 #define DLL_TXCLK_TAPNUM_FROM_SW BIT(24) 78 #define DLL_TXCLK_NO_INVERTER BIT(29) 79 #define DWCMSHC_EMMC_DLL_LOCKED BIT(8) 80 #define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9) 81 #define DLL_RXCLK_NO_INVERTER BIT(29) 82 #define DLL_RXCLK_ORI_GATE BIT(31) 83 #define DLL_CMDOUT_TAPNUM_90_DEGREES 0x8 84 #define DLL_CMDOUT_TAPNUM_FROM_SW BIT(24) 85 #define DLL_CMDOUT_SRC_CLK_NEG BIT(28) 86 #define DLL_CMDOUT_EN_SRC_CLK_NEG BIT(29) 87 #define DLL_CMDOUT_BOTH_CLK_EDGE BIT(30) 88 89 #define DWCMSHC_ENHANCED_STROBE BIT(8) 90 #define DLL_LOCK_WO_TMOUT(x) \ 91 ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \ 92 (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0)) 93 #define ROCKCHIP_MAX_CLKS 3 94 95 struct rockchip_sdhc_plat { 96 #if CONFIG_IS_ENABLED(OF_PLATDATA) 97 struct dtd_rockchip_rk3399_sdhci_5_1 dtplat; 98 #endif 99 struct mmc_config cfg; 100 struct mmc mmc; 101 }; 102 103 struct rockchip_emmc_phy { 104 u32 emmcphy_con[7]; 105 u32 reserved; 106 u32 emmcphy_status; 107 }; 108 109 struct rockchip_sdhc { 110 struct sdhci_host host; 111 struct udevice *dev; 112 void *base; 113 struct rockchip_emmc_phy *phy; 114 struct clk emmc_clk; 115 }; 116 117 struct sdhci_data { 118 int (*emmc_set_clock)(struct sdhci_host *host, unsigned int clock); 119 void (*set_ios_post)(struct sdhci_host *host); 120 int (*set_enhanced_strobe)(struct sdhci_host *host); 121 int (*get_phy)(struct udevice *dev); 122 u32 flags; 123 #define RK_DLL_CMD_OUT BIT(1) 124 #define RK_RXCLK_NO_INVERTER BIT(2) 125 126 u8 hs200_tx_tap; 127 u8 hs400_tx_tap; 128 u8 hs400_cmd_tap; 129 u8 hs400_strbin_tap; 130 u8 ddr50_strbin_delay_num; 131 }; 132 133 static void rk3399_emmc_phy_power_on(struct rockchip_emmc_phy *phy, u32 clock) 134 { 135 u32 caldone, dllrdy, freqsel; 136 uint start; 137 138 writel(RK_CLRSETBITS(7 << 4, 0), &phy->emmcphy_con[6]); 139 writel(RK_CLRSETBITS(1 << 11, 1 << 11), &phy->emmcphy_con[0]); 140 writel(RK_CLRSETBITS(0xf << 7, 6 << 7), &phy->emmcphy_con[0]); 141 142 /* 143 * According to the user manual, calpad calibration 144 * cycle takes more than 2us without the minimal recommended 145 * value, so we may need a little margin here 146 */ 147 udelay(3); 148 writel(RK_CLRSETBITS(1, 1), &phy->emmcphy_con[6]); 149 150 /* 151 * According to the user manual, it asks driver to 152 * wait 5us for calpad busy trimming. But it seems that 153 * 5us of caldone isn't enough for all cases. 154 */ 155 udelay(500); 156 caldone = readl(&phy->emmcphy_status); 157 caldone = (caldone >> PHYCTRL_CALDONE_SHIFT) & PHYCTRL_CALDONE_MASK; 158 if (caldone != PHYCTRL_CALDONE_DONE) { 159 printf("%s: caldone timeout.\n", __func__); 160 return; 161 } 162 163 /* Set the frequency of the DLL operation */ 164 if (clock < 75 * MHz) 165 freqsel = PHYCTRL_FREQSEL_50M; 166 else if (clock < 125 * MHz) 167 freqsel = PHYCTRL_FREQSEL_100M; 168 else if (clock < 175 * MHz) 169 freqsel = PHYCTRL_FREQSEL_150M; 170 else 171 freqsel = PHYCTRL_FREQSEL_200M; 172 173 /* Set the frequency of the DLL operation */ 174 writel(RK_CLRSETBITS(3 << 12, freqsel << 12), &phy->emmcphy_con[0]); 175 writel(RK_CLRSETBITS(1 << 1, 1 << 1), &phy->emmcphy_con[6]); 176 177 /* REN Enable on STRB Line for HS400 */ 178 writel(RK_CLRSETBITS(0, 1 << 9), &phy->emmcphy_con[2]); 179 180 start = get_timer(0); 181 182 do { 183 udelay(1); 184 dllrdy = readl(&phy->emmcphy_status); 185 dllrdy = (dllrdy >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK; 186 if (dllrdy == PHYCTRL_DLLRDY_DONE) 187 break; 188 } while (get_timer(start) < 50000); 189 190 if (dllrdy != PHYCTRL_DLLRDY_DONE) 191 printf("%s: dllrdy timeout.\n", __func__); 192 } 193 194 static void rk3399_emmc_phy_power_off(struct rockchip_emmc_phy *phy) 195 { 196 writel(RK_CLRSETBITS(1, 0), &phy->emmcphy_con[6]); 197 writel(RK_CLRSETBITS(1 << 1, 0), &phy->emmcphy_con[6]); 198 } 199 200 static int rockchip_emmc_set_clock(struct sdhci_host *host, unsigned int clock) 201 { 202 unsigned int div, clk = 0, timeout; 203 unsigned int input_clk; 204 struct rockchip_sdhc *priv = 205 container_of(host, struct rockchip_sdhc, host); 206 207 /* Wait max 20 ms */ 208 timeout = 200; 209 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & 210 (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) { 211 if (timeout == 0) { 212 printf("%s: Timeout to wait cmd & data inhibit\n", 213 __func__); 214 return -EBUSY; 215 } 216 217 timeout--; 218 udelay(100); 219 } 220 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 221 222 if (clock == 0) 223 return 0; 224 225 input_clk = clk_set_rate(&priv->emmc_clk, clock); 226 if (IS_ERR_VALUE(input_clk)) 227 input_clk = host->max_clk; 228 229 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { 230 /* 231 * Check if the Host Controller supports Programmable Clock 232 * Mode. 233 */ 234 if (host->clk_mul) { 235 for (div = 1; div <= 1024; div++) { 236 if ((input_clk / div) <= clock) 237 break; 238 } 239 240 /* 241 * Set Programmable Clock Mode in the Clock 242 * Control register. 243 */ 244 clk = SDHCI_PROG_CLOCK_MODE; 245 div--; 246 } else { 247 /* Version 3.00 divisors must be a multiple of 2. */ 248 if (input_clk <= clock) { 249 div = 1; 250 } else { 251 for (div = 2; 252 div < SDHCI_MAX_DIV_SPEC_300; 253 div += 2) { 254 if ((input_clk / div) <= clock) 255 break; 256 } 257 } 258 div >>= 1; 259 } 260 } else { 261 /* Version 2.00 divisors must be a power of 2. */ 262 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { 263 if ((input_clk / div) <= clock) 264 break; 265 } 266 div >>= 1; 267 } 268 269 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; 270 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) 271 << SDHCI_DIVIDER_HI_SHIFT; 272 clk |= SDHCI_CLOCK_INT_EN; 273 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 274 275 /* Wait max 20 ms */ 276 timeout = 20; 277 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 278 & SDHCI_CLOCK_INT_STABLE)) { 279 if (timeout == 0) { 280 printf("%s: Internal clock never stabilised.\n", 281 __func__); 282 return -EBUSY; 283 } 284 timeout--; 285 udelay(1000); 286 } 287 clk |= SDHCI_CLOCK_CARD_EN; 288 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 289 host->clock = clock; 290 291 return 0; 292 } 293 294 static int rk3399_emmc_get_phy(struct udevice *dev) 295 { 296 struct rockchip_sdhc *priv = dev_get_priv(dev); 297 298 #if CONFIG_IS_ENABLED(OF_PLATDATA) 299 priv->phy = (struct rockchip_emmc_phy *)0xff77f780; 300 #else 301 ofnode phy_node; 302 void *grf_base; 303 u32 grf_phy_offset, phandle; 304 305 phandle = dev_read_u32_default(dev, "phys", 0); 306 phy_node = ofnode_get_by_phandle(phandle); 307 if (!ofnode_valid(phy_node)) { 308 debug("Not found emmc phy device\n"); 309 return -ENODEV; 310 } 311 312 grf_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 313 if (IS_ERR(grf_base)) 314 printf("%s Get syscon grf failed", __func__); 315 grf_phy_offset = ofnode_read_u32_default(phy_node, "reg", 0); 316 317 priv->phy = (struct rockchip_emmc_phy *)(grf_base + grf_phy_offset); 318 #endif 319 return 0; 320 } 321 322 static int rk3399_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clock) 323 { 324 struct rockchip_sdhc *priv = 325 container_of(host, struct rockchip_sdhc, host); 326 int cycle_phy = host->clock != clock && 327 clock > EMMC_MIN_FREQ; 328 329 if (cycle_phy) 330 rk3399_emmc_phy_power_off(priv->phy); 331 332 rockchip_emmc_set_clock(host, clock); 333 334 if (cycle_phy) 335 rk3399_emmc_phy_power_on(priv->phy, clock); 336 337 return 0; 338 } 339 340 static int dwcmshc_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clock) 341 { 342 struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host); 343 struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev); 344 u32 txclk_tapnum, extra; 345 int timeout = 500, ret; 346 347 ret = rockchip_emmc_set_clock(host, clock); 348 349 if (clock >= 100 * MHz) { 350 /* reset DLL */ 351 sdhci_writel(host, DWCMSHC_EMMC_DLL_CTRL_RESET, DWCMSHC_EMMC_DLL_CTRL); 352 udelay(1); 353 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL); 354 355 extra = 0x1 << 16 | /* tune clock stop en */ 356 0x2 << 17 | /* pre-change delay */ 357 0x3 << 19; /* post-change delay */ 358 sdhci_writel(host, extra, DWCMSHC_EMMC_ATCTRL); 359 360 /* Init DLL settings */ 361 extra = DWCMSHC_EMMC_DLL_START_DEFAULT << DWCMSHC_EMMC_DLL_START_POINT | 362 DWCMSHC_EMMC_DLL_INC_VALUE << DWCMSHC_EMMC_DLL_INC | 363 DWCMSHC_EMMC_DLL_START; 364 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL); 365 366 while (1) { 367 if (timeout < 0) 368 return -ETIMEDOUT; 369 if (DLL_LOCK_WO_TMOUT((sdhci_readl(host, DWCMSHC_EMMC_DLL_STATUS0)))) 370 break; 371 udelay(1); 372 timeout--; 373 } 374 extra = DWCMSHC_EMMC_DLL_DLYENA | DLL_RXCLK_ORI_GATE; 375 if (data->flags & RK_RXCLK_NO_INVERTER) 376 extra |= DLL_RXCLK_NO_INVERTER; 377 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK); 378 379 txclk_tapnum = data->hs200_tx_tap; 380 if ((data->flags & RK_DLL_CMD_OUT) && 381 (host->mmc->timing == MMC_TIMING_MMC_HS400 || 382 host->mmc->timing == MMC_TIMING_MMC_HS400ES)) { 383 txclk_tapnum = data->hs400_tx_tap; 384 385 extra = DLL_CMDOUT_SRC_CLK_NEG | 386 DLL_CMDOUT_BOTH_CLK_EDGE | 387 DWCMSHC_EMMC_DLL_DLYENA | 388 data->hs400_cmd_tap | 389 DLL_CMDOUT_TAPNUM_FROM_SW; 390 sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT); 391 } 392 393 extra = DWCMSHC_EMMC_DLL_DLYENA | 394 DLL_TXCLK_TAPNUM_FROM_SW | 395 DLL_TXCLK_NO_INVERTER| 396 txclk_tapnum; 397 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK); 398 399 extra = DWCMSHC_EMMC_DLL_DLYENA | 400 data->hs400_strbin_tap | 401 DLL_STRBIN_TAPNUM_FROM_SW; 402 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN); 403 } else { 404 /* Disable cmd conflict check */ 405 extra = sdhci_readl(host, DWCMSHC_HOST_CTRL3); 406 extra &= ~BIT(0); 407 sdhci_writel(host, extra, DWCMSHC_HOST_CTRL3); 408 409 /* reset the clock phase when the frequency is lower than 100MHz */ 410 sdhci_writel(host, DWCMSHC_EMMC_DLL_BYPASS | DWCMSHC_EMMC_DLL_START, DWCMSHC_EMMC_DLL_CTRL); 411 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_RXCLK); 412 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK); 413 sdhci_writel(host, 0, DECMSHC_EMMC_DLL_CMDOUT); 414 /* 415 * Before switching to hs400es mode, the driver will enable 416 * enhanced strobe first. PHY needs to configure the parameters 417 * of enhanced strobe first. 418 */ 419 extra = DWCMSHC_EMMC_DLL_DLYENA | 420 DLL_STRBIN_DELAY_NUM_SEL | 421 data->ddr50_strbin_delay_num << DLL_STRBIN_DELAY_NUM_OFFSET; 422 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN); 423 } 424 425 return ret; 426 } 427 428 static int dwcmshc_sdhci_set_enhanced_strobe(struct sdhci_host *host) 429 { 430 struct mmc *mmc = host->mmc; 431 u32 vendor; 432 433 vendor = sdhci_readl(host, DWCMSHC_EMMC_CONTROL); 434 if (mmc->timing == MMC_TIMING_MMC_HS400ES) 435 vendor |= DWCMSHC_ENHANCED_STROBE; 436 else 437 vendor &= ~DWCMSHC_ENHANCED_STROBE; 438 sdhci_writel(host, vendor, DWCMSHC_EMMC_CONTROL); 439 440 return 0; 441 } 442 443 static void dwcmshc_sdhci_set_ios_post(struct sdhci_host *host) 444 { 445 u16 ctrl; 446 u32 timing = host->mmc->timing; 447 448 if (timing == MMC_TIMING_MMC_HS400 || timing == MMC_TIMING_MMC_HS400ES) { 449 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 450 ctrl &= ~SDHCI_CTRL_UHS_MASK; 451 ctrl |= DWCMSHC_CTRL_HS400; 452 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); 453 454 /* set CARD_IS_EMMC bit to enable Data Strobe for HS400 */ 455 ctrl = sdhci_readw(host, DWCMSHC_EMMC_CONTROL); 456 ctrl |= DWCMSHC_CARD_IS_EMMC; 457 sdhci_writew(host, ctrl, DWCMSHC_EMMC_CONTROL); 458 } 459 } 460 461 static int dwcmshc_emmc_get_phy(struct udevice *dev) 462 { 463 return 0; 464 } 465 466 static int rockchip_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 467 { 468 struct rockchip_sdhc *priv = 469 container_of(host, struct rockchip_sdhc, host); 470 struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev); 471 if (!data) 472 return -EINVAL; 473 474 return data->emmc_set_clock(host, clock); 475 } 476 477 static void rockchip_sdhci_set_ios_post(struct sdhci_host *host) 478 { 479 struct rockchip_sdhc *priv = 480 container_of(host, struct rockchip_sdhc, host); 481 struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev); 482 483 if (data && data->set_ios_post) 484 data->set_ios_post(host); 485 } 486 487 static int rockchip_sdhci_set_enhanced_strobe(struct sdhci_host *host) 488 { 489 struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host); 490 struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev); 491 492 if (data->set_enhanced_strobe) 493 return data->set_enhanced_strobe(host); 494 495 return -ENOTSUPP; 496 } 497 498 static struct sdhci_ops rockchip_sdhci_ops = { 499 .set_clock = rockchip_sdhci_set_clock, 500 .set_ios_post = rockchip_sdhci_set_ios_post, 501 .set_enhanced_strobe = rockchip_sdhci_set_enhanced_strobe, 502 }; 503 504 static int rockchip_sdhci_probe(struct udevice *dev) 505 { 506 struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(dev); 507 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 508 struct rockchip_sdhc_plat *plat = dev_get_platdata(dev); 509 struct rockchip_sdhc *prv = dev_get_priv(dev); 510 struct sdhci_host *host = &prv->host; 511 int max_frequency, ret; 512 struct clk clk; 513 514 #if CONFIG_IS_ENABLED(OF_PLATDATA) 515 struct dtd_rockchip_rk3399_sdhci_5_1 *dtplat = &plat->dtplat; 516 517 host->name = dev->name; 518 host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]); 519 host->host_caps |= MMC_MODE_8BIT; 520 max_frequency = dtplat->max_frequency; 521 ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &clk); 522 #else 523 max_frequency = dev_read_u32_default(dev, "max-frequency", 0); 524 switch (dev_read_u32_default(dev, "bus-width", 4)) { 525 case 8: 526 host->host_caps |= MMC_MODE_8BIT; 527 break; 528 case 4: 529 host->host_caps |= MMC_MODE_4BIT; 530 break; 531 case 1: 532 break; 533 default: 534 printf("Invalid \"bus-width\" value\n"); 535 return -EINVAL; 536 } 537 ret = clk_get_by_index(dev, 0, &clk); 538 #endif 539 if (!ret) { 540 ret = clk_set_rate(&clk, max_frequency); 541 if (IS_ERR_VALUE(ret)) 542 printf("%s clk set rate fail!\n", __func__); 543 } else { 544 printf("%s fail to get clk\n", __func__); 545 } 546 547 prv->emmc_clk = clk; 548 prv->dev = dev; 549 ret = data->get_phy(dev); 550 if (ret) 551 return ret; 552 553 host->ops = &rockchip_sdhci_ops; 554 555 host->max_clk = max_frequency; 556 557 if (dev_read_bool(dev, "mmc-hs200-1_8v")) 558 host->host_caps |= MMC_MODE_HS200; 559 else if (dev_read_bool(dev, "mmc-hs400-1_8v")) 560 host->host_caps |= MMC_MODE_HS400; 561 562 if (data->set_enhanced_strobe && dev_read_bool(dev, "mmc-hs400-enhanced-strobe")) 563 host->host_caps |= MMC_MODE_HS400ES; 564 565 ret = sdhci_setup_cfg(&plat->cfg, host, 0, EMMC_MIN_FREQ); 566 567 host->mmc = &plat->mmc; 568 if (ret) 569 return ret; 570 host->mmc->priv = &prv->host; 571 host->mmc->dev = dev; 572 upriv->mmc = host->mmc; 573 574 return sdhci_probe(dev); 575 } 576 577 static int rockchip_sdhci_of_to_plat(struct udevice *dev) 578 { 579 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 580 struct sdhci_host *host = dev_get_priv(dev); 581 582 host->name = dev->name; 583 host->ioaddr = dev_read_addr_ptr(dev); 584 #endif 585 586 return 0; 587 } 588 589 static int rockchip_sdhci_bind(struct udevice *dev) 590 { 591 struct rockchip_sdhc_plat *plat = dev_get_platdata(dev); 592 593 return sdhci_bind(dev, &plat->mmc, &plat->cfg); 594 } 595 596 static const struct sdhci_data arasan_data = { 597 .emmc_set_clock = rk3399_sdhci_emmc_set_clock, 598 .get_phy = rk3399_emmc_get_phy, 599 }; 600 601 static const struct sdhci_data rk3568_data = { 602 .emmc_set_clock = dwcmshc_sdhci_emmc_set_clock, 603 .get_phy = dwcmshc_emmc_get_phy, 604 .flags = RK_RXCLK_NO_INVERTER, 605 .hs200_tx_tap = 16, 606 .hs400_tx_tap = 8, 607 .hs400_cmd_tap = 8, 608 .hs400_strbin_tap = 3, 609 .ddr50_strbin_delay_num = 16, 610 }; 611 612 static const struct sdhci_data rk3588_data = { 613 .emmc_set_clock = dwcmshc_sdhci_emmc_set_clock, 614 .get_phy = dwcmshc_emmc_get_phy, 615 .set_ios_post = dwcmshc_sdhci_set_ios_post, 616 .set_enhanced_strobe = dwcmshc_sdhci_set_enhanced_strobe, 617 .flags = RK_DLL_CMD_OUT, 618 .hs200_tx_tap = 16, 619 .hs400_tx_tap = 9, 620 .hs400_cmd_tap = 8, 621 .hs400_strbin_tap = 3, 622 .ddr50_strbin_delay_num = 16, 623 }; 624 625 static const struct sdhci_data rk3528_data = { 626 .emmc_set_clock = dwcmshc_sdhci_emmc_set_clock, 627 .get_phy = dwcmshc_emmc_get_phy, 628 .set_ios_post = dwcmshc_sdhci_set_ios_post, 629 .set_enhanced_strobe = dwcmshc_sdhci_set_enhanced_strobe, 630 .flags = RK_DLL_CMD_OUT | RK_RXCLK_NO_INVERTER, 631 .hs200_tx_tap = 12, 632 .hs400_tx_tap = 4, 633 .hs400_cmd_tap = 4, 634 .hs400_strbin_tap = 3, 635 .ddr50_strbin_delay_num = 10, 636 }; 637 638 static const struct udevice_id sdhci_ids[] = { 639 { 640 .compatible = "arasan,sdhci-5.1", 641 .data = (ulong)&arasan_data, 642 }, 643 { 644 .compatible = "snps,dwcmshc-sdhci", 645 .data = (ulong)&rk3568_data, 646 }, 647 { 648 .compatible = "rockchip,rk3528-dwcmshc", 649 .data = (ulong)&rk3528_data, 650 }, 651 { 652 .compatible = "rockchip,rk3588-dwcmshc", 653 .data = (ulong)&rk3588_data, 654 }, 655 { } 656 }; 657 658 U_BOOT_DRIVER(arasan_sdhci_drv) = { 659 .name = "rockchip_sdhci_5_1", 660 .id = UCLASS_MMC, 661 .of_match = sdhci_ids, 662 .ofdata_to_platdata = rockchip_sdhci_of_to_plat, 663 .ops = &sdhci_ops, 664 .bind = rockchip_sdhci_bind, 665 .probe = rockchip_sdhci_probe, 666 .priv_auto_alloc_size = sizeof(struct rockchip_sdhc), 667 .platdata_auto_alloc_size = sizeof(struct rockchip_sdhc_plat), 668 }; 669