1 /* 2 * (C) Copyright 2016 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * Rockchip SD Host Controller Interface 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <asm/arch/hardware.h> 10 #include <common.h> 11 #include <dm.h> 12 #include <dt-structs.h> 13 #include <linux/libfdt.h> 14 #include <malloc.h> 15 #include <mapmem.h> 16 #include <sdhci.h> 17 #include <clk.h> 18 #include <syscon.h> 19 #include <dm/ofnode.h> 20 #include <asm/arch/clock.h> 21 22 DECLARE_GLOBAL_DATA_PTR; 23 /* 400KHz is max freq for card ID etc. Use that as min */ 24 #define EMMC_MIN_FREQ 400000 25 #define KHz (1000) 26 #define MHz (1000 * KHz) 27 28 #define PHYCTRL_CALDONE_MASK 0x1 29 #define PHYCTRL_CALDONE_SHIFT 0x6 30 #define PHYCTRL_CALDONE_DONE 0x1 31 #define PHYCTRL_DLLRDY_MASK 0x1 32 #define PHYCTRL_DLLRDY_SHIFT 0x5 33 #define PHYCTRL_DLLRDY_DONE 0x1 34 #define PHYCTRL_FREQSEL_200M 0x0 35 #define PHYCTRL_FREQSEL_50M 0x1 36 #define PHYCTRL_FREQSEL_100M 0x2 37 #define PHYCTRL_FREQSEL_150M 0x3 38 39 /* Rockchip specific Registers */ 40 #define DWCMSHC_EMMC_DLL_CTRL 0x800 41 #define DWCMSHC_EMMC_DLL_RXCLK 0x804 42 #define DWCMSHC_EMMC_DLL_TXCLK 0x808 43 #define DWCMSHC_EMMC_DLL_STRBIN 0x80c 44 #define DWCMSHC_EMMC_DLL_STATUS0 0x840 45 #define DWCMSHC_EMMC_DLL_STATUS1 0x844 46 #define DWCMSHC_EMMC_DLL_START BIT(0) 47 #define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL 29 48 #define DWCMSHC_EMMC_DLL_START_POINT 16 49 #define DWCMSHC_EMMC_DLL_INC 8 50 #define DWCMSHC_EMMC_DLL_DLYENA BIT(27) 51 #define DLL_TXCLK_TAPNUM_DEFAULT 0x10 52 #define DLL_STRBIN_TAPNUM_DEFAULT 0x3 53 #define DLL_TXCLK_TAPNUM_FROM_SW BIT(24) 54 #define DWCMSHC_EMMC_DLL_LOCKED BIT(8) 55 #define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9) 56 #define DLL_RXCLK_NO_INVERTER 1 57 #define DLL_RXCLK_INVERTER 0 58 #define DWCMSHC_ENHANCED_STROBE BIT(8) 59 #define DLL_LOCK_WO_TMOUT(x) \ 60 ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \ 61 (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0)) 62 #define ROCKCHIP_MAX_CLKS 3 63 64 struct rockchip_sdhc_plat { 65 #if CONFIG_IS_ENABLED(OF_PLATDATA) 66 struct dtd_rockchip_rk3399_sdhci_5_1 dtplat; 67 #endif 68 struct mmc_config cfg; 69 struct mmc mmc; 70 }; 71 72 struct rockchip_emmc_phy { 73 u32 emmcphy_con[7]; 74 u32 reserved; 75 u32 emmcphy_status; 76 }; 77 78 struct rockchip_sdhc { 79 struct sdhci_host host; 80 struct udevice *dev; 81 void *base; 82 struct rockchip_emmc_phy *phy; 83 struct clk emmc_clk; 84 }; 85 86 struct sdhci_data { 87 int (*emmc_set_clock)(struct sdhci_host *host, unsigned int clock); 88 int (*emmc_phy_init)(struct udevice *dev); 89 int (*get_phy)(struct udevice *dev); 90 }; 91 92 static int rk3399_emmc_phy_init(struct udevice *dev) 93 { 94 return 0; 95 } 96 97 static void rk3399_emmc_phy_power_on(struct rockchip_emmc_phy *phy, u32 clock) 98 { 99 u32 caldone, dllrdy, freqsel; 100 uint start; 101 102 writel(RK_CLRSETBITS(7 << 4, 0), &phy->emmcphy_con[6]); 103 writel(RK_CLRSETBITS(1 << 11, 1 << 11), &phy->emmcphy_con[0]); 104 writel(RK_CLRSETBITS(0xf << 7, 6 << 7), &phy->emmcphy_con[0]); 105 106 /* 107 * According to the user manual, calpad calibration 108 * cycle takes more than 2us without the minimal recommended 109 * value, so we may need a little margin here 110 */ 111 udelay(3); 112 writel(RK_CLRSETBITS(1, 1), &phy->emmcphy_con[6]); 113 114 /* 115 * According to the user manual, it asks driver to 116 * wait 5us for calpad busy trimming. But it seems that 117 * 5us of caldone isn't enough for all cases. 118 */ 119 udelay(500); 120 caldone = readl(&phy->emmcphy_status); 121 caldone = (caldone >> PHYCTRL_CALDONE_SHIFT) & PHYCTRL_CALDONE_MASK; 122 if (caldone != PHYCTRL_CALDONE_DONE) { 123 printf("%s: caldone timeout.\n", __func__); 124 return; 125 } 126 127 /* Set the frequency of the DLL operation */ 128 if (clock < 75 * MHz) 129 freqsel = PHYCTRL_FREQSEL_50M; 130 else if (clock < 125 * MHz) 131 freqsel = PHYCTRL_FREQSEL_100M; 132 else if (clock < 175 * MHz) 133 freqsel = PHYCTRL_FREQSEL_150M; 134 else 135 freqsel = PHYCTRL_FREQSEL_200M; 136 137 /* Set the frequency of the DLL operation */ 138 writel(RK_CLRSETBITS(3 << 12, freqsel << 12), &phy->emmcphy_con[0]); 139 writel(RK_CLRSETBITS(1 << 1, 1 << 1), &phy->emmcphy_con[6]); 140 141 start = get_timer(0); 142 143 do { 144 udelay(1); 145 dllrdy = readl(&phy->emmcphy_status); 146 dllrdy = (dllrdy >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK; 147 if (dllrdy == PHYCTRL_DLLRDY_DONE) 148 break; 149 } while (get_timer(start) < 50000); 150 151 if (dllrdy != PHYCTRL_DLLRDY_DONE) 152 printf("%s: dllrdy timeout.\n", __func__); 153 } 154 155 static void rk3399_emmc_phy_power_off(struct rockchip_emmc_phy *phy) 156 { 157 writel(RK_CLRSETBITS(1, 0), &phy->emmcphy_con[6]); 158 writel(RK_CLRSETBITS(1 << 1, 0), &phy->emmcphy_con[6]); 159 } 160 161 static int rk3399_emmc_set_clock(struct sdhci_host *host, unsigned int clock) 162 { 163 unsigned int div, clk = 0, timeout; 164 unsigned int input_clk; 165 struct rockchip_sdhc *priv = 166 container_of(host, struct rockchip_sdhc, host); 167 168 /* Wait max 20 ms */ 169 timeout = 200; 170 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & 171 (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) { 172 if (timeout == 0) { 173 printf("%s: Timeout to wait cmd & data inhibit\n", 174 __func__); 175 return -EBUSY; 176 } 177 178 timeout--; 179 udelay(100); 180 } 181 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 182 183 if (clock == 0) 184 return 0; 185 186 input_clk = clk_set_rate(&priv->emmc_clk, clock); 187 if (IS_ERR_VALUE(input_clk)) 188 input_clk = host->max_clk; 189 190 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { 191 /* 192 * Check if the Host Controller supports Programmable Clock 193 * Mode. 194 */ 195 if (host->clk_mul) { 196 for (div = 1; div <= 1024; div++) { 197 if ((input_clk / div) <= clock) 198 break; 199 } 200 201 /* 202 * Set Programmable Clock Mode in the Clock 203 * Control register. 204 */ 205 clk = SDHCI_PROG_CLOCK_MODE; 206 div--; 207 } else { 208 /* Version 3.00 divisors must be a multiple of 2. */ 209 if (input_clk <= clock) { 210 div = 1; 211 } else { 212 for (div = 2; 213 div < SDHCI_MAX_DIV_SPEC_300; 214 div += 2) { 215 if ((input_clk / div) <= clock) 216 break; 217 } 218 } 219 div >>= 1; 220 } 221 } else { 222 /* Version 2.00 divisors must be a power of 2. */ 223 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { 224 if ((input_clk / div) <= clock) 225 break; 226 } 227 div >>= 1; 228 } 229 230 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; 231 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) 232 << SDHCI_DIVIDER_HI_SHIFT; 233 clk |= SDHCI_CLOCK_INT_EN; 234 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 235 236 /* Wait max 20 ms */ 237 timeout = 20; 238 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) 239 & SDHCI_CLOCK_INT_STABLE)) { 240 if (timeout == 0) { 241 printf("%s: Internal clock never stabilised.\n", 242 __func__); 243 return -EBUSY; 244 } 245 timeout--; 246 udelay(1000); 247 } 248 clk |= SDHCI_CLOCK_CARD_EN; 249 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 250 host->clock = clock; 251 252 return 0; 253 } 254 255 static int rk3399_emmc_get_phy(struct udevice *dev) 256 { 257 struct rockchip_sdhc *priv = dev_get_priv(dev); 258 259 #if CONFIG_IS_ENABLED(OF_PLATDATA) 260 priv->phy = (struct rockchip_emmc_phy *)0xff77f780; 261 #else 262 ofnode phy_node; 263 void *grf_base; 264 u32 grf_phy_offset, phandle; 265 266 phandle = dev_read_u32_default(dev, "phys", 0); 267 phy_node = ofnode_get_by_phandle(phandle); 268 if (!ofnode_valid(phy_node)) { 269 debug("Not found emmc phy device\n"); 270 return -ENODEV; 271 } 272 273 grf_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 274 if (grf_base < 0) 275 printf("%s Get syscon grf failed", __func__); 276 grf_phy_offset = ofnode_read_u32_default(phy_node, "reg", 0); 277 278 priv->phy = (struct rockchip_emmc_phy *)(grf_base + grf_phy_offset); 279 #endif 280 return 0; 281 } 282 283 static int rk3399_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clock) 284 { 285 struct rockchip_sdhc *priv = 286 container_of(host, struct rockchip_sdhc, host); 287 int cycle_phy = host->clock != clock && 288 clock > EMMC_MIN_FREQ; 289 290 if (cycle_phy) 291 rk3399_emmc_phy_power_off(priv->phy); 292 293 rk3399_emmc_set_clock(host, clock); 294 295 if (cycle_phy) 296 rk3399_emmc_phy_power_on(priv->phy, clock); 297 298 return 0; 299 } 300 301 static int rk3568_emmc_phy_init(struct udevice *dev) 302 { 303 struct rockchip_sdhc *prv = dev_get_priv(dev); 304 struct sdhci_host *host = &prv->host; 305 u32 extra; 306 307 extra = DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL; 308 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK); 309 return 0; 310 } 311 312 static int rk3568_sdhci_emmc_set_clock(struct sdhci_host *host, unsigned int clock) 313 { 314 u32 extra; 315 int timeout = 500, ret; 316 317 ret = rk3399_emmc_set_clock(host, clock); 318 319 if (clock >= 50 * 1000000) { 320 sdhci_writel(host, BIT(1), DWCMSHC_EMMC_DLL_CTRL); 321 udelay(1); 322 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL); 323 /* Init DLL settings */ 324 extra = 0x5 << DWCMSHC_EMMC_DLL_START_POINT | 325 0x2 << DWCMSHC_EMMC_DLL_INC | 326 DWCMSHC_EMMC_DLL_START; 327 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL); 328 329 while (1) { 330 if (timeout < 0) 331 return -ETIMEDOUT; 332 if (DLL_LOCK_WO_TMOUT((sdhci_readl(host, DWCMSHC_EMMC_DLL_STATUS0)))) 333 break; 334 udelay(1); 335 timeout--; 336 } 337 338 extra = DWCMSHC_EMMC_DLL_DLYENA | 339 DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL; 340 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK); 341 342 extra = DWCMSHC_EMMC_DLL_DLYENA | 343 DLL_TXCLK_TAPNUM_DEFAULT | 344 DLL_TXCLK_TAPNUM_FROM_SW; 345 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK); 346 347 extra = DWCMSHC_EMMC_DLL_DLYENA | 348 DLL_STRBIN_TAPNUM_DEFAULT; 349 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN); 350 udelay(1); 351 } else { 352 /* reset the clock phase when the frequency is lower than 52MHz */ 353 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL); 354 extra = DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL; 355 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK); 356 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK); 357 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN); 358 udelay(1); 359 } 360 361 return ret; 362 } 363 364 static int rk3568_emmc_get_phy(struct udevice *dev) 365 { 366 return 0; 367 } 368 369 static int arasan_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) 370 { 371 struct rockchip_sdhc *priv = 372 container_of(host, struct rockchip_sdhc, host); 373 struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev); 374 if (!data) 375 return -EINVAL; 376 377 return data->emmc_set_clock(host, clock); 378 } 379 380 static struct sdhci_ops arasan_sdhci_ops = { 381 .set_clock = arasan_sdhci_set_clock, 382 }; 383 384 static int arasan_sdhci_probe(struct udevice *dev) 385 { 386 struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(dev); 387 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 388 struct rockchip_sdhc_plat *plat = dev_get_platdata(dev); 389 struct rockchip_sdhc *prv = dev_get_priv(dev); 390 struct sdhci_host *host = &prv->host; 391 int max_frequency, ret; 392 struct clk clk; 393 394 #if CONFIG_IS_ENABLED(OF_PLATDATA) 395 struct dtd_rockchip_rk3399_sdhci_5_1 *dtplat = &plat->dtplat; 396 397 host->name = dev->name; 398 host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]); 399 host->host_caps |= MMC_MODE_8BIT; 400 max_frequency = dtplat->max_frequency; 401 ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &clk); 402 #else 403 max_frequency = dev_read_u32_default(dev, "max-frequency", 0); 404 switch (dev_read_u32_default(dev, "bus-width", 4)) { 405 case 8: 406 host->host_caps |= MMC_MODE_8BIT; 407 break; 408 case 4: 409 host->host_caps |= MMC_MODE_4BIT; 410 break; 411 case 1: 412 break; 413 default: 414 printf("Invalid \"bus-width\" value\n"); 415 return -EINVAL; 416 } 417 ret = clk_get_by_index(dev, 0, &clk); 418 #endif 419 if (!ret) { 420 ret = clk_set_rate(&clk, max_frequency); 421 if (IS_ERR_VALUE(ret)) 422 printf("%s clk set rate fail!\n", __func__); 423 } else { 424 printf("%s fail to get clk\n", __func__); 425 } 426 427 prv->emmc_clk = clk; 428 prv->dev = dev; 429 ret = data->get_phy(dev); 430 if (ret) 431 return ret; 432 433 ret = data->emmc_phy_init(dev); 434 if (ret) 435 return ret; 436 437 host->ops = &arasan_sdhci_ops; 438 439 host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD; 440 host->max_clk = max_frequency; 441 442 if (dev_read_bool(dev, "mmc-hs200-1_8v")) 443 host->host_caps |= MMC_MODE_HS200; 444 else if (dev_read_bool(dev, "mmc-hs400-1_8v")) 445 host->host_caps |= MMC_MODE_HS400; 446 ret = sdhci_setup_cfg(&plat->cfg, host, 0, EMMC_MIN_FREQ); 447 448 host->mmc = &plat->mmc; 449 if (ret) 450 return ret; 451 host->mmc->priv = &prv->host; 452 host->mmc->dev = dev; 453 upriv->mmc = host->mmc; 454 455 return sdhci_probe(dev); 456 } 457 458 static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev) 459 { 460 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 461 struct sdhci_host *host = dev_get_priv(dev); 462 463 host->name = dev->name; 464 host->ioaddr = dev_read_addr_ptr(dev); 465 #endif 466 467 return 0; 468 } 469 470 static int rockchip_sdhci_bind(struct udevice *dev) 471 { 472 struct rockchip_sdhc_plat *plat = dev_get_platdata(dev); 473 474 return sdhci_bind(dev, &plat->mmc, &plat->cfg); 475 } 476 477 static const struct sdhci_data arasan_data = { 478 .emmc_set_clock = rk3399_sdhci_emmc_set_clock, 479 .get_phy = rk3399_emmc_get_phy, 480 .emmc_phy_init = rk3399_emmc_phy_init, 481 }; 482 483 static const struct sdhci_data snps_data = { 484 .emmc_set_clock = rk3568_sdhci_emmc_set_clock, 485 .get_phy = rk3568_emmc_get_phy, 486 .emmc_phy_init = rk3568_emmc_phy_init, 487 }; 488 489 static const struct udevice_id arasan_sdhci_ids[] = { 490 { 491 .compatible = "arasan,sdhci-5.1", 492 .data = (ulong)&arasan_data, 493 }, 494 { 495 .compatible = "snps,dwcmshc-sdhci", 496 .data = (ulong)&snps_data, 497 }, 498 { } 499 }; 500 501 U_BOOT_DRIVER(arasan_sdhci_drv) = { 502 .name = "rockchip_rk3399_sdhci_5_1", 503 .id = UCLASS_MMC, 504 .of_match = arasan_sdhci_ids, 505 .ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata, 506 .ops = &sdhci_ops, 507 .bind = rockchip_sdhci_bind, 508 .probe = arasan_sdhci_probe, 509 .priv_auto_alloc_size = sizeof(struct rockchip_sdhc), 510 .platdata_auto_alloc_size = sizeof(struct rockchip_sdhc_plat), 511 }; 512