1 /* 2 * (C) Copyright 2012 SAMSUNG Electronics 3 * Jaehoon Chung <jh80.chung@samsung.com> 4 * Rajeshawari Shinde <rajeshwari.s@samsung.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <bouncebuf.h> 11 #include <div64.h> 12 #include <errno.h> 13 #include <malloc.h> 14 #include <memalign.h> 15 #include <mmc.h> 16 #include <dwmmc.h> 17 #include <dm/pinctrl.h> 18 #include <dm.h> 19 #ifdef CONFIG_DM_GPIO 20 #include <asm/gpio.h> 21 #include <asm-generic/gpio.h> 22 #endif 23 24 #define PAGE_SIZE 4096 25 #define MSEC_PER_SEC 1000ULL 26 27 /* 28 * Currently it supports read/write up to 8*8*4 Bytes per 29 * stride as a burst mode. Please note that if you change 30 * MAX_STRIDE, you should also update dwmci_memcpy_fromio 31 * to augment the groups of {ldm, stm}. 32 */ 33 #define MAX_STRIDE 64 34 #if (CONFIG_ARM && CONFIG_CPU_V7 && !defined(CONFIG_MMC_SIMPLE)) 35 void noinline dwmci_memcpy_fromio(void *buffer, void *fifo_addr) 36 { 37 __asm__ __volatile__ ( 38 "push {r2, r3, r4, r5, r6, r7, r8, r9}\n" 39 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 40 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 41 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 42 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 43 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 44 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 45 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 46 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 47 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 48 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 49 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 50 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 51 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 52 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 53 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 54 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 55 "pop {r2, r3, r4, r5, r6,r7,r8,r9}\n" 56 :::"memory" 57 ); 58 } 59 60 void noinline dwmci_memcpy_toio(void *buffer, void *fifo_addr) 61 { 62 __asm__ __volatile__ ( 63 "push {r2, r3, r4, r5, r6, r7, r8, r9}\n" 64 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 65 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 66 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 67 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 68 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 69 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 70 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 71 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 72 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 73 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 74 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 75 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 76 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 77 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 78 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 79 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 80 "pop {r2, r3, r4, r5, r6,r7,r8,r9}\n" 81 :::"memory" 82 ); 83 } 84 #else 85 void dwmci_memcpy_fromio(void *buffer, void *fifo_addr) {}; 86 void dwmci_memcpy_toio(void *buffer, void *fifo_addr) {}; 87 #endif 88 89 static int dwmci_wait_reset(struct dwmci_host *host, u32 value) 90 { 91 unsigned long timeout = 1000; 92 u32 ctrl; 93 94 dwmci_writel(host, DWMCI_CTRL, value); 95 96 while (timeout--) { 97 ctrl = dwmci_readl(host, DWMCI_CTRL); 98 if (!(ctrl & DWMCI_RESET_ALL)) 99 return 1; 100 } 101 return 0; 102 } 103 104 static void dwmci_set_idma_desc(struct dwmci_idmac *idmac, 105 u32 desc0, u32 desc1, u32 desc2) 106 { 107 struct dwmci_idmac *desc = idmac; 108 109 desc->flags = desc0; 110 desc->cnt = desc1; 111 desc->addr = desc2; 112 desc->next_addr = (ulong)desc + sizeof(struct dwmci_idmac); 113 } 114 115 static void dwmci_prepare_data(struct dwmci_host *host, 116 struct mmc_data *data, 117 struct dwmci_idmac *cur_idmac, 118 void *bounce_buffer) 119 { 120 unsigned long ctrl; 121 unsigned int i = 0, flags, cnt, blk_cnt; 122 ulong data_start, data_end; 123 124 125 blk_cnt = data->blocks; 126 127 dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET); 128 129 data_start = (ulong)cur_idmac; 130 dwmci_writel(host, DWMCI_DBADDR, (ulong)cur_idmac); 131 132 do { 133 flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ; 134 flags |= (i == 0) ? DWMCI_IDMAC_FS : 0; 135 if (blk_cnt <= 8) { 136 flags |= DWMCI_IDMAC_LD; 137 cnt = data->blocksize * blk_cnt; 138 } else 139 cnt = data->blocksize * 8; 140 141 dwmci_set_idma_desc(cur_idmac, flags, cnt, 142 (ulong)bounce_buffer + (i * PAGE_SIZE)); 143 144 if (blk_cnt <= 8) 145 break; 146 blk_cnt -= 8; 147 cur_idmac++; 148 i++; 149 } while(1); 150 151 data_end = (ulong)cur_idmac; 152 flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN); 153 154 ctrl = dwmci_readl(host, DWMCI_CTRL); 155 ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN; 156 dwmci_writel(host, DWMCI_CTRL, ctrl); 157 158 ctrl = dwmci_readl(host, DWMCI_BMOD); 159 ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN; 160 dwmci_writel(host, DWMCI_BMOD, ctrl); 161 162 dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize); 163 dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks); 164 } 165 166 #ifdef CONFIG_SPL_BUILD 167 static unsigned int dwmci_get_drto(struct dwmci_host *host, 168 const unsigned int size) 169 { 170 unsigned int drto_clks; 171 unsigned int drto_div; 172 unsigned int drto_ms; 173 174 drto_clks = dwmci_readl(host, DWMCI_TMOUT) >> 8; 175 drto_div = (dwmci_readl(host, DWMCI_CLKDIV) & 0xff) * 2; 176 if (drto_div == 0) 177 drto_div = 1; 178 179 drto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * drto_clks * drto_div, 180 host->mmc->clock); 181 182 /* add a bit spare time */ 183 drto_ms += 10; 184 185 return drto_ms; 186 } 187 #else 188 static unsigned int dwmci_get_drto(struct dwmci_host *host, 189 const unsigned int size) 190 { 191 unsigned int timeout; 192 193 timeout = size * 8; /* counting in bits */ 194 timeout *= 10; /* wait 10 times as long */ 195 timeout /= host->mmc->clock; 196 timeout /= host->mmc->bus_width; 197 timeout *= 1000; /* counting in msec */ 198 timeout = (timeout < 10000) ? 10000 : timeout; 199 200 return timeout; 201 } 202 #endif 203 204 static unsigned int dwmci_get_cto(struct dwmci_host *host) 205 { 206 unsigned int cto_clks; 207 unsigned int cto_div; 208 unsigned int cto_ms; 209 210 cto_clks = dwmci_readl(host, DWMCI_TMOUT) & 0xff; 211 cto_div = (dwmci_readl(host, DWMCI_CLKDIV) & 0xff) * 2; 212 if (cto_div == 0) 213 cto_div = 1; 214 215 cto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * cto_clks * cto_div, 216 host->mmc->clock); 217 218 /* add a bit spare time */ 219 cto_ms += 10; 220 221 return cto_ms; 222 } 223 224 static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data) 225 { 226 int ret = 0; 227 int reset_timeout = 100; 228 u32 timeout, status, ctrl, mask, size, i, len = 0; 229 u32 *buf = NULL; 230 ulong start = get_timer(0); 231 u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >> 232 RX_WMARK_SHIFT) + 1) * 2; 233 bool stride; 234 235 size = data->blocksize * data->blocks; 236 /* Still use legacy PIO mode if size < 512(128 * 4) Bytes */ 237 stride = host->stride_pio && size > 128; 238 if (data->flags == MMC_DATA_READ) 239 buf = (unsigned int *)data->dest; 240 else 241 buf = (unsigned int *)data->src; 242 243 timeout = dwmci_get_drto(host, size); 244 size /= 4; 245 246 for (;;) { 247 mask = dwmci_readl(host, DWMCI_RINTSTS); 248 /* Error during data transfer. */ 249 if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) { 250 debug("%s: DATA ERROR!\n", __func__); 251 dwmci_wait_reset(host, DWMCI_RESET_ALL); 252 dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT | 253 DWMCI_CMD_UPD_CLK | DWMCI_CMD_START); 254 255 do { 256 status = dwmci_readl(host, DWMCI_CMD); 257 if (reset_timeout-- < 0) 258 break; 259 udelay(100); 260 } while (status & DWMCI_CMD_START); 261 262 if (!host->fifo_mode) { 263 ctrl = dwmci_readl(host, DWMCI_BMOD); 264 ctrl |= DWMCI_BMOD_IDMAC_RESET; 265 dwmci_writel(host, DWMCI_BMOD, ctrl); 266 } 267 268 ret = -EINVAL; 269 break; 270 } 271 272 if (host->fifo_mode && size) { 273 len = 0; 274 if (data->flags == MMC_DATA_READ && 275 (mask & DWMCI_INTMSK_RXDR)) { 276 while (size) { 277 len = dwmci_readl(host, DWMCI_STATUS); 278 len = (len >> DWMCI_FIFO_SHIFT) & 279 DWMCI_FIFO_MASK; 280 len = min(size, len); 281 if (!stride) { 282 /* Legacy pio mode */ 283 for (i = 0; i < len; i++) 284 *buf++ = dwmci_readl(host, DWMCI_DATA); 285 goto read_again; 286 } 287 288 /* dwmci_memcpy_fromio now bursts 256 Bytes once */ 289 if (len < MAX_STRIDE) 290 continue; 291 292 for (i = 0; i < len / MAX_STRIDE; i++) { 293 dwmci_memcpy_fromio(buf, host->ioaddr + DWMCI_DATA); 294 buf += MAX_STRIDE; 295 } 296 297 len = i * MAX_STRIDE; 298 read_again: 299 size = size > len ? (size - len) : 0; 300 } 301 dwmci_writel(host, DWMCI_RINTSTS, 302 DWMCI_INTMSK_RXDR); 303 start = get_timer(0); 304 } else if (data->flags == MMC_DATA_WRITE && 305 (mask & DWMCI_INTMSK_TXDR)) { 306 while (size) { 307 len = dwmci_readl(host, DWMCI_STATUS); 308 len = fifo_depth - ((len >> 309 DWMCI_FIFO_SHIFT) & 310 DWMCI_FIFO_MASK); 311 len = min(size, len); 312 if (!stride) { 313 for (i = 0; i < len; i++) 314 dwmci_writel(host, DWMCI_DATA, 315 *buf++); 316 goto write_again; 317 } 318 /* dwmci_memcpy_toio now bursts 256 Bytes once */ 319 if (len < MAX_STRIDE) 320 continue; 321 322 for (i = 0; i < len / MAX_STRIDE; i++) { 323 dwmci_memcpy_toio(buf, host->ioaddr + DWMCI_DATA); 324 buf += MAX_STRIDE; 325 } 326 327 len = i * MAX_STRIDE; 328 write_again: 329 size = size > len ? (size - len) : 0; 330 } 331 dwmci_writel(host, DWMCI_RINTSTS, 332 DWMCI_INTMSK_TXDR); 333 start = get_timer(0); 334 } 335 } 336 337 /* Data arrived correctly. */ 338 if (mask & DWMCI_INTMSK_DTO) { 339 ret = 0; 340 break; 341 } 342 343 /* Check for timeout. */ 344 if (get_timer(start) > timeout) { 345 debug("%s: Timeout waiting for data!\n", 346 __func__); 347 ret = -ETIMEDOUT; 348 break; 349 } 350 } 351 352 dwmci_writel(host, DWMCI_RINTSTS, mask); 353 354 return ret; 355 } 356 357 static int dwmci_set_transfer_mode(struct dwmci_host *host, 358 struct mmc_data *data) 359 { 360 unsigned long mode; 361 362 mode = DWMCI_CMD_DATA_EXP; 363 if (data->flags & MMC_DATA_WRITE) 364 mode |= DWMCI_CMD_RW; 365 366 return mode; 367 } 368 369 #ifdef CONFIG_DM_MMC 370 static int dwmci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, 371 struct mmc_data *data) 372 { 373 struct mmc *mmc = mmc_get_mmc_dev(dev); 374 #else 375 static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 376 struct mmc_data *data) 377 { 378 #endif 379 struct dwmci_host *host = mmc->priv; 380 ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac, 381 data ? DIV_ROUND_UP(data->blocks, 8) : 0); 382 int ret = 0, flags = 0; 383 unsigned int timeout = 500; 384 u32 mask, ctrl; 385 ulong start = get_timer(0); 386 struct bounce_buffer bbstate; 387 388 while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) { 389 if (get_timer(start) > timeout) { 390 debug("%s: Timeout on data busy\n", __func__); 391 return -ETIMEDOUT; 392 } 393 } 394 395 dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL); 396 397 if (data) { 398 if (host->fifo_mode) { 399 dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize); 400 dwmci_writel(host, DWMCI_BYTCNT, 401 data->blocksize * data->blocks); 402 dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET); 403 } else { 404 if (data->flags == MMC_DATA_READ) { 405 ret = bounce_buffer_start(&bbstate, 406 (void*)data->dest, 407 data->blocksize * 408 data->blocks, GEN_BB_WRITE); 409 } else { 410 ret = bounce_buffer_start(&bbstate, 411 (void*)data->src, 412 data->blocksize * 413 data->blocks, GEN_BB_READ); 414 } 415 416 if (ret) 417 return ret; 418 419 dwmci_prepare_data(host, data, cur_idmac, 420 bbstate.bounce_buffer); 421 } 422 } 423 424 dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg); 425 426 if (data) 427 flags = dwmci_set_transfer_mode(host, data); 428 429 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) 430 return -1; 431 432 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 433 flags |= DWMCI_CMD_ABORT_STOP; 434 else 435 flags |= DWMCI_CMD_PRV_DAT_WAIT; 436 437 if (cmd->resp_type & MMC_RSP_PRESENT) { 438 flags |= DWMCI_CMD_RESP_EXP; 439 if (cmd->resp_type & MMC_RSP_136) 440 flags |= DWMCI_CMD_RESP_LENGTH; 441 } 442 443 if (cmd->resp_type & MMC_RSP_CRC) 444 flags |= DWMCI_CMD_CHECK_CRC; 445 446 flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG); 447 448 debug("Sending CMD%d\n",cmd->cmdidx); 449 450 dwmci_writel(host, DWMCI_CMD, flags); 451 452 timeout = dwmci_get_cto(host); 453 start = get_timer(0); 454 do { 455 mask = dwmci_readl(host, DWMCI_RINTSTS); 456 if (mask & DWMCI_INTMSK_CDONE) { 457 if (!data) 458 dwmci_writel(host, DWMCI_RINTSTS, mask); 459 break; 460 } 461 } while (!(get_timer(start) > timeout)); 462 463 if (get_timer(start) > timeout) { 464 debug("%s: Timeout.\n", __func__); 465 return -ETIMEDOUT; 466 } 467 468 if (mask & DWMCI_INTMSK_RTO) { 469 /* 470 * Timeout here is not necessarily fatal. (e)MMC cards 471 * will splat here when they receive CMD55 as they do 472 * not support this command and that is exactly the way 473 * to tell them apart from SD cards. Thus, this output 474 * below shall be debug(). eMMC cards also do not favor 475 * CMD8, please keep that in mind. 476 */ 477 debug("%s: Response Timeout.\n", __func__); 478 return -ETIMEDOUT; 479 } else if (mask & DWMCI_INTMSK_RE) { 480 debug("%s: Response Error.\n", __func__); 481 return -EIO; 482 } 483 484 485 if (cmd->resp_type & MMC_RSP_PRESENT) { 486 if (cmd->resp_type & MMC_RSP_136) { 487 cmd->response[0] = dwmci_readl(host, DWMCI_RESP3); 488 cmd->response[1] = dwmci_readl(host, DWMCI_RESP2); 489 cmd->response[2] = dwmci_readl(host, DWMCI_RESP1); 490 cmd->response[3] = dwmci_readl(host, DWMCI_RESP0); 491 } else { 492 cmd->response[0] = dwmci_readl(host, DWMCI_RESP0); 493 } 494 } 495 496 if (data) { 497 ret = dwmci_data_transfer(host, data); 498 499 /* only dma mode need it */ 500 if (!host->fifo_mode) { 501 ctrl = dwmci_readl(host, DWMCI_CTRL); 502 ctrl &= ~(DWMCI_DMA_EN); 503 dwmci_writel(host, DWMCI_CTRL, ctrl); 504 bounce_buffer_stop(&bbstate); 505 } 506 } 507 508 return ret; 509 } 510 511 #ifdef CONFIG_SPL_BLK_READ_PREPARE 512 #ifdef CONFIG_DM_MMC 513 static int dwmci_send_cmd_prepare(struct udevice *dev, struct mmc_cmd *cmd, 514 struct mmc_data *data) 515 { 516 struct mmc *mmc = mmc_get_mmc_dev(dev); 517 #else 518 static int dwmci_send_cmd_prepare(struct mmc *mmc, struct mmc_cmd *cmd, 519 struct mmc_data *data) 520 { 521 #endif 522 struct dwmci_host *host = mmc->priv; 523 struct dwmci_idmac *cur_idmac; 524 int ret = 0, flags = 0; 525 unsigned int timeout = 500; 526 u32 mask; 527 ulong start = get_timer(0); 528 struct bounce_buffer bbstate; 529 530 cur_idmac = malloc(ROUND(DIV_ROUND_UP(data->blocks, 8) * 531 sizeof(struct dwmci_idmac), 532 ARCH_DMA_MINALIGN) + ARCH_DMA_MINALIGN - 1); 533 if (!cur_idmac) 534 return -ENODATA; 535 536 while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) { 537 if (get_timer(start) > timeout) { 538 debug("%s: Timeout on data busy\n", __func__); 539 return -ETIMEDOUT; 540 } 541 } 542 543 dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL); 544 545 if (data) { 546 if (host->fifo_mode) { 547 dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize); 548 dwmci_writel(host, DWMCI_BYTCNT, 549 data->blocksize * data->blocks); 550 dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET); 551 } else { 552 if (data->flags == MMC_DATA_READ) { 553 bounce_buffer_start(&bbstate, (void *)data->dest, 554 data->blocksize * 555 data->blocks, GEN_BB_WRITE); 556 } else { 557 bounce_buffer_start(&bbstate, (void *)data->src, 558 data->blocksize * 559 data->blocks, GEN_BB_READ); 560 } 561 dwmci_prepare_data(host, data, cur_idmac, 562 bbstate.bounce_buffer); 563 } 564 } 565 566 dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg); 567 568 if (data) 569 flags = dwmci_set_transfer_mode(host, data); 570 571 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) 572 return -1; 573 574 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 575 flags |= DWMCI_CMD_ABORT_STOP; 576 else 577 flags |= DWMCI_CMD_PRV_DAT_WAIT; 578 579 if (cmd->resp_type & MMC_RSP_PRESENT) { 580 flags |= DWMCI_CMD_RESP_EXP; 581 if (cmd->resp_type & MMC_RSP_136) 582 flags |= DWMCI_CMD_RESP_LENGTH; 583 } 584 585 if (cmd->resp_type & MMC_RSP_CRC) 586 flags |= DWMCI_CMD_CHECK_CRC; 587 588 flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG); 589 590 debug("Sending CMD%d\n", cmd->cmdidx); 591 592 dwmci_writel(host, DWMCI_CMD, flags); 593 594 timeout = dwmci_get_cto(host); 595 start = get_timer(0); 596 do { 597 mask = dwmci_readl(host, DWMCI_RINTSTS); 598 if (mask & DWMCI_INTMSK_CDONE) { 599 if (!data) 600 dwmci_writel(host, DWMCI_RINTSTS, mask); 601 break; 602 } 603 } while (!(get_timer(start) > timeout)); 604 605 if (get_timer(start) > timeout) { 606 debug("%s: Timeout.\n", __func__); 607 return -ETIMEDOUT; 608 } 609 610 if (mask & DWMCI_INTMSK_RTO) { 611 /* 612 * Timeout here is not necessarily fatal. (e)MMC cards 613 * will splat here when they receive CMD55 as they do 614 * not support this command and that is exactly the way 615 * to tell them apart from SD cards. Thus, this output 616 * below shall be debug(). eMMC cards also do not favor 617 * CMD8, please keep that in mind. 618 */ 619 debug("%s: Response Timeout.\n", __func__); 620 return -ETIMEDOUT; 621 } else if (mask & DWMCI_INTMSK_RE) { 622 debug("%s: Response Error.\n", __func__); 623 return -EIO; 624 } 625 626 if (cmd->resp_type & MMC_RSP_PRESENT) { 627 if (cmd->resp_type & MMC_RSP_136) { 628 cmd->response[0] = dwmci_readl(host, DWMCI_RESP3); 629 cmd->response[1] = dwmci_readl(host, DWMCI_RESP2); 630 cmd->response[2] = dwmci_readl(host, DWMCI_RESP1); 631 cmd->response[3] = dwmci_readl(host, DWMCI_RESP0); 632 } else { 633 cmd->response[0] = dwmci_readl(host, DWMCI_RESP0); 634 } 635 } 636 637 return ret; 638 } 639 #endif 640 641 static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) 642 { 643 u32 div, status; 644 int timeout = 10000; 645 unsigned long sclk; 646 647 if (freq == 0) 648 return 0; 649 /* 650 * If host->get_mmc_clk isn't defined, 651 * then assume that host->bus_hz is source clock value. 652 * host->bus_hz should be set by user. 653 */ 654 if (host->get_mmc_clk) 655 sclk = host->get_mmc_clk(host, freq); 656 else if (host->bus_hz) 657 sclk = host->bus_hz; 658 else { 659 debug("%s: Didn't get source clock value.\n", __func__); 660 return -EINVAL; 661 } 662 663 if (sclk == 0) 664 return -EINVAL; 665 666 if (sclk == freq) 667 div = 0; /* bypass mode */ 668 else 669 div = DIV_ROUND_UP(sclk, 2 * freq); 670 671 dwmci_writel(host, DWMCI_CLKENA, 0); 672 dwmci_writel(host, DWMCI_CLKSRC, 0); 673 674 dwmci_writel(host, DWMCI_CLKDIV, div); 675 dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT | 676 DWMCI_CMD_UPD_CLK | DWMCI_CMD_START); 677 678 do { 679 status = dwmci_readl(host, DWMCI_CMD); 680 if (timeout-- < 0) { 681 debug("%s: Timeout!\n", __func__); 682 return -ETIMEDOUT; 683 } 684 } while (status & DWMCI_CMD_START); 685 686 dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE | 687 DWMCI_CLKEN_LOW_PWR); 688 689 dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT | 690 DWMCI_CMD_UPD_CLK | DWMCI_CMD_START); 691 692 timeout = 10000; 693 do { 694 status = dwmci_readl(host, DWMCI_CMD); 695 if (timeout-- < 0) { 696 debug("%s: Timeout!\n", __func__); 697 return -ETIMEDOUT; 698 } 699 } while (status & DWMCI_CMD_START); 700 701 host->clock = freq; 702 703 return 0; 704 } 705 706 #ifdef CONFIG_DM_MMC 707 static bool dwmci_card_busy(struct udevice *dev) 708 { 709 struct mmc *mmc = mmc_get_mmc_dev(dev); 710 #else 711 static bool dwmci_card_busy(struct mmc *mmc) 712 { 713 #endif 714 u32 status; 715 struct dwmci_host *host = (struct dwmci_host *)mmc->priv; 716 717 /* 718 * Check the busy bit which is low when DAT[3:0] 719 * (the data lines) are 0000 720 */ 721 status = dwmci_readl(host, DWMCI_STATUS); 722 723 return !!(status & DWMCI_BUSY); 724 } 725 726 #ifdef CONFIG_DM_MMC 727 static int dwmci_execute_tuning(struct udevice *dev, u32 opcode) 728 { 729 struct mmc *mmc = mmc_get_mmc_dev(dev); 730 #else 731 static int dwmci_execute_tuning(struct mmc *mmc, u32 opcode) 732 { 733 #endif 734 struct dwmci_host *host = (struct dwmci_host *)mmc->priv; 735 736 if (!host->execute_tuning) 737 return -EIO; 738 739 return host->execute_tuning(host, opcode); 740 } 741 742 #ifdef CONFIG_DM_MMC 743 static int dwmci_set_ios(struct udevice *dev) 744 { 745 struct mmc *mmc = mmc_get_mmc_dev(dev); 746 #else 747 static int dwmci_set_ios(struct mmc *mmc) 748 { 749 #endif 750 struct dwmci_host *host = (struct dwmci_host *)mmc->priv; 751 u32 ctype, regs; 752 753 debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock); 754 755 dwmci_setup_bus(host, mmc->clock); 756 switch (mmc->bus_width) { 757 case 8: 758 ctype = DWMCI_CTYPE_8BIT; 759 break; 760 case 4: 761 ctype = DWMCI_CTYPE_4BIT; 762 break; 763 default: 764 ctype = DWMCI_CTYPE_1BIT; 765 break; 766 } 767 768 dwmci_writel(host, DWMCI_CTYPE, ctype); 769 770 regs = dwmci_readl(host, DWMCI_UHS_REG); 771 if (mmc_card_ddr(mmc)) 772 regs |= DWMCI_DDR_MODE; 773 else 774 regs &= ~DWMCI_DDR_MODE; 775 776 dwmci_writel(host, DWMCI_UHS_REG, regs); 777 778 if (host->clksel) 779 host->clksel(host); 780 781 return 0; 782 } 783 784 static int dwmci_init(struct mmc *mmc) 785 { 786 struct dwmci_host *host = mmc->priv; 787 uint32_t use_dma; 788 uint32_t verid; 789 790 #if defined(CONFIG_DM_GPIO) && (defined(CONFIG_SPL_GPIO_SUPPORT) || !defined(CONFIG_SPL_BUILD)) 791 struct gpio_desc pwr_en_gpio; 792 u32 delay_ms; 793 794 if (mmc_getcd(mmc) == 1 && 795 !gpio_request_by_name(mmc->dev, "pwr-en-gpios", 0, &pwr_en_gpio, GPIOD_IS_OUT)) { 796 dm_gpio_set_value(&pwr_en_gpio, 0); 797 pinctrl_select_state(mmc->dev, "idle"); 798 delay_ms = dev_read_u32_default(mmc->dev, "power-off-delay-ms", 200); 799 mdelay(delay_ms); 800 dm_gpio_set_value(&pwr_en_gpio, 1); 801 pinctrl_select_state(mmc->dev, "default"); 802 dm_gpio_free(mmc->dev, &pwr_en_gpio); 803 } 804 #endif 805 806 if (host->board_init) 807 host->board_init(host); 808 #ifdef CONFIG_ARCH_ROCKCHIP 809 if (host->dev_index == 0) 810 dwmci_writel(host, DWMCI_PWREN, 1); 811 else if (host->dev_index == 1) 812 dwmci_writel(host, DWMCI_PWREN, 0); 813 else 814 dwmci_writel(host, DWMCI_PWREN, 1); 815 #else 816 dwmci_writel(host, DWMCI_PWREN, 1); 817 #endif 818 819 verid = dwmci_readl(host, DWMCI_VERID) & 0x0000ffff; 820 if (verid >= DW_MMC_240A) 821 dwmci_writel(host, DWMCI_CARDTHRCTL, DWMCI_CDTHRCTRL_CONFIG); 822 823 if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) { 824 debug("%s[%d] Fail-reset!!\n", __func__, __LINE__); 825 return -EIO; 826 } 827 828 use_dma = SDMMC_GET_TRANS_MODE(dwmci_readl(host, DWMCI_HCON)); 829 if (use_dma == DMA_INTERFACE_IDMA) { 830 host->fifo_mode = 0; 831 } else { 832 host->fifo_mode = 1; 833 } 834 835 /* Enumerate at 400KHz */ 836 dwmci_setup_bus(host, mmc->cfg->f_min); 837 838 dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF); 839 dwmci_writel(host, DWMCI_INTMASK, 0); 840 841 dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF); 842 843 dwmci_writel(host, DWMCI_IDINTEN, 0); 844 dwmci_writel(host, DWMCI_BMOD, 1); 845 846 if (!host->fifoth_val) { 847 uint32_t fifo_size; 848 849 fifo_size = dwmci_readl(host, DWMCI_FIFOTH); 850 fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1; 851 host->fifoth_val = MSIZE(DWMCI_MSIZE) | 852 RX_WMARK(fifo_size / 2 - 1) | 853 TX_WMARK(fifo_size / 2); 854 } 855 dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val); 856 857 dwmci_writel(host, DWMCI_CLKENA, 0); 858 dwmci_writel(host, DWMCI_CLKSRC, 0); 859 860 return 0; 861 } 862 863 static int dwmci_get_cd(struct udevice *dev) 864 { 865 int ret = -1; 866 867 #if defined(CONFIG_DM_GPIO) && (defined(CONFIG_SPL_GPIO_SUPPORT) || !defined(CONFIG_SPL_BUILD)) 868 struct gpio_desc detect; 869 870 ret = gpio_request_by_name(dev, "cd-gpios", 0, &detect, GPIOD_IS_IN); 871 if (ret) { 872 return ret; 873 } 874 875 ret = !dm_gpio_get_value(&detect); 876 dm_gpio_free(dev, &detect); 877 #endif 878 return ret; 879 } 880 881 #ifdef CONFIG_DM_MMC 882 int dwmci_probe(struct udevice *dev) 883 { 884 struct mmc *mmc = mmc_get_mmc_dev(dev); 885 886 return dwmci_init(mmc); 887 } 888 889 const struct dm_mmc_ops dm_dwmci_ops = { 890 .card_busy = dwmci_card_busy, 891 .send_cmd = dwmci_send_cmd, 892 #ifdef CONFIG_SPL_BLK_READ_PREPARE 893 .send_cmd_prepare = dwmci_send_cmd_prepare, 894 #endif 895 .set_ios = dwmci_set_ios, 896 .get_cd = dwmci_get_cd, 897 .execute_tuning = dwmci_execute_tuning, 898 }; 899 900 #else 901 static const struct mmc_ops dwmci_ops = { 902 .card_busy = dwmci_card_busy, 903 .send_cmd = dwmci_send_cmd, 904 .set_ios = dwmci_set_ios, 905 .get_cd = dwmci_get_cd, 906 .init = dwmci_init, 907 .execute_tuning = dwmci_execute_tuning, 908 }; 909 #endif 910 911 void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host, 912 u32 max_clk, u32 min_clk) 913 { 914 cfg->name = host->name; 915 #ifndef CONFIG_DM_MMC 916 cfg->ops = &dwmci_ops; 917 #endif 918 cfg->f_min = min_clk; 919 cfg->f_max = max_clk; 920 921 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 922 923 cfg->host_caps = host->caps; 924 925 switch (host->buswidth) { 926 case 8: 927 cfg->host_caps |= MMC_MODE_8BIT | MMC_MODE_4BIT; 928 break; 929 case 4: 930 cfg->host_caps |= MMC_MODE_4BIT; 931 cfg->host_caps &= ~MMC_MODE_8BIT; 932 break; 933 case 1: 934 cfg->host_caps &= ~MMC_MODE_4BIT; 935 cfg->host_caps &= ~MMC_MODE_8BIT; 936 break; 937 default: 938 printf("Unsupported bus width: %d\n", host->buswidth); 939 break; 940 } 941 cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz; 942 943 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 944 } 945 946 #ifdef CONFIG_BLK 947 int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg) 948 { 949 return mmc_bind(dev, mmc, cfg); 950 } 951 #else 952 int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk) 953 { 954 dwmci_setup_cfg(&host->cfg, host, max_clk, min_clk); 955 956 host->mmc = mmc_create(&host->cfg, host); 957 if (host->mmc == NULL) 958 return -1; 959 960 return 0; 961 } 962 #endif 963