1 /* 2 * (C) Copyright 2012 SAMSUNG Electronics 3 * Jaehoon Chung <jh80.chung@samsung.com> 4 * Rajeshawari Shinde <rajeshwari.s@samsung.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <bouncebuf.h> 11 #include <div64.h> 12 #include <errno.h> 13 #include <malloc.h> 14 #include <memalign.h> 15 #include <mmc.h> 16 #include <dwmmc.h> 17 #include <dm/pinctrl.h> 18 #include <dm.h> 19 #ifdef CONFIG_DM_GPIO 20 #include <asm/gpio.h> 21 #include <asm-generic/gpio.h> 22 #endif 23 24 #define PAGE_SIZE 4096 25 #define MSEC_PER_SEC 1000ULL 26 27 /* 28 * Currently it supports read/write up to 8*8*4 Bytes per 29 * stride as a burst mode. Please note that if you change 30 * MAX_STRIDE, you should also update dwmci_memcpy_fromio 31 * to augment the groups of {ldm, stm}. 32 */ 33 #define MAX_STRIDE 64 34 #if (CONFIG_ARM && CONFIG_CPU_V7 && !defined(CONFIG_MMC_SIMPLE)) 35 void noinline dwmci_memcpy_fromio(void *buffer, void *fifo_addr) 36 { 37 __asm__ __volatile__ ( 38 "push {r2, r3, r4, r5, r6, r7, r8, r9}\n" 39 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 40 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 41 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 42 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 43 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 44 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 45 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 46 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 47 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 48 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 49 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 50 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 51 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 52 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 53 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 54 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 55 "pop {r2, r3, r4, r5, r6,r7,r8,r9}\n" 56 :::"memory" 57 ); 58 } 59 60 void noinline dwmci_memcpy_toio(void *buffer, void *fifo_addr) 61 { 62 __asm__ __volatile__ ( 63 "push {r2, r3, r4, r5, r6, r7, r8, r9}\n" 64 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 65 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 66 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 67 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 68 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 69 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 70 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 71 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 72 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 73 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 74 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 75 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 76 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 77 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 78 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 79 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 80 "pop {r2, r3, r4, r5, r6,r7,r8,r9}\n" 81 :::"memory" 82 ); 83 } 84 #else 85 void dwmci_memcpy_fromio(void *buffer, void *fifo_addr) {}; 86 void dwmci_memcpy_toio(void *buffer, void *fifo_addr) {}; 87 #endif 88 89 static int dwmci_wait_reset(struct dwmci_host *host, u32 value) 90 { 91 unsigned long timeout = 1000; 92 u32 ctrl; 93 94 dwmci_writel(host, DWMCI_CTRL, value); 95 96 while (timeout--) { 97 ctrl = dwmci_readl(host, DWMCI_CTRL); 98 if (!(ctrl & DWMCI_RESET_ALL)) 99 return 1; 100 } 101 return 0; 102 } 103 104 static void dwmci_set_idma_desc(struct dwmci_idmac *idmac, 105 u32 desc0, u32 desc1, u32 desc2) 106 { 107 struct dwmci_idmac *desc = idmac; 108 109 desc->flags = desc0; 110 desc->cnt = desc1; 111 desc->addr = desc2; 112 desc->next_addr = (ulong)desc + sizeof(struct dwmci_idmac); 113 } 114 115 static void dwmci_prepare_data(struct dwmci_host *host, 116 struct mmc_data *data, 117 struct dwmci_idmac *cur_idmac, 118 void *bounce_buffer) 119 { 120 unsigned long ctrl; 121 unsigned int i = 0, flags, cnt, blk_cnt; 122 ulong data_start, data_end; 123 124 125 blk_cnt = data->blocks; 126 127 dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET); 128 129 data_start = (ulong)cur_idmac; 130 dwmci_writel(host, DWMCI_DBADDR, (ulong)cur_idmac); 131 132 do { 133 flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ; 134 flags |= (i == 0) ? DWMCI_IDMAC_FS : 0; 135 if (blk_cnt <= 8) { 136 flags |= DWMCI_IDMAC_LD; 137 cnt = data->blocksize * blk_cnt; 138 } else 139 cnt = data->blocksize * 8; 140 141 dwmci_set_idma_desc(cur_idmac, flags, cnt, 142 (ulong)bounce_buffer + (i * PAGE_SIZE)); 143 144 if (blk_cnt <= 8) 145 break; 146 blk_cnt -= 8; 147 cur_idmac++; 148 i++; 149 } while(1); 150 151 data_end = (ulong)cur_idmac; 152 flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN); 153 154 ctrl = dwmci_readl(host, DWMCI_CTRL); 155 ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN; 156 dwmci_writel(host, DWMCI_CTRL, ctrl); 157 158 ctrl = dwmci_readl(host, DWMCI_BMOD); 159 ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN; 160 dwmci_writel(host, DWMCI_BMOD, ctrl); 161 162 dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize); 163 dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks); 164 } 165 166 #ifdef CONFIG_SPL_BUILD 167 static unsigned int dwmci_get_drto(struct dwmci_host *host, 168 const unsigned int size) 169 { 170 unsigned int drto_clks; 171 unsigned int drto_div; 172 unsigned int drto_ms; 173 174 drto_clks = dwmci_readl(host, DWMCI_TMOUT) >> 8; 175 drto_div = (dwmci_readl(host, DWMCI_CLKDIV) & 0xff) * 2; 176 if (drto_div == 0) 177 drto_div = 1; 178 179 drto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * drto_clks * drto_div, 180 host->mmc->clock); 181 182 /* add a bit spare time */ 183 drto_ms += 10; 184 185 return drto_ms; 186 } 187 #else 188 static unsigned int dwmci_get_drto(struct dwmci_host *host, 189 const unsigned int size) 190 { 191 unsigned int timeout; 192 193 timeout = size * 8; /* counting in bits */ 194 timeout *= 10; /* wait 10 times as long */ 195 timeout /= host->mmc->clock; 196 timeout /= host->mmc->bus_width; 197 timeout *= 1000; /* counting in msec */ 198 timeout = (timeout < 10000) ? 10000 : timeout; 199 200 return timeout; 201 } 202 #endif 203 204 static unsigned int dwmci_get_cto(struct dwmci_host *host) 205 { 206 unsigned int cto_clks; 207 unsigned int cto_div; 208 unsigned int cto_ms; 209 210 cto_clks = dwmci_readl(host, DWMCI_TMOUT) & 0xff; 211 cto_div = (dwmci_readl(host, DWMCI_CLKDIV) & 0xff) * 2; 212 if (cto_div == 0) 213 cto_div = 1; 214 215 cto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * cto_clks * cto_div, 216 host->mmc->clock); 217 218 /* add a bit spare time */ 219 cto_ms += 10; 220 221 return cto_ms; 222 } 223 224 static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data) 225 { 226 int ret = 0; 227 int reset_timeout = 100; 228 u32 timeout, status, ctrl, mask, size, i, len = 0; 229 u32 *buf = NULL; 230 ulong start = get_timer(0); 231 u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >> 232 RX_WMARK_SHIFT) + 1) * 2; 233 bool stride; 234 235 size = data->blocksize * data->blocks; 236 /* Still use legacy PIO mode if size < 512(128 * 4) Bytes */ 237 stride = host->stride_pio && size > 128; 238 if (data->flags == MMC_DATA_READ) 239 buf = (unsigned int *)data->dest; 240 else 241 buf = (unsigned int *)data->src; 242 243 timeout = dwmci_get_drto(host, size); 244 /* The tuning data is 128bytes, a timeout of 1ms is sufficient.*/ 245 if ((dwmci_readl(host, DWMCI_CMD) & 0x1F) == MMC_SEND_TUNING_BLOCK_HS200) 246 timeout = 1; 247 248 size /= 4; 249 250 for (;;) { 251 mask = dwmci_readl(host, DWMCI_RINTSTS); 252 /* Error during data transfer. */ 253 if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) { 254 debug("%s: DATA ERROR!\n", __func__); 255 /* 256 * It is necessary to wait for several cycles before 257 * resetting the controller while data timeout or error. 258 */ 259 udelay(1); 260 dwmci_wait_reset(host, DWMCI_RESET_ALL); 261 dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT | 262 DWMCI_CMD_UPD_CLK | DWMCI_CMD_START); 263 264 do { 265 status = dwmci_readl(host, DWMCI_CMD); 266 if (reset_timeout-- < 0) 267 break; 268 udelay(100); 269 } while (status & DWMCI_CMD_START); 270 271 if (!host->fifo_mode) { 272 ctrl = dwmci_readl(host, DWMCI_BMOD); 273 ctrl |= DWMCI_BMOD_IDMAC_RESET; 274 dwmci_writel(host, DWMCI_BMOD, ctrl); 275 } 276 277 ret = -EINVAL; 278 break; 279 } 280 281 if (host->fifo_mode && size) { 282 len = 0; 283 if (data->flags == MMC_DATA_READ && 284 (mask & DWMCI_INTMSK_RXDR)) { 285 while (size) { 286 len = dwmci_readl(host, DWMCI_STATUS); 287 len = (len >> DWMCI_FIFO_SHIFT) & 288 DWMCI_FIFO_MASK; 289 len = min(size, len); 290 if (!stride) { 291 /* Legacy pio mode */ 292 for (i = 0; i < len; i++) 293 *buf++ = dwmci_readl(host, DWMCI_DATA); 294 goto read_again; 295 } 296 297 /* dwmci_memcpy_fromio now bursts 256 Bytes once */ 298 if (len < MAX_STRIDE) 299 continue; 300 301 for (i = 0; i < len / MAX_STRIDE; i++) { 302 dwmci_memcpy_fromio(buf, host->ioaddr + DWMCI_DATA); 303 buf += MAX_STRIDE; 304 } 305 306 len = i * MAX_STRIDE; 307 read_again: 308 size = size > len ? (size - len) : 0; 309 } 310 dwmci_writel(host, DWMCI_RINTSTS, 311 DWMCI_INTMSK_RXDR); 312 start = get_timer(0); 313 } else if (data->flags == MMC_DATA_WRITE && 314 (mask & DWMCI_INTMSK_TXDR)) { 315 while (size) { 316 len = dwmci_readl(host, DWMCI_STATUS); 317 len = fifo_depth - ((len >> 318 DWMCI_FIFO_SHIFT) & 319 DWMCI_FIFO_MASK); 320 len = min(size, len); 321 if (!stride) { 322 for (i = 0; i < len; i++) 323 dwmci_writel(host, DWMCI_DATA, 324 *buf++); 325 goto write_again; 326 } 327 /* dwmci_memcpy_toio now bursts 256 Bytes once */ 328 if (len < MAX_STRIDE) 329 continue; 330 331 for (i = 0; i < len / MAX_STRIDE; i++) { 332 dwmci_memcpy_toio(buf, host->ioaddr + DWMCI_DATA); 333 buf += MAX_STRIDE; 334 } 335 336 len = i * MAX_STRIDE; 337 write_again: 338 size = size > len ? (size - len) : 0; 339 } 340 dwmci_writel(host, DWMCI_RINTSTS, 341 DWMCI_INTMSK_TXDR); 342 start = get_timer(0); 343 } 344 } 345 346 /* Data arrived correctly. */ 347 if (mask & DWMCI_INTMSK_DTO) { 348 ret = 0; 349 break; 350 } 351 352 /* Check for timeout. */ 353 if (get_timer(start) > timeout) { 354 debug("%s: Timeout waiting for data!\n", 355 __func__); 356 ret = -ETIMEDOUT; 357 break; 358 } 359 } 360 361 dwmci_writel(host, DWMCI_RINTSTS, mask); 362 363 return ret; 364 } 365 366 static int dwmci_set_transfer_mode(struct dwmci_host *host, 367 struct mmc_data *data) 368 { 369 unsigned long mode; 370 371 mode = DWMCI_CMD_DATA_EXP; 372 if (data->flags & MMC_DATA_WRITE) 373 mode |= DWMCI_CMD_RW; 374 375 return mode; 376 } 377 378 #ifdef CONFIG_DM_MMC 379 static int dwmci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, 380 struct mmc_data *data) 381 { 382 struct mmc *mmc = mmc_get_mmc_dev(dev); 383 #else 384 static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 385 struct mmc_data *data) 386 { 387 #endif 388 struct dwmci_host *host = mmc->priv; 389 ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac, 390 data ? DIV_ROUND_UP(data->blocks, 8) : 0); 391 int ret = 0, flags = 0; 392 unsigned int timeout = 500; 393 u32 mask, ctrl; 394 ulong start = get_timer(0); 395 struct bounce_buffer bbstate; 396 397 while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) { 398 if (get_timer(start) > timeout) { 399 debug("%s: Timeout on data busy\n", __func__); 400 return -ETIMEDOUT; 401 } 402 } 403 404 dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL); 405 406 if (data) { 407 if (host->fifo_mode) { 408 dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize); 409 dwmci_writel(host, DWMCI_BYTCNT, 410 data->blocksize * data->blocks); 411 dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET); 412 } else { 413 if (data->flags == MMC_DATA_READ) { 414 ret = bounce_buffer_start(&bbstate, 415 (void*)data->dest, 416 data->blocksize * 417 data->blocks, GEN_BB_WRITE); 418 } else { 419 ret = bounce_buffer_start(&bbstate, 420 (void*)data->src, 421 data->blocksize * 422 data->blocks, GEN_BB_READ); 423 } 424 425 if (ret) 426 return ret; 427 428 dwmci_prepare_data(host, data, cur_idmac, 429 bbstate.bounce_buffer); 430 } 431 } 432 433 dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg); 434 435 if (data) 436 flags = dwmci_set_transfer_mode(host, data); 437 438 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) 439 return -1; 440 441 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 442 flags |= DWMCI_CMD_ABORT_STOP; 443 else 444 flags |= DWMCI_CMD_PRV_DAT_WAIT; 445 446 if (cmd->resp_type & MMC_RSP_PRESENT) { 447 flags |= DWMCI_CMD_RESP_EXP; 448 if (cmd->resp_type & MMC_RSP_136) 449 flags |= DWMCI_CMD_RESP_LENGTH; 450 } 451 452 if (cmd->resp_type & MMC_RSP_CRC) 453 flags |= DWMCI_CMD_CHECK_CRC; 454 455 flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG); 456 457 debug("Sending CMD%d\n",cmd->cmdidx); 458 459 dwmci_writel(host, DWMCI_CMD, flags); 460 461 timeout = dwmci_get_cto(host); 462 start = get_timer(0); 463 do { 464 mask = dwmci_readl(host, DWMCI_RINTSTS); 465 if (mask & DWMCI_INTMSK_CDONE) { 466 if (!data) 467 dwmci_writel(host, DWMCI_RINTSTS, mask); 468 break; 469 } 470 } while (!(get_timer(start) > timeout)); 471 472 if (get_timer(start) > timeout) { 473 debug("%s: Timeout.\n", __func__); 474 return -ETIMEDOUT; 475 } 476 477 if (mask & DWMCI_INTMSK_RTO) { 478 /* 479 * Timeout here is not necessarily fatal. (e)MMC cards 480 * will splat here when they receive CMD55 as they do 481 * not support this command and that is exactly the way 482 * to tell them apart from SD cards. Thus, this output 483 * below shall be debug(). eMMC cards also do not favor 484 * CMD8, please keep that in mind. 485 */ 486 debug("%s: Response Timeout.\n", __func__); 487 return -ETIMEDOUT; 488 } else if (mask & DWMCI_INTMSK_RE) { 489 debug("%s: Response Error.\n", __func__); 490 return -EIO; 491 } 492 493 494 if (cmd->resp_type & MMC_RSP_PRESENT) { 495 if (cmd->resp_type & MMC_RSP_136) { 496 cmd->response[0] = dwmci_readl(host, DWMCI_RESP3); 497 cmd->response[1] = dwmci_readl(host, DWMCI_RESP2); 498 cmd->response[2] = dwmci_readl(host, DWMCI_RESP1); 499 cmd->response[3] = dwmci_readl(host, DWMCI_RESP0); 500 } else { 501 cmd->response[0] = dwmci_readl(host, DWMCI_RESP0); 502 } 503 } 504 505 if (data) { 506 ret = dwmci_data_transfer(host, data); 507 508 /* only dma mode need it */ 509 if (!host->fifo_mode) { 510 ctrl = dwmci_readl(host, DWMCI_CTRL); 511 ctrl &= ~(DWMCI_DMA_EN); 512 dwmci_writel(host, DWMCI_CTRL, ctrl); 513 bounce_buffer_stop(&bbstate); 514 } 515 } 516 517 return ret; 518 } 519 520 #ifdef CONFIG_SPL_BLK_READ_PREPARE 521 #ifdef CONFIG_DM_MMC 522 static int dwmci_send_cmd_prepare(struct udevice *dev, struct mmc_cmd *cmd, 523 struct mmc_data *data) 524 { 525 struct mmc *mmc = mmc_get_mmc_dev(dev); 526 #else 527 static int dwmci_send_cmd_prepare(struct mmc *mmc, struct mmc_cmd *cmd, 528 struct mmc_data *data) 529 { 530 #endif 531 struct dwmci_host *host = mmc->priv; 532 struct dwmci_idmac *cur_idmac; 533 int ret = 0, flags = 0; 534 unsigned int timeout = 500; 535 u32 mask; 536 ulong start = get_timer(0); 537 struct bounce_buffer bbstate; 538 539 cur_idmac = malloc(ROUND(DIV_ROUND_UP(data->blocks, 8) * 540 sizeof(struct dwmci_idmac), 541 ARCH_DMA_MINALIGN) + ARCH_DMA_MINALIGN - 1); 542 if (!cur_idmac) 543 return -ENODATA; 544 545 while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) { 546 if (get_timer(start) > timeout) { 547 debug("%s: Timeout on data busy\n", __func__); 548 return -ETIMEDOUT; 549 } 550 } 551 552 dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL); 553 554 if (data) { 555 if (host->fifo_mode) { 556 dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize); 557 dwmci_writel(host, DWMCI_BYTCNT, 558 data->blocksize * data->blocks); 559 dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET); 560 } else { 561 if (data->flags == MMC_DATA_READ) { 562 bounce_buffer_start(&bbstate, (void *)data->dest, 563 data->blocksize * 564 data->blocks, GEN_BB_WRITE); 565 } else { 566 bounce_buffer_start(&bbstate, (void *)data->src, 567 data->blocksize * 568 data->blocks, GEN_BB_READ); 569 } 570 dwmci_prepare_data(host, data, cur_idmac, 571 bbstate.bounce_buffer); 572 } 573 } 574 575 dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg); 576 577 if (data) 578 flags = dwmci_set_transfer_mode(host, data); 579 580 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) 581 return -1; 582 583 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 584 flags |= DWMCI_CMD_ABORT_STOP; 585 else 586 flags |= DWMCI_CMD_PRV_DAT_WAIT; 587 588 if (cmd->resp_type & MMC_RSP_PRESENT) { 589 flags |= DWMCI_CMD_RESP_EXP; 590 if (cmd->resp_type & MMC_RSP_136) 591 flags |= DWMCI_CMD_RESP_LENGTH; 592 } 593 594 if (cmd->resp_type & MMC_RSP_CRC) 595 flags |= DWMCI_CMD_CHECK_CRC; 596 597 flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG); 598 599 debug("Sending CMD%d\n", cmd->cmdidx); 600 601 dwmci_writel(host, DWMCI_CMD, flags); 602 603 timeout = dwmci_get_cto(host); 604 start = get_timer(0); 605 do { 606 mask = dwmci_readl(host, DWMCI_RINTSTS); 607 if (mask & DWMCI_INTMSK_CDONE) { 608 if (!data) 609 dwmci_writel(host, DWMCI_RINTSTS, mask); 610 break; 611 } 612 } while (!(get_timer(start) > timeout)); 613 614 if (get_timer(start) > timeout) { 615 debug("%s: Timeout.\n", __func__); 616 return -ETIMEDOUT; 617 } 618 619 if (mask & DWMCI_INTMSK_RTO) { 620 /* 621 * Timeout here is not necessarily fatal. (e)MMC cards 622 * will splat here when they receive CMD55 as they do 623 * not support this command and that is exactly the way 624 * to tell them apart from SD cards. Thus, this output 625 * below shall be debug(). eMMC cards also do not favor 626 * CMD8, please keep that in mind. 627 */ 628 debug("%s: Response Timeout.\n", __func__); 629 return -ETIMEDOUT; 630 } else if (mask & DWMCI_INTMSK_RE) { 631 debug("%s: Response Error.\n", __func__); 632 return -EIO; 633 } 634 635 if (cmd->resp_type & MMC_RSP_PRESENT) { 636 if (cmd->resp_type & MMC_RSP_136) { 637 cmd->response[0] = dwmci_readl(host, DWMCI_RESP3); 638 cmd->response[1] = dwmci_readl(host, DWMCI_RESP2); 639 cmd->response[2] = dwmci_readl(host, DWMCI_RESP1); 640 cmd->response[3] = dwmci_readl(host, DWMCI_RESP0); 641 } else { 642 cmd->response[0] = dwmci_readl(host, DWMCI_RESP0); 643 } 644 } 645 646 return ret; 647 } 648 #endif 649 650 static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) 651 { 652 u32 div, status; 653 int timeout = 10000; 654 unsigned long sclk; 655 656 if (freq == 0) 657 return 0; 658 /* 659 * If host->get_mmc_clk isn't defined, 660 * then assume that host->bus_hz is source clock value. 661 * host->bus_hz should be set by user. 662 */ 663 if (host->get_mmc_clk) 664 sclk = host->get_mmc_clk(host, freq); 665 else if (host->bus_hz) 666 sclk = host->bus_hz; 667 else { 668 debug("%s: Didn't get source clock value.\n", __func__); 669 return -EINVAL; 670 } 671 672 if (sclk == 0) 673 return -EINVAL; 674 675 if (sclk == freq) 676 div = 0; /* bypass mode */ 677 else 678 div = DIV_ROUND_UP(sclk, 2 * freq); 679 680 dwmci_writel(host, DWMCI_CLKENA, 0); 681 dwmci_writel(host, DWMCI_CLKSRC, 0); 682 683 dwmci_writel(host, DWMCI_CLKDIV, div); 684 dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT | 685 DWMCI_CMD_UPD_CLK | DWMCI_CMD_START); 686 687 do { 688 status = dwmci_readl(host, DWMCI_CMD); 689 if (timeout-- < 0) { 690 debug("%s: Timeout!\n", __func__); 691 return -ETIMEDOUT; 692 } 693 } while (status & DWMCI_CMD_START); 694 695 dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE | 696 DWMCI_CLKEN_LOW_PWR); 697 698 dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT | 699 DWMCI_CMD_UPD_CLK | DWMCI_CMD_START); 700 701 timeout = 10000; 702 do { 703 status = dwmci_readl(host, DWMCI_CMD); 704 if (timeout-- < 0) { 705 debug("%s: Timeout!\n", __func__); 706 return -ETIMEDOUT; 707 } 708 } while (status & DWMCI_CMD_START); 709 710 host->clock = freq; 711 712 return 0; 713 } 714 715 #ifdef CONFIG_DM_MMC 716 static bool dwmci_card_busy(struct udevice *dev) 717 { 718 struct mmc *mmc = mmc_get_mmc_dev(dev); 719 #else 720 static bool dwmci_card_busy(struct mmc *mmc) 721 { 722 #endif 723 u32 status; 724 struct dwmci_host *host = (struct dwmci_host *)mmc->priv; 725 726 /* 727 * Check the busy bit which is low when DAT[3:0] 728 * (the data lines) are 0000 729 */ 730 status = dwmci_readl(host, DWMCI_STATUS); 731 732 return !!(status & DWMCI_BUSY); 733 } 734 735 #ifdef CONFIG_DM_MMC 736 static int dwmci_execute_tuning(struct udevice *dev, u32 opcode) 737 { 738 struct mmc *mmc = mmc_get_mmc_dev(dev); 739 #else 740 static int dwmci_execute_tuning(struct mmc *mmc, u32 opcode) 741 { 742 #endif 743 struct dwmci_host *host = (struct dwmci_host *)mmc->priv; 744 745 if (!host->execute_tuning) 746 return -EIO; 747 748 return host->execute_tuning(host, opcode); 749 } 750 751 #ifdef CONFIG_DM_MMC 752 static int dwmci_set_ios(struct udevice *dev) 753 { 754 struct mmc *mmc = mmc_get_mmc_dev(dev); 755 #else 756 static int dwmci_set_ios(struct mmc *mmc) 757 { 758 #endif 759 struct dwmci_host *host = (struct dwmci_host *)mmc->priv; 760 u32 ctype, regs; 761 762 debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock); 763 764 dwmci_setup_bus(host, mmc->clock); 765 switch (mmc->bus_width) { 766 case 8: 767 ctype = DWMCI_CTYPE_8BIT; 768 break; 769 case 4: 770 ctype = DWMCI_CTYPE_4BIT; 771 break; 772 default: 773 ctype = DWMCI_CTYPE_1BIT; 774 break; 775 } 776 777 dwmci_writel(host, DWMCI_CTYPE, ctype); 778 779 regs = dwmci_readl(host, DWMCI_UHS_REG); 780 if (mmc_card_ddr(mmc)) 781 regs |= DWMCI_DDR_MODE; 782 else 783 regs &= ~DWMCI_DDR_MODE; 784 785 dwmci_writel(host, DWMCI_UHS_REG, regs); 786 787 if (host->clksel) 788 host->clksel(host); 789 790 return 0; 791 } 792 793 static int dwmci_init(struct mmc *mmc) 794 { 795 struct dwmci_host *host = mmc->priv; 796 uint32_t use_dma; 797 uint32_t verid; 798 799 #if defined(CONFIG_DM_GPIO) && (defined(CONFIG_SPL_GPIO_SUPPORT) || !defined(CONFIG_SPL_BUILD)) 800 struct gpio_desc pwr_en_gpio; 801 u32 delay_ms; 802 803 if (mmc_getcd(mmc) == 1 && 804 !gpio_request_by_name(mmc->dev, "pwr-en-gpios", 0, &pwr_en_gpio, GPIOD_IS_OUT)) { 805 dm_gpio_set_value(&pwr_en_gpio, 0); 806 pinctrl_select_state(mmc->dev, "idle"); 807 delay_ms = dev_read_u32_default(mmc->dev, "power-off-delay-ms", 200); 808 mdelay(delay_ms); 809 dm_gpio_set_value(&pwr_en_gpio, 1); 810 pinctrl_select_state(mmc->dev, "default"); 811 dm_gpio_free(mmc->dev, &pwr_en_gpio); 812 } 813 #endif 814 815 if (host->board_init) 816 host->board_init(host); 817 #ifdef CONFIG_ARCH_ROCKCHIP 818 if (host->dev_index == 0) 819 dwmci_writel(host, DWMCI_PWREN, 1); 820 else if (host->dev_index == 1) 821 dwmci_writel(host, DWMCI_PWREN, 0); 822 else 823 dwmci_writel(host, DWMCI_PWREN, 1); 824 #else 825 dwmci_writel(host, DWMCI_PWREN, 1); 826 #endif 827 828 verid = dwmci_readl(host, DWMCI_VERID) & 0x0000ffff; 829 if (verid >= DW_MMC_240A) 830 dwmci_writel(host, DWMCI_CARDTHRCTL, DWMCI_CDTHRCTRL_CONFIG); 831 832 if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) { 833 debug("%s[%d] Fail-reset!!\n", __func__, __LINE__); 834 return -EIO; 835 } 836 837 use_dma = SDMMC_GET_TRANS_MODE(dwmci_readl(host, DWMCI_HCON)); 838 if (use_dma == DMA_INTERFACE_IDMA) { 839 host->fifo_mode = 0; 840 } else { 841 host->fifo_mode = 1; 842 } 843 844 /* Enumerate at 400KHz */ 845 dwmci_setup_bus(host, mmc->cfg->f_min); 846 847 dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF); 848 dwmci_writel(host, DWMCI_INTMASK, 0); 849 850 dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF); 851 852 dwmci_writel(host, DWMCI_IDINTEN, 0); 853 dwmci_writel(host, DWMCI_BMOD, 1); 854 855 if (!host->fifoth_val) { 856 uint32_t fifo_size; 857 858 fifo_size = dwmci_readl(host, DWMCI_FIFOTH); 859 fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1; 860 host->fifoth_val = MSIZE(DWMCI_MSIZE) | 861 RX_WMARK(fifo_size / 2 - 1) | 862 TX_WMARK(fifo_size / 2); 863 } 864 dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val); 865 866 dwmci_writel(host, DWMCI_CLKENA, 0); 867 dwmci_writel(host, DWMCI_CLKSRC, 0); 868 869 return 0; 870 } 871 872 static int dwmci_get_cd(struct udevice *dev) 873 { 874 int ret = -1; 875 struct mmc *mmc = mmc_get_mmc_dev(dev); 876 struct dwmci_host *host = mmc->priv; 877 878 #if defined(CONFIG_DM_GPIO) && (defined(CONFIG_SPL_GPIO_SUPPORT) || !defined(CONFIG_SPL_BUILD)) 879 struct gpio_desc detect; 880 881 ret = gpio_request_by_name(dev, "cd-gpios", 0, &detect, GPIOD_IS_IN); 882 if (ret) { 883 goto dw_mmc_cdetect; 884 } 885 886 ret = !dm_gpio_get_value(&detect); 887 dm_gpio_free(dev, &detect); 888 return ret; 889 dw_mmc_cdetect: 890 #endif 891 ret = (dwmci_readl(host, DWMCI_CDETECT) & (1 << 0)) == 0 ? 1 : 0; 892 893 return ret; 894 } 895 896 #ifdef CONFIG_DM_MMC 897 int dwmci_probe(struct udevice *dev) 898 { 899 struct mmc *mmc = mmc_get_mmc_dev(dev); 900 901 return dwmci_init(mmc); 902 } 903 904 const struct dm_mmc_ops dm_dwmci_ops = { 905 .card_busy = dwmci_card_busy, 906 .send_cmd = dwmci_send_cmd, 907 #ifdef CONFIG_SPL_BLK_READ_PREPARE 908 .send_cmd_prepare = dwmci_send_cmd_prepare, 909 #endif 910 .set_ios = dwmci_set_ios, 911 .get_cd = dwmci_get_cd, 912 .execute_tuning = dwmci_execute_tuning, 913 }; 914 915 #else 916 static const struct mmc_ops dwmci_ops = { 917 .card_busy = dwmci_card_busy, 918 .send_cmd = dwmci_send_cmd, 919 .set_ios = dwmci_set_ios, 920 .get_cd = dwmci_get_cd, 921 .init = dwmci_init, 922 .execute_tuning = dwmci_execute_tuning, 923 }; 924 #endif 925 926 void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host, 927 u32 max_clk, u32 min_clk) 928 { 929 cfg->name = host->name; 930 #ifndef CONFIG_DM_MMC 931 cfg->ops = &dwmci_ops; 932 #endif 933 cfg->f_min = min_clk; 934 cfg->f_max = max_clk; 935 936 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 937 938 cfg->host_caps = host->caps; 939 940 switch (host->buswidth) { 941 case 8: 942 cfg->host_caps |= MMC_MODE_8BIT | MMC_MODE_4BIT; 943 break; 944 case 4: 945 cfg->host_caps |= MMC_MODE_4BIT; 946 cfg->host_caps &= ~MMC_MODE_8BIT; 947 break; 948 case 1: 949 cfg->host_caps &= ~MMC_MODE_4BIT; 950 cfg->host_caps &= ~MMC_MODE_8BIT; 951 break; 952 default: 953 printf("Unsupported bus width: %d\n", host->buswidth); 954 break; 955 } 956 cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz; 957 958 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 959 } 960 961 #ifdef CONFIG_BLK 962 int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg) 963 { 964 return mmc_bind(dev, mmc, cfg); 965 } 966 #else 967 int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk) 968 { 969 dwmci_setup_cfg(&host->cfg, host, max_clk, min_clk); 970 971 host->mmc = mmc_create(&host->cfg, host); 972 if (host->mmc == NULL) 973 return -1; 974 975 return 0; 976 } 977 #endif 978