1 /* 2 * (C) Copyright 2012 SAMSUNG Electronics 3 * Jaehoon Chung <jh80.chung@samsung.com> 4 * Rajeshawari Shinde <rajeshwari.s@samsung.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <bouncebuf.h> 10 #include <common.h> 11 #include <errno.h> 12 #include <malloc.h> 13 #include <memalign.h> 14 #include <mmc.h> 15 #include <dwmmc.h> 16 17 #define PAGE_SIZE 4096 18 19 /* 20 * Currently it supports read/write up to 8*8*4 Bytes per 21 * stride as a burst mode. Please note that if you change 22 * MAX_STRIDE, you should also update dwmci_memcpy_fromio 23 * to augment the groups of {ldm, stm}. 24 */ 25 #define MAX_STRIDE 64 26 #if CONFIG_ARM && CONFIG_CPU_V7 27 void noinline dwmci_memcpy_fromio(void *buffer, void *fifo_addr) 28 { 29 __asm__ __volatile__ ( 30 "push {r2, r3, r4, r5, r6, r7, r8, r9}\n" 31 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 32 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 33 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 34 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 35 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 36 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 37 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 38 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 39 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 40 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 41 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 42 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 43 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 44 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 45 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 46 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 47 "pop {r2, r3, r4, r5, r6,r7,r8,r9}\n" 48 :::"memory" 49 ); 50 } 51 52 void noinline dwmci_memcpy_toio(void *buffer, void *fifo_addr) 53 { 54 __asm__ __volatile__ ( 55 "push {r2, r3, r4, r5, r6, r7, r8, r9}\n" 56 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 57 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 58 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 59 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 60 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 61 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 62 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 63 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 64 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 65 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 66 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 67 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 68 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 69 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 70 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 71 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 72 "pop {r2, r3, r4, r5, r6,r7,r8,r9}\n" 73 :::"memory" 74 ); 75 } 76 #else 77 void dwmci_memcpy_fromio(void *buffer, void *fifo_addr) {}; 78 void dwmci_memcpy_toio(void *buffer, void *fifo_addr) {}; 79 #endif 80 static int dwmci_wait_reset(struct dwmci_host *host, u32 value) 81 { 82 unsigned long timeout = 1000; 83 u32 ctrl; 84 85 dwmci_writel(host, DWMCI_CTRL, value); 86 87 while (timeout--) { 88 ctrl = dwmci_readl(host, DWMCI_CTRL); 89 if (!(ctrl & DWMCI_RESET_ALL)) 90 return 1; 91 } 92 return 0; 93 } 94 95 static void dwmci_set_idma_desc(struct dwmci_idmac *idmac, 96 u32 desc0, u32 desc1, u32 desc2) 97 { 98 struct dwmci_idmac *desc = idmac; 99 100 desc->flags = desc0; 101 desc->cnt = desc1; 102 desc->addr = desc2; 103 desc->next_addr = (ulong)desc + sizeof(struct dwmci_idmac); 104 } 105 106 static void dwmci_prepare_data(struct dwmci_host *host, 107 struct mmc_data *data, 108 struct dwmci_idmac *cur_idmac, 109 void *bounce_buffer) 110 { 111 unsigned long ctrl; 112 unsigned int i = 0, flags, cnt, blk_cnt; 113 ulong data_start, data_end; 114 115 116 blk_cnt = data->blocks; 117 118 dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET); 119 120 data_start = (ulong)cur_idmac; 121 dwmci_writel(host, DWMCI_DBADDR, (ulong)cur_idmac); 122 123 do { 124 flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ; 125 flags |= (i == 0) ? DWMCI_IDMAC_FS : 0; 126 if (blk_cnt <= 8) { 127 flags |= DWMCI_IDMAC_LD; 128 cnt = data->blocksize * blk_cnt; 129 } else 130 cnt = data->blocksize * 8; 131 132 dwmci_set_idma_desc(cur_idmac, flags, cnt, 133 (ulong)bounce_buffer + (i * PAGE_SIZE)); 134 135 if (blk_cnt <= 8) 136 break; 137 blk_cnt -= 8; 138 cur_idmac++; 139 i++; 140 } while(1); 141 142 data_end = (ulong)cur_idmac; 143 flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN); 144 145 ctrl = dwmci_readl(host, DWMCI_CTRL); 146 ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN; 147 dwmci_writel(host, DWMCI_CTRL, ctrl); 148 149 ctrl = dwmci_readl(host, DWMCI_BMOD); 150 ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN; 151 dwmci_writel(host, DWMCI_BMOD, ctrl); 152 153 dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize); 154 dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks); 155 } 156 157 static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data) 158 { 159 int ret = 0; 160 u32 timeout = 240000; 161 u32 status, ctrl, mask, size, i, len = 0; 162 u32 *buf = NULL; 163 ulong start = get_timer(0); 164 u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >> 165 RX_WMARK_SHIFT) + 1) * 2; 166 bool stride; 167 168 size = data->blocksize * data->blocks / 4; 169 /* Still use legacy PIO mode if size < 512(128 * 4) Bytes */ 170 stride = host->stride_pio && size > 128; 171 if (data->flags == MMC_DATA_READ) 172 buf = (unsigned int *)data->dest; 173 else 174 buf = (unsigned int *)data->src; 175 176 for (;;) { 177 mask = dwmci_readl(host, DWMCI_RINTSTS); 178 /* Error during data transfer. */ 179 if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) { 180 debug("%s: DATA ERROR!\n", __func__); 181 182 dwmci_wait_reset(host, DWMCI_RESET_ALL); 183 dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT | 184 DWMCI_CMD_UPD_CLK | DWMCI_CMD_START); 185 186 do { 187 status = dwmci_readl(host, DWMCI_CMD); 188 if (timeout-- < 0) 189 ret = -ETIMEDOUT; 190 } while (status & DWMCI_CMD_START); 191 192 if (!host->fifo_mode) { 193 ctrl = dwmci_readl(host, DWMCI_BMOD); 194 ctrl |= DWMCI_BMOD_IDMAC_RESET; 195 dwmci_writel(host, DWMCI_BMOD, ctrl); 196 } 197 198 ret = -EINVAL; 199 break; 200 } 201 202 if (host->fifo_mode && size) { 203 len = 0; 204 if (data->flags == MMC_DATA_READ && 205 (mask & DWMCI_INTMSK_RXDR)) { 206 while (size) { 207 len = dwmci_readl(host, DWMCI_STATUS); 208 len = (len >> DWMCI_FIFO_SHIFT) & 209 DWMCI_FIFO_MASK; 210 len = min(size, len); 211 if (!stride) { 212 /* Legacy pio mode */ 213 for (i = 0; i < len; i++) 214 *buf++ = dwmci_readl(host, DWMCI_DATA); 215 goto read_again; 216 } 217 218 /* dwmci_memcpy_fromio now bursts 256 Bytes once */ 219 if (len < MAX_STRIDE) 220 continue; 221 222 for (i = 0; i < len / MAX_STRIDE; i++) { 223 dwmci_memcpy_fromio(buf, host->ioaddr + DWMCI_DATA); 224 buf += MAX_STRIDE; 225 } 226 227 len = i * MAX_STRIDE; 228 read_again: 229 size = size > len ? (size - len) : 0; 230 } 231 dwmci_writel(host, DWMCI_RINTSTS, 232 DWMCI_INTMSK_RXDR); 233 } else if (data->flags == MMC_DATA_WRITE && 234 (mask & DWMCI_INTMSK_TXDR)) { 235 while (size) { 236 len = dwmci_readl(host, DWMCI_STATUS); 237 len = fifo_depth - ((len >> 238 DWMCI_FIFO_SHIFT) & 239 DWMCI_FIFO_MASK); 240 len = min(size, len); 241 if (!stride) { 242 for (i = 0; i < len; i++) 243 dwmci_writel(host, DWMCI_DATA, 244 *buf++); 245 goto write_again; 246 } 247 /* dwmci_memcpy_toio now bursts 256 Bytes once */ 248 if (len < MAX_STRIDE) 249 continue; 250 251 for (i = 0; i < len / MAX_STRIDE; i++) { 252 dwmci_memcpy_toio(buf, host->ioaddr + DWMCI_DATA); 253 buf += MAX_STRIDE; 254 } 255 256 len = i * MAX_STRIDE; 257 write_again: 258 size = size > len ? (size - len) : 0; 259 } 260 dwmci_writel(host, DWMCI_RINTSTS, 261 DWMCI_INTMSK_TXDR); 262 } 263 } 264 265 /* Data arrived correctly. */ 266 if (mask & DWMCI_INTMSK_DTO) { 267 ret = 0; 268 break; 269 } 270 271 /* Check for timeout. */ 272 if (get_timer(start) > timeout) { 273 debug("%s: Timeout waiting for data!\n", 274 __func__); 275 ret = -ETIMEDOUT; 276 break; 277 } 278 } 279 280 dwmci_writel(host, DWMCI_RINTSTS, mask); 281 282 return ret; 283 } 284 285 static int dwmci_set_transfer_mode(struct dwmci_host *host, 286 struct mmc_data *data) 287 { 288 unsigned long mode; 289 290 mode = DWMCI_CMD_DATA_EXP; 291 if (data->flags & MMC_DATA_WRITE) 292 mode |= DWMCI_CMD_RW; 293 294 return mode; 295 } 296 297 #ifdef CONFIG_DM_MMC 298 static int dwmci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, 299 struct mmc_data *data) 300 { 301 struct mmc *mmc = mmc_get_mmc_dev(dev); 302 #else 303 static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 304 struct mmc_data *data) 305 { 306 #endif 307 struct dwmci_host *host = mmc->priv; 308 ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac, 309 data ? DIV_ROUND_UP(data->blocks, 8) : 0); 310 int ret = 0, flags = 0, i; 311 unsigned int timeout = 500; 312 u32 retry = 100000; 313 u32 mask, ctrl; 314 ulong start = get_timer(0); 315 struct bounce_buffer bbstate; 316 317 while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) { 318 if (get_timer(start) > timeout) { 319 debug("%s: Timeout on data busy\n", __func__); 320 return -ETIMEDOUT; 321 } 322 } 323 324 dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL); 325 326 if (data) { 327 if (host->fifo_mode) { 328 dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize); 329 dwmci_writel(host, DWMCI_BYTCNT, 330 data->blocksize * data->blocks); 331 dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET); 332 } else { 333 if (data->flags == MMC_DATA_READ) { 334 bounce_buffer_start(&bbstate, (void*)data->dest, 335 data->blocksize * 336 data->blocks, GEN_BB_WRITE); 337 } else { 338 bounce_buffer_start(&bbstate, (void*)data->src, 339 data->blocksize * 340 data->blocks, GEN_BB_READ); 341 } 342 dwmci_prepare_data(host, data, cur_idmac, 343 bbstate.bounce_buffer); 344 } 345 } 346 347 dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg); 348 349 if (data) 350 flags = dwmci_set_transfer_mode(host, data); 351 352 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) 353 return -1; 354 355 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 356 flags |= DWMCI_CMD_ABORT_STOP; 357 else 358 flags |= DWMCI_CMD_PRV_DAT_WAIT; 359 360 if (cmd->resp_type & MMC_RSP_PRESENT) { 361 flags |= DWMCI_CMD_RESP_EXP; 362 if (cmd->resp_type & MMC_RSP_136) 363 flags |= DWMCI_CMD_RESP_LENGTH; 364 } 365 366 if (cmd->resp_type & MMC_RSP_CRC) 367 flags |= DWMCI_CMD_CHECK_CRC; 368 369 flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG); 370 371 debug("Sending CMD%d\n",cmd->cmdidx); 372 373 dwmci_writel(host, DWMCI_CMD, flags); 374 375 for (i = 0; i < retry; i++) { 376 mask = dwmci_readl(host, DWMCI_RINTSTS); 377 if (mask & DWMCI_INTMSK_CDONE) { 378 if (!data) 379 dwmci_writel(host, DWMCI_RINTSTS, mask); 380 break; 381 } 382 } 383 384 if (i == retry) { 385 debug("%s: Timeout.\n", __func__); 386 return -ETIMEDOUT; 387 } 388 389 if (mask & DWMCI_INTMSK_RTO) { 390 /* 391 * Timeout here is not necessarily fatal. (e)MMC cards 392 * will splat here when they receive CMD55 as they do 393 * not support this command and that is exactly the way 394 * to tell them apart from SD cards. Thus, this output 395 * below shall be debug(). eMMC cards also do not favor 396 * CMD8, please keep that in mind. 397 */ 398 debug("%s: Response Timeout.\n", __func__); 399 return -ETIMEDOUT; 400 } else if (mask & DWMCI_INTMSK_RE) { 401 debug("%s: Response Error.\n", __func__); 402 return -EIO; 403 } 404 405 406 if (cmd->resp_type & MMC_RSP_PRESENT) { 407 if (cmd->resp_type & MMC_RSP_136) { 408 cmd->response[0] = dwmci_readl(host, DWMCI_RESP3); 409 cmd->response[1] = dwmci_readl(host, DWMCI_RESP2); 410 cmd->response[2] = dwmci_readl(host, DWMCI_RESP1); 411 cmd->response[3] = dwmci_readl(host, DWMCI_RESP0); 412 } else { 413 cmd->response[0] = dwmci_readl(host, DWMCI_RESP0); 414 } 415 } 416 417 if (data) { 418 ret = dwmci_data_transfer(host, data); 419 420 /* only dma mode need it */ 421 if (!host->fifo_mode) { 422 ctrl = dwmci_readl(host, DWMCI_CTRL); 423 ctrl &= ~(DWMCI_DMA_EN); 424 dwmci_writel(host, DWMCI_CTRL, ctrl); 425 bounce_buffer_stop(&bbstate); 426 } 427 } 428 429 udelay(100); 430 431 return ret; 432 } 433 434 static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) 435 { 436 u32 div, status; 437 int timeout = 10000; 438 unsigned long sclk; 439 440 if (freq == 0) 441 return 0; 442 /* 443 * If host->get_mmc_clk isn't defined, 444 * then assume that host->bus_hz is source clock value. 445 * host->bus_hz should be set by user. 446 */ 447 if (host->get_mmc_clk) 448 sclk = host->get_mmc_clk(host, freq); 449 else if (host->bus_hz) 450 sclk = host->bus_hz; 451 else { 452 debug("%s: Didn't get source clock value.\n", __func__); 453 return -EINVAL; 454 } 455 456 if (sclk == freq) 457 div = 0; /* bypass mode */ 458 else 459 div = DIV_ROUND_UP(sclk, 2 * freq); 460 461 dwmci_writel(host, DWMCI_CLKENA, 0); 462 dwmci_writel(host, DWMCI_CLKSRC, 0); 463 464 dwmci_writel(host, DWMCI_CLKDIV, div); 465 dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT | 466 DWMCI_CMD_UPD_CLK | DWMCI_CMD_START); 467 468 do { 469 status = dwmci_readl(host, DWMCI_CMD); 470 if (timeout-- < 0) { 471 debug("%s: Timeout!\n", __func__); 472 return -ETIMEDOUT; 473 } 474 } while (status & DWMCI_CMD_START); 475 476 dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE | 477 DWMCI_CLKEN_LOW_PWR); 478 479 dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT | 480 DWMCI_CMD_UPD_CLK | DWMCI_CMD_START); 481 482 timeout = 10000; 483 do { 484 status = dwmci_readl(host, DWMCI_CMD); 485 if (timeout-- < 0) { 486 debug("%s: Timeout!\n", __func__); 487 return -ETIMEDOUT; 488 } 489 } while (status & DWMCI_CMD_START); 490 491 host->clock = freq; 492 493 return 0; 494 } 495 496 #ifdef CONFIG_DM_MMC 497 static bool dwmci_card_busy(struct udevice *dev) 498 { 499 struct mmc *mmc = mmc_get_mmc_dev(dev); 500 #else 501 static bool dwmci_card_busy(struct mmc *mmc) 502 { 503 #endif 504 u32 status; 505 struct dwmci_host *host = (struct dwmci_host *)mmc->priv; 506 507 /* 508 * Check the busy bit which is low when DAT[3:0] 509 * (the data lines) are 0000 510 */ 511 status = dwmci_readl(host, DWMCI_STATUS); 512 513 return !!(status & DWMCI_BUSY); 514 } 515 516 #ifdef CONFIG_DM_MMC 517 static int dwmci_execute_tuning(struct udevice *dev, u32 opcode) 518 { 519 struct mmc *mmc = mmc_get_mmc_dev(dev); 520 #else 521 static int dwmci_execute_tuning(struct mmc *mmc, u32 opcode) 522 { 523 #endif 524 struct dwmci_host *host = (struct dwmci_host *)mmc->priv; 525 526 if (!host->execute_tuning) 527 return -EIO; 528 529 return host->execute_tuning(host, opcode); 530 } 531 532 #ifdef CONFIG_DM_MMC 533 static int dwmci_set_ios(struct udevice *dev) 534 { 535 struct mmc *mmc = mmc_get_mmc_dev(dev); 536 #else 537 static int dwmci_set_ios(struct mmc *mmc) 538 { 539 #endif 540 struct dwmci_host *host = (struct dwmci_host *)mmc->priv; 541 u32 ctype, regs; 542 543 debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock); 544 545 dwmci_setup_bus(host, mmc->clock); 546 switch (mmc->bus_width) { 547 case 8: 548 ctype = DWMCI_CTYPE_8BIT; 549 break; 550 case 4: 551 ctype = DWMCI_CTYPE_4BIT; 552 break; 553 default: 554 ctype = DWMCI_CTYPE_1BIT; 555 break; 556 } 557 558 dwmci_writel(host, DWMCI_CTYPE, ctype); 559 560 regs = dwmci_readl(host, DWMCI_UHS_REG); 561 if (mmc_card_ddr(mmc)) 562 regs |= DWMCI_DDR_MODE; 563 else 564 regs &= ~DWMCI_DDR_MODE; 565 566 dwmci_writel(host, DWMCI_UHS_REG, regs); 567 568 if (host->clksel) 569 host->clksel(host); 570 571 return 0; 572 } 573 574 static int dwmci_init(struct mmc *mmc) 575 { 576 struct dwmci_host *host = mmc->priv; 577 uint32_t use_dma; 578 579 if (host->board_init) 580 host->board_init(host); 581 582 dwmci_writel(host, DWMCI_PWREN, 1); 583 584 if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) { 585 debug("%s[%d] Fail-reset!!\n", __func__, __LINE__); 586 return -EIO; 587 } 588 589 use_dma = SDMMC_GET_TRANS_MODE(dwmci_readl(host, DWMCI_HCON)); 590 if (use_dma == DMA_INTERFACE_IDMA) { 591 host->fifo_mode = 0; 592 } else { 593 host->fifo_mode = 1; 594 } 595 596 /* Enumerate at 400KHz */ 597 dwmci_setup_bus(host, mmc->cfg->f_min); 598 599 dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF); 600 dwmci_writel(host, DWMCI_INTMASK, 0); 601 602 dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF); 603 604 dwmci_writel(host, DWMCI_IDINTEN, 0); 605 dwmci_writel(host, DWMCI_BMOD, 1); 606 607 if (!host->fifoth_val) { 608 uint32_t fifo_size; 609 610 fifo_size = dwmci_readl(host, DWMCI_FIFOTH); 611 fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1; 612 host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) | 613 TX_WMARK(fifo_size / 2); 614 } 615 dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val); 616 617 dwmci_writel(host, DWMCI_CLKENA, 0); 618 dwmci_writel(host, DWMCI_CLKSRC, 0); 619 620 return 0; 621 } 622 623 #ifdef CONFIG_DM_MMC 624 int dwmci_probe(struct udevice *dev) 625 { 626 struct mmc *mmc = mmc_get_mmc_dev(dev); 627 628 return dwmci_init(mmc); 629 } 630 631 const struct dm_mmc_ops dm_dwmci_ops = { 632 .card_busy = dwmci_card_busy, 633 .send_cmd = dwmci_send_cmd, 634 .set_ios = dwmci_set_ios, 635 .execute_tuning = dwmci_execute_tuning, 636 }; 637 638 #else 639 static const struct mmc_ops dwmci_ops = { 640 .card_busy = dwmci_card_busy, 641 .send_cmd = dwmci_send_cmd, 642 .set_ios = dwmci_set_ios, 643 .init = dwmci_init, 644 .execute_tuning = dwmci_execute_tuning, 645 }; 646 #endif 647 648 void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host, 649 u32 max_clk, u32 min_clk) 650 { 651 cfg->name = host->name; 652 #ifndef CONFIG_DM_MMC 653 cfg->ops = &dwmci_ops; 654 #endif 655 cfg->f_min = min_clk; 656 cfg->f_max = max_clk; 657 658 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 659 660 cfg->host_caps = host->caps; 661 662 if (host->buswidth == 8) { 663 cfg->host_caps |= MMC_MODE_8BIT | MMC_MODE_4BIT; 664 } else { 665 cfg->host_caps |= MMC_MODE_4BIT; 666 cfg->host_caps &= ~MMC_MODE_8BIT; 667 } 668 cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz; 669 670 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 671 } 672 673 #ifdef CONFIG_BLK 674 int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg) 675 { 676 return mmc_bind(dev, mmc, cfg); 677 } 678 #else 679 int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk) 680 { 681 dwmci_setup_cfg(&host->cfg, host, max_clk, min_clk); 682 683 host->mmc = mmc_create(&host->cfg, host); 684 if (host->mmc == NULL) 685 return -1; 686 687 return 0; 688 } 689 #endif 690