1 /* 2 * (C) Copyright 2012 SAMSUNG Electronics 3 * Jaehoon Chung <jh80.chung@samsung.com> 4 * Rajeshawari Shinde <rajeshwari.s@samsung.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <bouncebuf.h> 11 #include <errno.h> 12 #include <malloc.h> 13 #include <memalign.h> 14 #include <mmc.h> 15 #include <dwmmc.h> 16 #ifdef CONFIG_DM_GPIO 17 #include <asm/gpio.h> 18 #include <asm-generic/gpio.h> 19 #endif 20 21 #define PAGE_SIZE 4096 22 23 /* 24 * Currently it supports read/write up to 8*8*4 Bytes per 25 * stride as a burst mode. Please note that if you change 26 * MAX_STRIDE, you should also update dwmci_memcpy_fromio 27 * to augment the groups of {ldm, stm}. 28 */ 29 #define MAX_STRIDE 64 30 #if CONFIG_ARM && CONFIG_CPU_V7 31 void noinline dwmci_memcpy_fromio(void *buffer, void *fifo_addr) 32 { 33 __asm__ __volatile__ ( 34 "push {r2, r3, r4, r5, r6, r7, r8, r9}\n" 35 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 36 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 37 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 38 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 39 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 40 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 41 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 42 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 43 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 44 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 45 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 46 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 47 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 48 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 49 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 50 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 51 "pop {r2, r3, r4, r5, r6,r7,r8,r9}\n" 52 :::"memory" 53 ); 54 } 55 56 void noinline dwmci_memcpy_toio(void *buffer, void *fifo_addr) 57 { 58 __asm__ __volatile__ ( 59 "push {r2, r3, r4, r5, r6, r7, r8, r9}\n" 60 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 61 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 62 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 63 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 64 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 65 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 66 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 67 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 68 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 69 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 70 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 71 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 72 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 73 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 74 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 75 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 76 "pop {r2, r3, r4, r5, r6,r7,r8,r9}\n" 77 :::"memory" 78 ); 79 } 80 #else 81 void dwmci_memcpy_fromio(void *buffer, void *fifo_addr) {}; 82 void dwmci_memcpy_toio(void *buffer, void *fifo_addr) {}; 83 #endif 84 static int dwmci_wait_reset(struct dwmci_host *host, u32 value) 85 { 86 unsigned long timeout = 1000; 87 u32 ctrl; 88 89 dwmci_writel(host, DWMCI_CTRL, value); 90 91 while (timeout--) { 92 ctrl = dwmci_readl(host, DWMCI_CTRL); 93 if (!(ctrl & DWMCI_RESET_ALL)) 94 return 1; 95 } 96 return 0; 97 } 98 99 static void dwmci_set_idma_desc(struct dwmci_idmac *idmac, 100 u32 desc0, u32 desc1, u32 desc2) 101 { 102 struct dwmci_idmac *desc = idmac; 103 104 desc->flags = desc0; 105 desc->cnt = desc1; 106 desc->addr = desc2; 107 desc->next_addr = (ulong)desc + sizeof(struct dwmci_idmac); 108 } 109 110 static void dwmci_prepare_data(struct dwmci_host *host, 111 struct mmc_data *data, 112 struct dwmci_idmac *cur_idmac, 113 void *bounce_buffer) 114 { 115 unsigned long ctrl; 116 unsigned int i = 0, flags, cnt, blk_cnt; 117 ulong data_start, data_end; 118 119 120 blk_cnt = data->blocks; 121 122 dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET); 123 124 data_start = (ulong)cur_idmac; 125 dwmci_writel(host, DWMCI_DBADDR, (ulong)cur_idmac); 126 127 do { 128 flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ; 129 flags |= (i == 0) ? DWMCI_IDMAC_FS : 0; 130 if (blk_cnt <= 8) { 131 flags |= DWMCI_IDMAC_LD; 132 cnt = data->blocksize * blk_cnt; 133 } else 134 cnt = data->blocksize * 8; 135 136 dwmci_set_idma_desc(cur_idmac, flags, cnt, 137 (ulong)bounce_buffer + (i * PAGE_SIZE)); 138 139 if (blk_cnt <= 8) 140 break; 141 blk_cnt -= 8; 142 cur_idmac++; 143 i++; 144 } while(1); 145 146 data_end = (ulong)cur_idmac; 147 flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN); 148 149 ctrl = dwmci_readl(host, DWMCI_CTRL); 150 ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN; 151 dwmci_writel(host, DWMCI_CTRL, ctrl); 152 153 ctrl = dwmci_readl(host, DWMCI_BMOD); 154 ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN; 155 dwmci_writel(host, DWMCI_BMOD, ctrl); 156 157 dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize); 158 dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks); 159 } 160 161 static unsigned int dwmci_get_timeout(struct mmc *mmc, const unsigned int size) 162 { 163 unsigned int timeout; 164 165 timeout = size * 8; /* counting in bits */ 166 timeout *= 10; /* wait 10 times as long */ 167 timeout /= mmc->clock; 168 timeout /= mmc->bus_width; 169 timeout *= 1000; /* counting in msec */ 170 timeout = (timeout < 10000) ? 10000 : timeout; 171 172 return timeout; 173 } 174 175 static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data) 176 { 177 int ret = 0; 178 int reset_timeout = 100; 179 u32 timeout, status, ctrl, mask, size, i, len = 0; 180 u32 *buf = NULL; 181 ulong start = get_timer(0); 182 u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >> 183 RX_WMARK_SHIFT) + 1) * 2; 184 bool stride; 185 186 size = data->blocksize * data->blocks; 187 /* Still use legacy PIO mode if size < 512(128 * 4) Bytes */ 188 stride = host->stride_pio && size > 128; 189 if (data->flags == MMC_DATA_READ) 190 buf = (unsigned int *)data->dest; 191 else 192 buf = (unsigned int *)data->src; 193 194 timeout = dwmci_get_timeout(host->mmc, size); 195 size /= 4; 196 197 for (;;) { 198 mask = dwmci_readl(host, DWMCI_RINTSTS); 199 /* Error during data transfer. */ 200 if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) { 201 debug("%s: DATA ERROR!\n", __func__); 202 dwmci_wait_reset(host, DWMCI_RESET_ALL); 203 dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT | 204 DWMCI_CMD_UPD_CLK | DWMCI_CMD_START); 205 206 do { 207 status = dwmci_readl(host, DWMCI_CMD); 208 if (reset_timeout-- < 0) 209 break; 210 udelay(100); 211 } while (status & DWMCI_CMD_START); 212 213 if (!host->fifo_mode) { 214 ctrl = dwmci_readl(host, DWMCI_BMOD); 215 ctrl |= DWMCI_BMOD_IDMAC_RESET; 216 dwmci_writel(host, DWMCI_BMOD, ctrl); 217 } 218 219 ret = -EINVAL; 220 break; 221 } 222 223 if (host->fifo_mode && size) { 224 len = 0; 225 if (data->flags == MMC_DATA_READ && 226 (mask & DWMCI_INTMSK_RXDR)) { 227 while (size) { 228 len = dwmci_readl(host, DWMCI_STATUS); 229 len = (len >> DWMCI_FIFO_SHIFT) & 230 DWMCI_FIFO_MASK; 231 len = min(size, len); 232 if (!stride) { 233 /* Legacy pio mode */ 234 for (i = 0; i < len; i++) 235 *buf++ = dwmci_readl(host, DWMCI_DATA); 236 goto read_again; 237 } 238 239 /* dwmci_memcpy_fromio now bursts 256 Bytes once */ 240 if (len < MAX_STRIDE) 241 continue; 242 243 for (i = 0; i < len / MAX_STRIDE; i++) { 244 dwmci_memcpy_fromio(buf, host->ioaddr + DWMCI_DATA); 245 buf += MAX_STRIDE; 246 } 247 248 len = i * MAX_STRIDE; 249 read_again: 250 size = size > len ? (size - len) : 0; 251 } 252 dwmci_writel(host, DWMCI_RINTSTS, 253 DWMCI_INTMSK_RXDR); 254 } else if (data->flags == MMC_DATA_WRITE && 255 (mask & DWMCI_INTMSK_TXDR)) { 256 while (size) { 257 len = dwmci_readl(host, DWMCI_STATUS); 258 len = fifo_depth - ((len >> 259 DWMCI_FIFO_SHIFT) & 260 DWMCI_FIFO_MASK); 261 len = min(size, len); 262 if (!stride) { 263 for (i = 0; i < len; i++) 264 dwmci_writel(host, DWMCI_DATA, 265 *buf++); 266 goto write_again; 267 } 268 /* dwmci_memcpy_toio now bursts 256 Bytes once */ 269 if (len < MAX_STRIDE) 270 continue; 271 272 for (i = 0; i < len / MAX_STRIDE; i++) { 273 dwmci_memcpy_toio(buf, host->ioaddr + DWMCI_DATA); 274 buf += MAX_STRIDE; 275 } 276 277 len = i * MAX_STRIDE; 278 write_again: 279 size = size > len ? (size - len) : 0; 280 } 281 dwmci_writel(host, DWMCI_RINTSTS, 282 DWMCI_INTMSK_TXDR); 283 } 284 } 285 286 /* Data arrived correctly. */ 287 if (mask & DWMCI_INTMSK_DTO) { 288 ret = 0; 289 break; 290 } 291 292 /* Check for timeout. */ 293 if (get_timer(start) > timeout) { 294 debug("%s: Timeout waiting for data!\n", 295 __func__); 296 ret = -ETIMEDOUT; 297 break; 298 } 299 } 300 301 dwmci_writel(host, DWMCI_RINTSTS, mask); 302 303 return ret; 304 } 305 306 static int dwmci_set_transfer_mode(struct dwmci_host *host, 307 struct mmc_data *data) 308 { 309 unsigned long mode; 310 311 mode = DWMCI_CMD_DATA_EXP; 312 if (data->flags & MMC_DATA_WRITE) 313 mode |= DWMCI_CMD_RW; 314 315 return mode; 316 } 317 318 #ifdef CONFIG_DM_MMC 319 static int dwmci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, 320 struct mmc_data *data) 321 { 322 struct mmc *mmc = mmc_get_mmc_dev(dev); 323 #else 324 static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 325 struct mmc_data *data) 326 { 327 #endif 328 struct dwmci_host *host = mmc->priv; 329 ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac, 330 data ? DIV_ROUND_UP(data->blocks, 8) : 0); 331 int ret = 0, flags = 0, i; 332 unsigned int timeout = 500; 333 u32 retry = 100000; 334 u32 mask, ctrl; 335 ulong start = get_timer(0); 336 struct bounce_buffer bbstate; 337 338 while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) { 339 if (get_timer(start) > timeout) { 340 debug("%s: Timeout on data busy\n", __func__); 341 return -ETIMEDOUT; 342 } 343 } 344 345 dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL); 346 347 if (data) { 348 if (host->fifo_mode) { 349 dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize); 350 dwmci_writel(host, DWMCI_BYTCNT, 351 data->blocksize * data->blocks); 352 dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET); 353 } else { 354 if (data->flags == MMC_DATA_READ) { 355 bounce_buffer_start(&bbstate, (void*)data->dest, 356 data->blocksize * 357 data->blocks, GEN_BB_WRITE); 358 } else { 359 bounce_buffer_start(&bbstate, (void*)data->src, 360 data->blocksize * 361 data->blocks, GEN_BB_READ); 362 } 363 dwmci_prepare_data(host, data, cur_idmac, 364 bbstate.bounce_buffer); 365 } 366 } 367 368 dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg); 369 370 if (data) 371 flags = dwmci_set_transfer_mode(host, data); 372 373 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) 374 return -1; 375 376 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 377 flags |= DWMCI_CMD_ABORT_STOP; 378 else 379 flags |= DWMCI_CMD_PRV_DAT_WAIT; 380 381 if (cmd->resp_type & MMC_RSP_PRESENT) { 382 flags |= DWMCI_CMD_RESP_EXP; 383 if (cmd->resp_type & MMC_RSP_136) 384 flags |= DWMCI_CMD_RESP_LENGTH; 385 } 386 387 if (cmd->resp_type & MMC_RSP_CRC) 388 flags |= DWMCI_CMD_CHECK_CRC; 389 390 flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG); 391 392 debug("Sending CMD%d\n",cmd->cmdidx); 393 394 dwmci_writel(host, DWMCI_CMD, flags); 395 396 for (i = 0; i < retry; i++) { 397 mask = dwmci_readl(host, DWMCI_RINTSTS); 398 if (mask & DWMCI_INTMSK_CDONE) { 399 if (!data) 400 dwmci_writel(host, DWMCI_RINTSTS, mask); 401 break; 402 } 403 } 404 405 if (i == retry) { 406 debug("%s: Timeout.\n", __func__); 407 return -ETIMEDOUT; 408 } 409 410 if (mask & DWMCI_INTMSK_RTO) { 411 /* 412 * Timeout here is not necessarily fatal. (e)MMC cards 413 * will splat here when they receive CMD55 as they do 414 * not support this command and that is exactly the way 415 * to tell them apart from SD cards. Thus, this output 416 * below shall be debug(). eMMC cards also do not favor 417 * CMD8, please keep that in mind. 418 */ 419 debug("%s: Response Timeout.\n", __func__); 420 return -ETIMEDOUT; 421 } else if (mask & DWMCI_INTMSK_RE) { 422 debug("%s: Response Error.\n", __func__); 423 return -EIO; 424 } 425 426 427 if (cmd->resp_type & MMC_RSP_PRESENT) { 428 if (cmd->resp_type & MMC_RSP_136) { 429 cmd->response[0] = dwmci_readl(host, DWMCI_RESP3); 430 cmd->response[1] = dwmci_readl(host, DWMCI_RESP2); 431 cmd->response[2] = dwmci_readl(host, DWMCI_RESP1); 432 cmd->response[3] = dwmci_readl(host, DWMCI_RESP0); 433 } else { 434 cmd->response[0] = dwmci_readl(host, DWMCI_RESP0); 435 } 436 } 437 438 if (data) { 439 ret = dwmci_data_transfer(host, data); 440 441 /* only dma mode need it */ 442 if (!host->fifo_mode) { 443 ctrl = dwmci_readl(host, DWMCI_CTRL); 444 ctrl &= ~(DWMCI_DMA_EN); 445 dwmci_writel(host, DWMCI_CTRL, ctrl); 446 bounce_buffer_stop(&bbstate); 447 } 448 } 449 450 return ret; 451 } 452 453 #ifdef CONFIG_SPL_BLK_READ_PREPARE 454 #ifdef CONFIG_DM_MMC 455 static int dwmci_send_cmd_prepare(struct udevice *dev, struct mmc_cmd *cmd, 456 struct mmc_data *data) 457 { 458 struct mmc *mmc = mmc_get_mmc_dev(dev); 459 #else 460 static int dwmci_send_cmd_prepare(struct mmc *mmc, struct mmc_cmd *cmd, 461 struct mmc_data *data) 462 { 463 #endif 464 struct dwmci_host *host = mmc->priv; 465 struct dwmci_idmac *cur_idmac; 466 int ret = 0, flags = 0, i; 467 unsigned int timeout = 500; 468 u32 retry = 100000; 469 u32 mask; 470 ulong start = get_timer(0); 471 struct bounce_buffer bbstate; 472 473 cur_idmac = malloc(ROUND(DIV_ROUND_UP(data->blocks, 8) * 474 sizeof(struct dwmci_idmac), 475 ARCH_DMA_MINALIGN) + ARCH_DMA_MINALIGN - 1); 476 if (!cur_idmac) 477 return -ENODATA; 478 479 while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) { 480 if (get_timer(start) > timeout) { 481 debug("%s: Timeout on data busy\n", __func__); 482 return -ETIMEDOUT; 483 } 484 } 485 486 dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL); 487 488 if (data) { 489 if (host->fifo_mode) { 490 dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize); 491 dwmci_writel(host, DWMCI_BYTCNT, 492 data->blocksize * data->blocks); 493 dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET); 494 } else { 495 if (data->flags == MMC_DATA_READ) { 496 bounce_buffer_start(&bbstate, (void *)data->dest, 497 data->blocksize * 498 data->blocks, GEN_BB_WRITE); 499 } else { 500 bounce_buffer_start(&bbstate, (void *)data->src, 501 data->blocksize * 502 data->blocks, GEN_BB_READ); 503 } 504 dwmci_prepare_data(host, data, cur_idmac, 505 bbstate.bounce_buffer); 506 } 507 } 508 509 dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg); 510 511 if (data) 512 flags = dwmci_set_transfer_mode(host, data); 513 514 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) 515 return -1; 516 517 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 518 flags |= DWMCI_CMD_ABORT_STOP; 519 else 520 flags |= DWMCI_CMD_PRV_DAT_WAIT; 521 522 if (cmd->resp_type & MMC_RSP_PRESENT) { 523 flags |= DWMCI_CMD_RESP_EXP; 524 if (cmd->resp_type & MMC_RSP_136) 525 flags |= DWMCI_CMD_RESP_LENGTH; 526 } 527 528 if (cmd->resp_type & MMC_RSP_CRC) 529 flags |= DWMCI_CMD_CHECK_CRC; 530 531 flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG); 532 533 debug("Sending CMD%d\n", cmd->cmdidx); 534 535 dwmci_writel(host, DWMCI_CMD, flags); 536 537 for (i = 0; i < retry; i++) { 538 mask = dwmci_readl(host, DWMCI_RINTSTS); 539 if (mask & DWMCI_INTMSK_CDONE) { 540 if (!data) 541 dwmci_writel(host, DWMCI_RINTSTS, mask); 542 break; 543 } 544 } 545 546 if (i == retry) { 547 debug("%s: Timeout.\n", __func__); 548 return -ETIMEDOUT; 549 } 550 551 if (mask & DWMCI_INTMSK_RTO) { 552 /* 553 * Timeout here is not necessarily fatal. (e)MMC cards 554 * will splat here when they receive CMD55 as they do 555 * not support this command and that is exactly the way 556 * to tell them apart from SD cards. Thus, this output 557 * below shall be debug(). eMMC cards also do not favor 558 * CMD8, please keep that in mind. 559 */ 560 debug("%s: Response Timeout.\n", __func__); 561 return -ETIMEDOUT; 562 } else if (mask & DWMCI_INTMSK_RE) { 563 debug("%s: Response Error.\n", __func__); 564 return -EIO; 565 } 566 567 if (cmd->resp_type & MMC_RSP_PRESENT) { 568 if (cmd->resp_type & MMC_RSP_136) { 569 cmd->response[0] = dwmci_readl(host, DWMCI_RESP3); 570 cmd->response[1] = dwmci_readl(host, DWMCI_RESP2); 571 cmd->response[2] = dwmci_readl(host, DWMCI_RESP1); 572 cmd->response[3] = dwmci_readl(host, DWMCI_RESP0); 573 } else { 574 cmd->response[0] = dwmci_readl(host, DWMCI_RESP0); 575 } 576 } 577 578 return ret; 579 } 580 #endif 581 582 static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) 583 { 584 u32 div, status; 585 int timeout = 10000; 586 unsigned long sclk; 587 588 if (freq == 0) 589 return 0; 590 /* 591 * If host->get_mmc_clk isn't defined, 592 * then assume that host->bus_hz is source clock value. 593 * host->bus_hz should be set by user. 594 */ 595 if (host->get_mmc_clk) 596 sclk = host->get_mmc_clk(host, freq); 597 else if (host->bus_hz) 598 sclk = host->bus_hz; 599 else { 600 debug("%s: Didn't get source clock value.\n", __func__); 601 return -EINVAL; 602 } 603 604 if (sclk == freq) 605 div = 0; /* bypass mode */ 606 else 607 div = DIV_ROUND_UP(sclk, 2 * freq); 608 609 dwmci_writel(host, DWMCI_CLKENA, 0); 610 dwmci_writel(host, DWMCI_CLKSRC, 0); 611 612 dwmci_writel(host, DWMCI_CLKDIV, div); 613 dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT | 614 DWMCI_CMD_UPD_CLK | DWMCI_CMD_START); 615 616 do { 617 status = dwmci_readl(host, DWMCI_CMD); 618 if (timeout-- < 0) { 619 debug("%s: Timeout!\n", __func__); 620 return -ETIMEDOUT; 621 } 622 } while (status & DWMCI_CMD_START); 623 624 dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE | 625 DWMCI_CLKEN_LOW_PWR); 626 627 dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT | 628 DWMCI_CMD_UPD_CLK | DWMCI_CMD_START); 629 630 timeout = 10000; 631 do { 632 status = dwmci_readl(host, DWMCI_CMD); 633 if (timeout-- < 0) { 634 debug("%s: Timeout!\n", __func__); 635 return -ETIMEDOUT; 636 } 637 } while (status & DWMCI_CMD_START); 638 639 host->clock = freq; 640 641 return 0; 642 } 643 644 #ifdef CONFIG_DM_MMC 645 static bool dwmci_card_busy(struct udevice *dev) 646 { 647 struct mmc *mmc = mmc_get_mmc_dev(dev); 648 #else 649 static bool dwmci_card_busy(struct mmc *mmc) 650 { 651 #endif 652 u32 status; 653 struct dwmci_host *host = (struct dwmci_host *)mmc->priv; 654 655 /* 656 * Check the busy bit which is low when DAT[3:0] 657 * (the data lines) are 0000 658 */ 659 status = dwmci_readl(host, DWMCI_STATUS); 660 661 return !!(status & DWMCI_BUSY); 662 } 663 664 #ifdef CONFIG_DM_MMC 665 static int dwmci_execute_tuning(struct udevice *dev, u32 opcode) 666 { 667 struct mmc *mmc = mmc_get_mmc_dev(dev); 668 #else 669 static int dwmci_execute_tuning(struct mmc *mmc, u32 opcode) 670 { 671 #endif 672 struct dwmci_host *host = (struct dwmci_host *)mmc->priv; 673 674 if (!host->execute_tuning) 675 return -EIO; 676 677 return host->execute_tuning(host, opcode); 678 } 679 680 #ifdef CONFIG_DM_MMC 681 static int dwmci_set_ios(struct udevice *dev) 682 { 683 struct mmc *mmc = mmc_get_mmc_dev(dev); 684 #else 685 static int dwmci_set_ios(struct mmc *mmc) 686 { 687 #endif 688 struct dwmci_host *host = (struct dwmci_host *)mmc->priv; 689 u32 ctype, regs; 690 691 debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock); 692 693 dwmci_setup_bus(host, mmc->clock); 694 switch (mmc->bus_width) { 695 case 8: 696 ctype = DWMCI_CTYPE_8BIT; 697 break; 698 case 4: 699 ctype = DWMCI_CTYPE_4BIT; 700 break; 701 default: 702 ctype = DWMCI_CTYPE_1BIT; 703 break; 704 } 705 706 dwmci_writel(host, DWMCI_CTYPE, ctype); 707 708 regs = dwmci_readl(host, DWMCI_UHS_REG); 709 if (mmc_card_ddr(mmc)) 710 regs |= DWMCI_DDR_MODE; 711 else 712 regs &= ~DWMCI_DDR_MODE; 713 714 dwmci_writel(host, DWMCI_UHS_REG, regs); 715 716 if (host->clksel) 717 host->clksel(host); 718 719 return 0; 720 } 721 722 static int dwmci_init(struct mmc *mmc) 723 { 724 struct dwmci_host *host = mmc->priv; 725 uint32_t use_dma; 726 uint32_t verid; 727 728 if (host->board_init) 729 host->board_init(host); 730 #ifdef CONFIG_ARCH_ROCKCHIP 731 if (host->dev_index == 0) 732 dwmci_writel(host, DWMCI_PWREN, 1); 733 else if (host->dev_index == 1) 734 dwmci_writel(host, DWMCI_PWREN, 0); 735 else 736 dwmci_writel(host, DWMCI_PWREN, 1); 737 #else 738 dwmci_writel(host, DWMCI_PWREN, 1); 739 #endif 740 741 verid = dwmci_readl(host, DWMCI_VERID) & 0x0000ffff; 742 if (verid >= DW_MMC_240A) 743 dwmci_writel(host, DWMCI_CARDTHRCTL, DWMCI_CDTHRCTRL_CONFIG); 744 745 if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) { 746 debug("%s[%d] Fail-reset!!\n", __func__, __LINE__); 747 return -EIO; 748 } 749 750 use_dma = SDMMC_GET_TRANS_MODE(dwmci_readl(host, DWMCI_HCON)); 751 if (use_dma == DMA_INTERFACE_IDMA) { 752 host->fifo_mode = 0; 753 } else { 754 host->fifo_mode = 1; 755 } 756 757 /* Enumerate at 400KHz */ 758 dwmci_setup_bus(host, mmc->cfg->f_min); 759 760 dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF); 761 dwmci_writel(host, DWMCI_INTMASK, 0); 762 763 dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF); 764 765 dwmci_writel(host, DWMCI_IDINTEN, 0); 766 dwmci_writel(host, DWMCI_BMOD, 1); 767 768 if (!host->fifoth_val) { 769 uint32_t fifo_size; 770 771 fifo_size = dwmci_readl(host, DWMCI_FIFOTH); 772 fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1; 773 host->fifoth_val = MSIZE(DWMCI_MSIZE) | 774 RX_WMARK(fifo_size / 2 - 1) | 775 TX_WMARK(fifo_size / 2); 776 } 777 dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val); 778 779 dwmci_writel(host, DWMCI_CLKENA, 0); 780 dwmci_writel(host, DWMCI_CLKSRC, 0); 781 782 return 0; 783 } 784 785 static int dwmci_get_cd(struct udevice *dev) 786 { 787 int ret = -1; 788 #ifndef CONFIG_SPL_BUILD 789 #ifdef CONFIG_DM_GPIO 790 struct gpio_desc detect; 791 792 ret = gpio_request_by_name(dev, "cd-gpios", 0, &detect, GPIOD_IS_IN); 793 if (ret) { 794 return ret; 795 } 796 797 ret = !dm_gpio_get_value(&detect); 798 #endif 799 #endif 800 return ret; 801 } 802 803 #ifdef CONFIG_DM_MMC 804 int dwmci_probe(struct udevice *dev) 805 { 806 struct mmc *mmc = mmc_get_mmc_dev(dev); 807 808 return dwmci_init(mmc); 809 } 810 811 const struct dm_mmc_ops dm_dwmci_ops = { 812 .card_busy = dwmci_card_busy, 813 .send_cmd = dwmci_send_cmd, 814 #ifdef CONFIG_SPL_BLK_READ_PREPARE 815 .send_cmd_prepare = dwmci_send_cmd_prepare, 816 #endif 817 .set_ios = dwmci_set_ios, 818 .get_cd = dwmci_get_cd, 819 .execute_tuning = dwmci_execute_tuning, 820 }; 821 822 #else 823 static const struct mmc_ops dwmci_ops = { 824 .card_busy = dwmci_card_busy, 825 .send_cmd = dwmci_send_cmd, 826 .set_ios = dwmci_set_ios, 827 .get_cd = dwmci_get_cd, 828 .init = dwmci_init, 829 .execute_tuning = dwmci_execute_tuning, 830 }; 831 #endif 832 833 void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host, 834 u32 max_clk, u32 min_clk) 835 { 836 cfg->name = host->name; 837 #ifndef CONFIG_DM_MMC 838 cfg->ops = &dwmci_ops; 839 #endif 840 cfg->f_min = min_clk; 841 cfg->f_max = max_clk; 842 843 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 844 845 cfg->host_caps = host->caps; 846 847 switch (host->buswidth) { 848 case 8: 849 cfg->host_caps |= MMC_MODE_8BIT | MMC_MODE_4BIT; 850 break; 851 case 4: 852 cfg->host_caps |= MMC_MODE_4BIT; 853 cfg->host_caps &= ~MMC_MODE_8BIT; 854 break; 855 case 1: 856 cfg->host_caps &= ~MMC_MODE_4BIT; 857 cfg->host_caps &= ~MMC_MODE_8BIT; 858 break; 859 default: 860 printf("Unsupported bus width: %d\n", host->buswidth); 861 break; 862 } 863 cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz; 864 865 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 866 } 867 868 #ifdef CONFIG_BLK 869 int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg) 870 { 871 return mmc_bind(dev, mmc, cfg); 872 } 873 #else 874 int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk) 875 { 876 dwmci_setup_cfg(&host->cfg, host, max_clk, min_clk); 877 878 host->mmc = mmc_create(&host->cfg, host); 879 if (host->mmc == NULL) 880 return -1; 881 882 return 0; 883 } 884 #endif 885