1 /* 2 * (C) Copyright 2012 SAMSUNG Electronics 3 * Jaehoon Chung <jh80.chung@samsung.com> 4 * Rajeshawari Shinde <rajeshwari.s@samsung.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <bouncebuf.h> 10 #include <common.h> 11 #include <errno.h> 12 #include <malloc.h> 13 #include <memalign.h> 14 #include <mmc.h> 15 #include <dwmmc.h> 16 #ifdef CONFIG_DM_GPIO 17 #include <asm/gpio.h> 18 #include <asm-generic/gpio.h> 19 #endif 20 21 #define PAGE_SIZE 4096 22 23 /* 24 * Currently it supports read/write up to 8*8*4 Bytes per 25 * stride as a burst mode. Please note that if you change 26 * MAX_STRIDE, you should also update dwmci_memcpy_fromio 27 * to augment the groups of {ldm, stm}. 28 */ 29 #define MAX_STRIDE 64 30 #if CONFIG_ARM && CONFIG_CPU_V7 31 void noinline dwmci_memcpy_fromio(void *buffer, void *fifo_addr) 32 { 33 __asm__ __volatile__ ( 34 "push {r2, r3, r4, r5, r6, r7, r8, r9}\n" 35 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 36 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 37 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 38 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 39 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 40 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 41 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 42 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 43 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 44 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 45 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 46 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 47 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 48 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 49 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 50 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 51 "pop {r2, r3, r4, r5, r6,r7,r8,r9}\n" 52 :::"memory" 53 ); 54 } 55 56 void noinline dwmci_memcpy_toio(void *buffer, void *fifo_addr) 57 { 58 __asm__ __volatile__ ( 59 "push {r2, r3, r4, r5, r6, r7, r8, r9}\n" 60 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 61 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 62 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 63 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 64 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 65 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 66 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 67 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 68 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 69 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 70 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 71 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 72 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 73 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 74 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 75 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 76 "pop {r2, r3, r4, r5, r6,r7,r8,r9}\n" 77 :::"memory" 78 ); 79 } 80 #else 81 void dwmci_memcpy_fromio(void *buffer, void *fifo_addr) {}; 82 void dwmci_memcpy_toio(void *buffer, void *fifo_addr) {}; 83 #endif 84 static int dwmci_wait_reset(struct dwmci_host *host, u32 value) 85 { 86 unsigned long timeout = 1000; 87 u32 ctrl; 88 89 dwmci_writel(host, DWMCI_CTRL, value); 90 91 while (timeout--) { 92 ctrl = dwmci_readl(host, DWMCI_CTRL); 93 if (!(ctrl & DWMCI_RESET_ALL)) 94 return 1; 95 } 96 return 0; 97 } 98 99 static void dwmci_set_idma_desc(struct dwmci_idmac *idmac, 100 u32 desc0, u32 desc1, u32 desc2) 101 { 102 struct dwmci_idmac *desc = idmac; 103 104 desc->flags = desc0; 105 desc->cnt = desc1; 106 desc->addr = desc2; 107 desc->next_addr = (ulong)desc + sizeof(struct dwmci_idmac); 108 } 109 110 static void dwmci_prepare_data(struct dwmci_host *host, 111 struct mmc_data *data, 112 struct dwmci_idmac *cur_idmac, 113 void *bounce_buffer) 114 { 115 unsigned long ctrl; 116 unsigned int i = 0, flags, cnt, blk_cnt; 117 ulong data_start, data_end; 118 119 120 blk_cnt = data->blocks; 121 122 dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET); 123 124 data_start = (ulong)cur_idmac; 125 dwmci_writel(host, DWMCI_DBADDR, (ulong)cur_idmac); 126 127 do { 128 flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ; 129 flags |= (i == 0) ? DWMCI_IDMAC_FS : 0; 130 if (blk_cnt <= 8) { 131 flags |= DWMCI_IDMAC_LD; 132 cnt = data->blocksize * blk_cnt; 133 } else 134 cnt = data->blocksize * 8; 135 136 dwmci_set_idma_desc(cur_idmac, flags, cnt, 137 (ulong)bounce_buffer + (i * PAGE_SIZE)); 138 139 if (blk_cnt <= 8) 140 break; 141 blk_cnt -= 8; 142 cur_idmac++; 143 i++; 144 } while(1); 145 146 data_end = (ulong)cur_idmac; 147 flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN); 148 149 ctrl = dwmci_readl(host, DWMCI_CTRL); 150 ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN; 151 dwmci_writel(host, DWMCI_CTRL, ctrl); 152 153 ctrl = dwmci_readl(host, DWMCI_BMOD); 154 ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN; 155 dwmci_writel(host, DWMCI_BMOD, ctrl); 156 157 dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize); 158 dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks); 159 } 160 161 static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data) 162 { 163 int ret = 0; 164 int reset_timeout = 100; 165 u32 timeout = 240000; 166 u32 status, ctrl, mask, size, i, len = 0; 167 u32 *buf = NULL; 168 ulong start = get_timer(0); 169 u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >> 170 RX_WMARK_SHIFT) + 1) * 2; 171 bool stride; 172 173 size = data->blocksize * data->blocks / 4; 174 /* Still use legacy PIO mode if size < 512(128 * 4) Bytes */ 175 stride = host->stride_pio && size > 128; 176 if (data->flags == MMC_DATA_READ) 177 buf = (unsigned int *)data->dest; 178 else 179 buf = (unsigned int *)data->src; 180 181 for (;;) { 182 mask = dwmci_readl(host, DWMCI_RINTSTS); 183 /* Error during data transfer. */ 184 if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) { 185 debug("%s: DATA ERROR!\n", __func__); 186 187 dwmci_wait_reset(host, DWMCI_RESET_ALL); 188 dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT | 189 DWMCI_CMD_UPD_CLK | DWMCI_CMD_START); 190 191 do { 192 status = dwmci_readl(host, DWMCI_CMD); 193 if (reset_timeout-- < 0) 194 break; 195 udelay(100); 196 } while (status & DWMCI_CMD_START); 197 198 if (!host->fifo_mode) { 199 ctrl = dwmci_readl(host, DWMCI_BMOD); 200 ctrl |= DWMCI_BMOD_IDMAC_RESET; 201 dwmci_writel(host, DWMCI_BMOD, ctrl); 202 } 203 204 ret = -EINVAL; 205 break; 206 } 207 208 if (host->fifo_mode && size) { 209 len = 0; 210 if (data->flags == MMC_DATA_READ && 211 (mask & DWMCI_INTMSK_RXDR)) { 212 while (size) { 213 len = dwmci_readl(host, DWMCI_STATUS); 214 len = (len >> DWMCI_FIFO_SHIFT) & 215 DWMCI_FIFO_MASK; 216 len = min(size, len); 217 if (!stride) { 218 /* Legacy pio mode */ 219 for (i = 0; i < len; i++) 220 *buf++ = dwmci_readl(host, DWMCI_DATA); 221 goto read_again; 222 } 223 224 /* dwmci_memcpy_fromio now bursts 256 Bytes once */ 225 if (len < MAX_STRIDE) 226 continue; 227 228 for (i = 0; i < len / MAX_STRIDE; i++) { 229 dwmci_memcpy_fromio(buf, host->ioaddr + DWMCI_DATA); 230 buf += MAX_STRIDE; 231 } 232 233 len = i * MAX_STRIDE; 234 read_again: 235 size = size > len ? (size - len) : 0; 236 } 237 dwmci_writel(host, DWMCI_RINTSTS, 238 DWMCI_INTMSK_RXDR); 239 } else if (data->flags == MMC_DATA_WRITE && 240 (mask & DWMCI_INTMSK_TXDR)) { 241 while (size) { 242 len = dwmci_readl(host, DWMCI_STATUS); 243 len = fifo_depth - ((len >> 244 DWMCI_FIFO_SHIFT) & 245 DWMCI_FIFO_MASK); 246 len = min(size, len); 247 if (!stride) { 248 for (i = 0; i < len; i++) 249 dwmci_writel(host, DWMCI_DATA, 250 *buf++); 251 goto write_again; 252 } 253 /* dwmci_memcpy_toio now bursts 256 Bytes once */ 254 if (len < MAX_STRIDE) 255 continue; 256 257 for (i = 0; i < len / MAX_STRIDE; i++) { 258 dwmci_memcpy_toio(buf, host->ioaddr + DWMCI_DATA); 259 buf += MAX_STRIDE; 260 } 261 262 len = i * MAX_STRIDE; 263 write_again: 264 size = size > len ? (size - len) : 0; 265 } 266 dwmci_writel(host, DWMCI_RINTSTS, 267 DWMCI_INTMSK_TXDR); 268 } 269 } 270 271 /* Data arrived correctly. */ 272 if (mask & DWMCI_INTMSK_DTO) { 273 ret = 0; 274 break; 275 } 276 277 /* Check for timeout. */ 278 if (get_timer(start) > timeout) { 279 debug("%s: Timeout waiting for data!\n", 280 __func__); 281 ret = -ETIMEDOUT; 282 break; 283 } 284 } 285 286 dwmci_writel(host, DWMCI_RINTSTS, mask); 287 288 return ret; 289 } 290 291 static int dwmci_set_transfer_mode(struct dwmci_host *host, 292 struct mmc_data *data) 293 { 294 unsigned long mode; 295 296 mode = DWMCI_CMD_DATA_EXP; 297 if (data->flags & MMC_DATA_WRITE) 298 mode |= DWMCI_CMD_RW; 299 300 return mode; 301 } 302 303 #ifdef CONFIG_DM_MMC 304 static int dwmci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, 305 struct mmc_data *data) 306 { 307 struct mmc *mmc = mmc_get_mmc_dev(dev); 308 #else 309 static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 310 struct mmc_data *data) 311 { 312 #endif 313 struct dwmci_host *host = mmc->priv; 314 ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac, 315 data ? DIV_ROUND_UP(data->blocks, 8) : 0); 316 int ret = 0, flags = 0, i; 317 unsigned int timeout = 500; 318 u32 retry = 100000; 319 u32 mask, ctrl; 320 ulong start = get_timer(0); 321 struct bounce_buffer bbstate; 322 323 while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) { 324 if (get_timer(start) > timeout) { 325 debug("%s: Timeout on data busy\n", __func__); 326 return -ETIMEDOUT; 327 } 328 } 329 330 dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL); 331 332 if (data) { 333 if (host->fifo_mode) { 334 dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize); 335 dwmci_writel(host, DWMCI_BYTCNT, 336 data->blocksize * data->blocks); 337 dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET); 338 } else { 339 if (data->flags == MMC_DATA_READ) { 340 bounce_buffer_start(&bbstate, (void*)data->dest, 341 data->blocksize * 342 data->blocks, GEN_BB_WRITE); 343 } else { 344 bounce_buffer_start(&bbstate, (void*)data->src, 345 data->blocksize * 346 data->blocks, GEN_BB_READ); 347 } 348 dwmci_prepare_data(host, data, cur_idmac, 349 bbstate.bounce_buffer); 350 } 351 } 352 353 dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg); 354 355 if (data) 356 flags = dwmci_set_transfer_mode(host, data); 357 358 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) 359 return -1; 360 361 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 362 flags |= DWMCI_CMD_ABORT_STOP; 363 else 364 flags |= DWMCI_CMD_PRV_DAT_WAIT; 365 366 if (cmd->resp_type & MMC_RSP_PRESENT) { 367 flags |= DWMCI_CMD_RESP_EXP; 368 if (cmd->resp_type & MMC_RSP_136) 369 flags |= DWMCI_CMD_RESP_LENGTH; 370 } 371 372 if (cmd->resp_type & MMC_RSP_CRC) 373 flags |= DWMCI_CMD_CHECK_CRC; 374 375 flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG); 376 377 debug("Sending CMD%d\n",cmd->cmdidx); 378 379 dwmci_writel(host, DWMCI_CMD, flags); 380 381 for (i = 0; i < retry; i++) { 382 mask = dwmci_readl(host, DWMCI_RINTSTS); 383 if (mask & DWMCI_INTMSK_CDONE) { 384 if (!data) 385 dwmci_writel(host, DWMCI_RINTSTS, mask); 386 break; 387 } 388 } 389 390 if (i == retry) { 391 debug("%s: Timeout.\n", __func__); 392 return -ETIMEDOUT; 393 } 394 395 if (mask & DWMCI_INTMSK_RTO) { 396 /* 397 * Timeout here is not necessarily fatal. (e)MMC cards 398 * will splat here when they receive CMD55 as they do 399 * not support this command and that is exactly the way 400 * to tell them apart from SD cards. Thus, this output 401 * below shall be debug(). eMMC cards also do not favor 402 * CMD8, please keep that in mind. 403 */ 404 debug("%s: Response Timeout.\n", __func__); 405 return -ETIMEDOUT; 406 } else if (mask & DWMCI_INTMSK_RE) { 407 debug("%s: Response Error.\n", __func__); 408 return -EIO; 409 } 410 411 412 if (cmd->resp_type & MMC_RSP_PRESENT) { 413 if (cmd->resp_type & MMC_RSP_136) { 414 cmd->response[0] = dwmci_readl(host, DWMCI_RESP3); 415 cmd->response[1] = dwmci_readl(host, DWMCI_RESP2); 416 cmd->response[2] = dwmci_readl(host, DWMCI_RESP1); 417 cmd->response[3] = dwmci_readl(host, DWMCI_RESP0); 418 } else { 419 cmd->response[0] = dwmci_readl(host, DWMCI_RESP0); 420 } 421 } 422 423 if (data) { 424 ret = dwmci_data_transfer(host, data); 425 426 /* only dma mode need it */ 427 if (!host->fifo_mode) { 428 ctrl = dwmci_readl(host, DWMCI_CTRL); 429 ctrl &= ~(DWMCI_DMA_EN); 430 dwmci_writel(host, DWMCI_CTRL, ctrl); 431 bounce_buffer_stop(&bbstate); 432 } 433 } 434 435 udelay(100); 436 437 return ret; 438 } 439 440 static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) 441 { 442 u32 div, status; 443 int timeout = 10000; 444 unsigned long sclk; 445 446 if (freq == 0) 447 return 0; 448 /* 449 * If host->get_mmc_clk isn't defined, 450 * then assume that host->bus_hz is source clock value. 451 * host->bus_hz should be set by user. 452 */ 453 if (host->get_mmc_clk) 454 sclk = host->get_mmc_clk(host, freq); 455 else if (host->bus_hz) 456 sclk = host->bus_hz; 457 else { 458 debug("%s: Didn't get source clock value.\n", __func__); 459 return -EINVAL; 460 } 461 462 if (sclk == freq) 463 div = 0; /* bypass mode */ 464 else 465 div = DIV_ROUND_UP(sclk, 2 * freq); 466 467 dwmci_writel(host, DWMCI_CLKENA, 0); 468 dwmci_writel(host, DWMCI_CLKSRC, 0); 469 470 dwmci_writel(host, DWMCI_CLKDIV, div); 471 dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT | 472 DWMCI_CMD_UPD_CLK | DWMCI_CMD_START); 473 474 do { 475 status = dwmci_readl(host, DWMCI_CMD); 476 if (timeout-- < 0) { 477 debug("%s: Timeout!\n", __func__); 478 return -ETIMEDOUT; 479 } 480 } while (status & DWMCI_CMD_START); 481 482 dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE | 483 DWMCI_CLKEN_LOW_PWR); 484 485 dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT | 486 DWMCI_CMD_UPD_CLK | DWMCI_CMD_START); 487 488 timeout = 10000; 489 do { 490 status = dwmci_readl(host, DWMCI_CMD); 491 if (timeout-- < 0) { 492 debug("%s: Timeout!\n", __func__); 493 return -ETIMEDOUT; 494 } 495 } while (status & DWMCI_CMD_START); 496 497 host->clock = freq; 498 499 return 0; 500 } 501 502 #ifdef CONFIG_DM_MMC 503 static bool dwmci_card_busy(struct udevice *dev) 504 { 505 struct mmc *mmc = mmc_get_mmc_dev(dev); 506 #else 507 static bool dwmci_card_busy(struct mmc *mmc) 508 { 509 #endif 510 u32 status; 511 struct dwmci_host *host = (struct dwmci_host *)mmc->priv; 512 513 /* 514 * Check the busy bit which is low when DAT[3:0] 515 * (the data lines) are 0000 516 */ 517 status = dwmci_readl(host, DWMCI_STATUS); 518 519 return !!(status & DWMCI_BUSY); 520 } 521 522 #ifdef CONFIG_DM_MMC 523 static int dwmci_execute_tuning(struct udevice *dev, u32 opcode) 524 { 525 struct mmc *mmc = mmc_get_mmc_dev(dev); 526 #else 527 static int dwmci_execute_tuning(struct mmc *mmc, u32 opcode) 528 { 529 #endif 530 struct dwmci_host *host = (struct dwmci_host *)mmc->priv; 531 532 if (!host->execute_tuning) 533 return -EIO; 534 535 return host->execute_tuning(host, opcode); 536 } 537 538 #ifdef CONFIG_DM_MMC 539 static int dwmci_set_ios(struct udevice *dev) 540 { 541 struct mmc *mmc = mmc_get_mmc_dev(dev); 542 #else 543 static int dwmci_set_ios(struct mmc *mmc) 544 { 545 #endif 546 struct dwmci_host *host = (struct dwmci_host *)mmc->priv; 547 u32 ctype, regs; 548 549 debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock); 550 551 dwmci_setup_bus(host, mmc->clock); 552 switch (mmc->bus_width) { 553 case 8: 554 ctype = DWMCI_CTYPE_8BIT; 555 break; 556 case 4: 557 ctype = DWMCI_CTYPE_4BIT; 558 break; 559 default: 560 ctype = DWMCI_CTYPE_1BIT; 561 break; 562 } 563 564 dwmci_writel(host, DWMCI_CTYPE, ctype); 565 566 regs = dwmci_readl(host, DWMCI_UHS_REG); 567 if (mmc_card_ddr(mmc)) 568 regs |= DWMCI_DDR_MODE; 569 else 570 regs &= ~DWMCI_DDR_MODE; 571 572 dwmci_writel(host, DWMCI_UHS_REG, regs); 573 574 if (host->clksel) 575 host->clksel(host); 576 577 return 0; 578 } 579 580 static int dwmci_init(struct mmc *mmc) 581 { 582 struct dwmci_host *host = mmc->priv; 583 uint32_t use_dma; 584 uint32_t verid; 585 586 if (host->board_init) 587 host->board_init(host); 588 #ifdef CONFIG_ARCH_ROCKCHIP 589 if (host->dev_index == 0) 590 dwmci_writel(host, DWMCI_PWREN, 1); 591 else if (host->dev_index == 1) 592 dwmci_writel(host, DWMCI_PWREN, 0); 593 else 594 dwmci_writel(host, DWMCI_PWREN, 1); 595 #else 596 dwmci_writel(host, DWMCI_PWREN, 1); 597 #endif 598 599 verid = dwmci_readl(host, DWMCI_VERID) & 0x0000ffff; 600 if (verid >= DW_MMC_240A) 601 dwmci_writel(host, DWMCI_CARDTHRCTL, DWMCI_CDTHRCTRL_CONFIG); 602 603 if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) { 604 debug("%s[%d] Fail-reset!!\n", __func__, __LINE__); 605 return -EIO; 606 } 607 608 use_dma = SDMMC_GET_TRANS_MODE(dwmci_readl(host, DWMCI_HCON)); 609 if (use_dma == DMA_INTERFACE_IDMA) { 610 host->fifo_mode = 0; 611 } else { 612 host->fifo_mode = 1; 613 } 614 615 /* Enumerate at 400KHz */ 616 dwmci_setup_bus(host, mmc->cfg->f_min); 617 618 dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF); 619 dwmci_writel(host, DWMCI_INTMASK, 0); 620 621 dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF); 622 623 dwmci_writel(host, DWMCI_IDINTEN, 0); 624 dwmci_writel(host, DWMCI_BMOD, 1); 625 626 if (!host->fifoth_val) { 627 uint32_t fifo_size; 628 629 fifo_size = dwmci_readl(host, DWMCI_FIFOTH); 630 fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1; 631 host->fifoth_val = MSIZE(DWMCI_MSIZE) | 632 RX_WMARK(fifo_size / 2 - 1) | 633 TX_WMARK(fifo_size / 2); 634 } 635 dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val); 636 637 dwmci_writel(host, DWMCI_CLKENA, 0); 638 dwmci_writel(host, DWMCI_CLKSRC, 0); 639 640 return 0; 641 } 642 643 static int dwmci_get_cd(struct udevice *dev) 644 { 645 int ret = -1; 646 #ifndef CONFIG_SPL_BUILD 647 #ifdef CONFIG_DM_GPIO 648 struct gpio_desc detect; 649 650 ret = gpio_request_by_name(dev, "cd-gpios", 0, &detect, GPIOD_IS_IN); 651 if (ret) { 652 return ret; 653 } 654 655 ret = !dm_gpio_get_value(&detect); 656 #endif 657 #endif 658 return ret; 659 } 660 661 #ifdef CONFIG_DM_MMC 662 int dwmci_probe(struct udevice *dev) 663 { 664 struct mmc *mmc = mmc_get_mmc_dev(dev); 665 666 return dwmci_init(mmc); 667 } 668 669 const struct dm_mmc_ops dm_dwmci_ops = { 670 .card_busy = dwmci_card_busy, 671 .send_cmd = dwmci_send_cmd, 672 .set_ios = dwmci_set_ios, 673 .get_cd = dwmci_get_cd, 674 .execute_tuning = dwmci_execute_tuning, 675 }; 676 677 #else 678 static const struct mmc_ops dwmci_ops = { 679 .card_busy = dwmci_card_busy, 680 .send_cmd = dwmci_send_cmd, 681 .set_ios = dwmci_set_ios, 682 .get_cd = dwmci_get_cd, 683 .init = dwmci_init, 684 .execute_tuning = dwmci_execute_tuning, 685 }; 686 #endif 687 688 void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host, 689 u32 max_clk, u32 min_clk) 690 { 691 cfg->name = host->name; 692 #ifndef CONFIG_DM_MMC 693 cfg->ops = &dwmci_ops; 694 #endif 695 cfg->f_min = min_clk; 696 cfg->f_max = max_clk; 697 698 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 699 700 cfg->host_caps = host->caps; 701 702 if (host->buswidth == 8) { 703 cfg->host_caps |= MMC_MODE_8BIT | MMC_MODE_4BIT; 704 } else { 705 cfg->host_caps |= MMC_MODE_4BIT; 706 cfg->host_caps &= ~MMC_MODE_8BIT; 707 } 708 cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz; 709 710 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 711 } 712 713 #ifdef CONFIG_BLK 714 int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg) 715 { 716 return mmc_bind(dev, mmc, cfg); 717 } 718 #else 719 int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk) 720 { 721 dwmci_setup_cfg(&host->cfg, host, max_clk, min_clk); 722 723 host->mmc = mmc_create(&host->cfg, host); 724 if (host->mmc == NULL) 725 return -1; 726 727 return 0; 728 } 729 #endif 730