1 /* 2 * (C) Copyright 2012 SAMSUNG Electronics 3 * Jaehoon Chung <jh80.chung@samsung.com> 4 * Rajeshawari Shinde <rajeshwari.s@samsung.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <bouncebuf.h> 11 #include <errno.h> 12 #include <malloc.h> 13 #include <memalign.h> 14 #include <mmc.h> 15 #include <dwmmc.h> 16 #ifdef CONFIG_DM_GPIO 17 #include <asm/gpio.h> 18 #include <asm-generic/gpio.h> 19 #endif 20 21 #define PAGE_SIZE 4096 22 23 /* 24 * Currently it supports read/write up to 8*8*4 Bytes per 25 * stride as a burst mode. Please note that if you change 26 * MAX_STRIDE, you should also update dwmci_memcpy_fromio 27 * to augment the groups of {ldm, stm}. 28 */ 29 #define MAX_STRIDE 64 30 #if CONFIG_ARM && CONFIG_CPU_V7 31 void noinline dwmci_memcpy_fromio(void *buffer, void *fifo_addr) 32 { 33 __asm__ __volatile__ ( 34 "push {r2, r3, r4, r5, r6, r7, r8, r9}\n" 35 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 36 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 37 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 38 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 39 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 40 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 41 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 42 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 43 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 44 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 45 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 46 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 47 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 48 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 49 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 50 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 51 "pop {r2, r3, r4, r5, r6,r7,r8,r9}\n" 52 :::"memory" 53 ); 54 } 55 56 void noinline dwmci_memcpy_toio(void *buffer, void *fifo_addr) 57 { 58 __asm__ __volatile__ ( 59 "push {r2, r3, r4, r5, r6, r7, r8, r9}\n" 60 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 61 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 62 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 63 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 64 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 65 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 66 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 67 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 68 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 69 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 70 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 71 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 72 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 73 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 74 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 75 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 76 "pop {r2, r3, r4, r5, r6,r7,r8,r9}\n" 77 :::"memory" 78 ); 79 } 80 #else 81 void dwmci_memcpy_fromio(void *buffer, void *fifo_addr) {}; 82 void dwmci_memcpy_toio(void *buffer, void *fifo_addr) {}; 83 #endif 84 static int dwmci_wait_reset(struct dwmci_host *host, u32 value) 85 { 86 unsigned long timeout = 1000; 87 u32 ctrl; 88 89 dwmci_writel(host, DWMCI_CTRL, value); 90 91 while (timeout--) { 92 ctrl = dwmci_readl(host, DWMCI_CTRL); 93 if (!(ctrl & DWMCI_RESET_ALL)) 94 return 1; 95 } 96 return 0; 97 } 98 99 static void dwmci_set_idma_desc(struct dwmci_idmac *idmac, 100 u32 desc0, u32 desc1, u32 desc2) 101 { 102 struct dwmci_idmac *desc = idmac; 103 104 desc->flags = desc0; 105 desc->cnt = desc1; 106 desc->addr = desc2; 107 desc->next_addr = (ulong)desc + sizeof(struct dwmci_idmac); 108 } 109 110 static void dwmci_prepare_data(struct dwmci_host *host, 111 struct mmc_data *data, 112 struct dwmci_idmac *cur_idmac, 113 void *bounce_buffer) 114 { 115 unsigned long ctrl; 116 unsigned int i = 0, flags, cnt, blk_cnt; 117 ulong data_start, data_end; 118 119 120 blk_cnt = data->blocks; 121 122 dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET); 123 124 data_start = (ulong)cur_idmac; 125 dwmci_writel(host, DWMCI_DBADDR, (ulong)cur_idmac); 126 127 do { 128 flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ; 129 flags |= (i == 0) ? DWMCI_IDMAC_FS : 0; 130 if (blk_cnt <= 8) { 131 flags |= DWMCI_IDMAC_LD; 132 cnt = data->blocksize * blk_cnt; 133 } else 134 cnt = data->blocksize * 8; 135 136 dwmci_set_idma_desc(cur_idmac, flags, cnt, 137 (ulong)bounce_buffer + (i * PAGE_SIZE)); 138 139 if (blk_cnt <= 8) 140 break; 141 blk_cnt -= 8; 142 cur_idmac++; 143 i++; 144 } while(1); 145 146 data_end = (ulong)cur_idmac; 147 flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN); 148 149 ctrl = dwmci_readl(host, DWMCI_CTRL); 150 ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN; 151 dwmci_writel(host, DWMCI_CTRL, ctrl); 152 153 ctrl = dwmci_readl(host, DWMCI_BMOD); 154 ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN; 155 dwmci_writel(host, DWMCI_BMOD, ctrl); 156 157 dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize); 158 dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks); 159 } 160 161 static unsigned int dwmci_get_timeout(struct mmc *mmc, const unsigned int size) 162 { 163 unsigned int timeout; 164 165 timeout = size * 8; /* counting in bits */ 166 timeout *= 10; /* wait 10 times as long */ 167 timeout /= mmc->clock; 168 timeout /= mmc->bus_width; 169 timeout *= 1000; /* counting in msec */ 170 timeout = (timeout < 10000) ? 10000 : timeout; 171 172 return timeout; 173 } 174 175 static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data) 176 { 177 int ret = 0; 178 int reset_timeout = 100; 179 u32 timeout, status, ctrl, mask, size, i, len = 0; 180 u32 *buf = NULL; 181 ulong start = get_timer(0); 182 u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >> 183 RX_WMARK_SHIFT) + 1) * 2; 184 bool stride; 185 186 size = data->blocksize * data->blocks; 187 /* Still use legacy PIO mode if size < 512(128 * 4) Bytes */ 188 stride = host->stride_pio && size > 128; 189 if (data->flags == MMC_DATA_READ) 190 buf = (unsigned int *)data->dest; 191 else 192 buf = (unsigned int *)data->src; 193 194 timeout = dwmci_get_timeout(host->mmc, size); 195 size /= 4; 196 197 for (;;) { 198 mask = dwmci_readl(host, DWMCI_RINTSTS); 199 /* Error during data transfer. */ 200 if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) { 201 debug("%s: DATA ERROR!\n", __func__); 202 203 dwmci_wait_reset(host, DWMCI_RESET_ALL); 204 dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT | 205 DWMCI_CMD_UPD_CLK | DWMCI_CMD_START); 206 207 do { 208 status = dwmci_readl(host, DWMCI_CMD); 209 if (reset_timeout-- < 0) 210 break; 211 udelay(100); 212 } while (status & DWMCI_CMD_START); 213 214 if (!host->fifo_mode) { 215 ctrl = dwmci_readl(host, DWMCI_BMOD); 216 ctrl |= DWMCI_BMOD_IDMAC_RESET; 217 dwmci_writel(host, DWMCI_BMOD, ctrl); 218 } 219 220 ret = -EINVAL; 221 break; 222 } 223 224 if (host->fifo_mode && size) { 225 len = 0; 226 if (data->flags == MMC_DATA_READ && 227 (mask & DWMCI_INTMSK_RXDR)) { 228 while (size) { 229 len = dwmci_readl(host, DWMCI_STATUS); 230 len = (len >> DWMCI_FIFO_SHIFT) & 231 DWMCI_FIFO_MASK; 232 len = min(size, len); 233 if (!stride) { 234 /* Legacy pio mode */ 235 for (i = 0; i < len; i++) 236 *buf++ = dwmci_readl(host, DWMCI_DATA); 237 goto read_again; 238 } 239 240 /* dwmci_memcpy_fromio now bursts 256 Bytes once */ 241 if (len < MAX_STRIDE) 242 continue; 243 244 for (i = 0; i < len / MAX_STRIDE; i++) { 245 dwmci_memcpy_fromio(buf, host->ioaddr + DWMCI_DATA); 246 buf += MAX_STRIDE; 247 } 248 249 len = i * MAX_STRIDE; 250 read_again: 251 size = size > len ? (size - len) : 0; 252 } 253 dwmci_writel(host, DWMCI_RINTSTS, 254 DWMCI_INTMSK_RXDR); 255 } else if (data->flags == MMC_DATA_WRITE && 256 (mask & DWMCI_INTMSK_TXDR)) { 257 while (size) { 258 len = dwmci_readl(host, DWMCI_STATUS); 259 len = fifo_depth - ((len >> 260 DWMCI_FIFO_SHIFT) & 261 DWMCI_FIFO_MASK); 262 len = min(size, len); 263 if (!stride) { 264 for (i = 0; i < len; i++) 265 dwmci_writel(host, DWMCI_DATA, 266 *buf++); 267 goto write_again; 268 } 269 /* dwmci_memcpy_toio now bursts 256 Bytes once */ 270 if (len < MAX_STRIDE) 271 continue; 272 273 for (i = 0; i < len / MAX_STRIDE; i++) { 274 dwmci_memcpy_toio(buf, host->ioaddr + DWMCI_DATA); 275 buf += MAX_STRIDE; 276 } 277 278 len = i * MAX_STRIDE; 279 write_again: 280 size = size > len ? (size - len) : 0; 281 } 282 dwmci_writel(host, DWMCI_RINTSTS, 283 DWMCI_INTMSK_TXDR); 284 } 285 } 286 287 /* Data arrived correctly. */ 288 if (mask & DWMCI_INTMSK_DTO) { 289 ret = 0; 290 break; 291 } 292 293 /* Check for timeout. */ 294 if (get_timer(start) > timeout) { 295 debug("%s: Timeout waiting for data!\n", 296 __func__); 297 ret = -ETIMEDOUT; 298 break; 299 } 300 } 301 302 dwmci_writel(host, DWMCI_RINTSTS, mask); 303 304 return ret; 305 } 306 307 static int dwmci_set_transfer_mode(struct dwmci_host *host, 308 struct mmc_data *data) 309 { 310 unsigned long mode; 311 312 mode = DWMCI_CMD_DATA_EXP; 313 if (data->flags & MMC_DATA_WRITE) 314 mode |= DWMCI_CMD_RW; 315 316 return mode; 317 } 318 319 #ifdef CONFIG_DM_MMC 320 static int dwmci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, 321 struct mmc_data *data) 322 { 323 struct mmc *mmc = mmc_get_mmc_dev(dev); 324 #else 325 static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 326 struct mmc_data *data) 327 { 328 #endif 329 struct dwmci_host *host = mmc->priv; 330 ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac, 331 data ? DIV_ROUND_UP(data->blocks, 8) : 0); 332 int ret = 0, flags = 0, i; 333 unsigned int timeout = 500; 334 u32 retry = 100000; 335 u32 mask, ctrl; 336 ulong start = get_timer(0); 337 struct bounce_buffer bbstate; 338 339 while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) { 340 if (get_timer(start) > timeout) { 341 debug("%s: Timeout on data busy\n", __func__); 342 return -ETIMEDOUT; 343 } 344 } 345 346 dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL); 347 348 if (data) { 349 if (host->fifo_mode) { 350 dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize); 351 dwmci_writel(host, DWMCI_BYTCNT, 352 data->blocksize * data->blocks); 353 dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET); 354 } else { 355 if (data->flags == MMC_DATA_READ) { 356 bounce_buffer_start(&bbstate, (void*)data->dest, 357 data->blocksize * 358 data->blocks, GEN_BB_WRITE); 359 } else { 360 bounce_buffer_start(&bbstate, (void*)data->src, 361 data->blocksize * 362 data->blocks, GEN_BB_READ); 363 } 364 dwmci_prepare_data(host, data, cur_idmac, 365 bbstate.bounce_buffer); 366 } 367 } 368 369 dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg); 370 371 if (data) 372 flags = dwmci_set_transfer_mode(host, data); 373 374 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) 375 return -1; 376 377 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 378 flags |= DWMCI_CMD_ABORT_STOP; 379 else 380 flags |= DWMCI_CMD_PRV_DAT_WAIT; 381 382 if (cmd->resp_type & MMC_RSP_PRESENT) { 383 flags |= DWMCI_CMD_RESP_EXP; 384 if (cmd->resp_type & MMC_RSP_136) 385 flags |= DWMCI_CMD_RESP_LENGTH; 386 } 387 388 if (cmd->resp_type & MMC_RSP_CRC) 389 flags |= DWMCI_CMD_CHECK_CRC; 390 391 flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG); 392 393 debug("Sending CMD%d\n",cmd->cmdidx); 394 395 dwmci_writel(host, DWMCI_CMD, flags); 396 397 for (i = 0; i < retry; i++) { 398 mask = dwmci_readl(host, DWMCI_RINTSTS); 399 if (mask & DWMCI_INTMSK_CDONE) { 400 if (!data) 401 dwmci_writel(host, DWMCI_RINTSTS, mask); 402 break; 403 } 404 } 405 406 if (i == retry) { 407 debug("%s: Timeout.\n", __func__); 408 return -ETIMEDOUT; 409 } 410 411 if (mask & DWMCI_INTMSK_RTO) { 412 /* 413 * Timeout here is not necessarily fatal. (e)MMC cards 414 * will splat here when they receive CMD55 as they do 415 * not support this command and that is exactly the way 416 * to tell them apart from SD cards. Thus, this output 417 * below shall be debug(). eMMC cards also do not favor 418 * CMD8, please keep that in mind. 419 */ 420 debug("%s: Response Timeout.\n", __func__); 421 return -ETIMEDOUT; 422 } else if (mask & DWMCI_INTMSK_RE) { 423 debug("%s: Response Error.\n", __func__); 424 return -EIO; 425 } 426 427 428 if (cmd->resp_type & MMC_RSP_PRESENT) { 429 if (cmd->resp_type & MMC_RSP_136) { 430 cmd->response[0] = dwmci_readl(host, DWMCI_RESP3); 431 cmd->response[1] = dwmci_readl(host, DWMCI_RESP2); 432 cmd->response[2] = dwmci_readl(host, DWMCI_RESP1); 433 cmd->response[3] = dwmci_readl(host, DWMCI_RESP0); 434 } else { 435 cmd->response[0] = dwmci_readl(host, DWMCI_RESP0); 436 } 437 } 438 439 if (data) { 440 ret = dwmci_data_transfer(host, data); 441 442 /* only dma mode need it */ 443 if (!host->fifo_mode) { 444 ctrl = dwmci_readl(host, DWMCI_CTRL); 445 ctrl &= ~(DWMCI_DMA_EN); 446 dwmci_writel(host, DWMCI_CTRL, ctrl); 447 bounce_buffer_stop(&bbstate); 448 } 449 } 450 451 udelay(100); 452 453 return ret; 454 } 455 456 #ifdef CONFIG_SPL_BLK_READ_PREPARE 457 #ifdef CONFIG_DM_MMC 458 static int dwmci_send_cmd_prepare(struct udevice *dev, struct mmc_cmd *cmd, 459 struct mmc_data *data) 460 { 461 struct mmc *mmc = mmc_get_mmc_dev(dev); 462 #else 463 static int dwmci_send_cmd_prepare(struct mmc *mmc, struct mmc_cmd *cmd, 464 struct mmc_data *data) 465 { 466 #endif 467 struct dwmci_host *host = mmc->priv; 468 struct dwmci_idmac *cur_idmac; 469 int ret = 0, flags = 0, i; 470 unsigned int timeout = 500; 471 u32 retry = 100000; 472 u32 mask; 473 ulong start = get_timer(0); 474 struct bounce_buffer bbstate; 475 476 cur_idmac = malloc(ROUND(DIV_ROUND_UP(data->blocks, 8) * 477 sizeof(struct dwmci_idmac), 478 ARCH_DMA_MINALIGN) + ARCH_DMA_MINALIGN - 1); 479 if (!cur_idmac) 480 return -ENODATA; 481 482 while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) { 483 if (get_timer(start) > timeout) { 484 debug("%s: Timeout on data busy\n", __func__); 485 return -ETIMEDOUT; 486 } 487 } 488 489 dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL); 490 491 if (data) { 492 if (host->fifo_mode) { 493 dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize); 494 dwmci_writel(host, DWMCI_BYTCNT, 495 data->blocksize * data->blocks); 496 dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET); 497 } else { 498 if (data->flags == MMC_DATA_READ) { 499 bounce_buffer_start(&bbstate, (void *)data->dest, 500 data->blocksize * 501 data->blocks, GEN_BB_WRITE); 502 } else { 503 bounce_buffer_start(&bbstate, (void *)data->src, 504 data->blocksize * 505 data->blocks, GEN_BB_READ); 506 } 507 dwmci_prepare_data(host, data, cur_idmac, 508 bbstate.bounce_buffer); 509 } 510 } 511 512 dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg); 513 514 if (data) 515 flags = dwmci_set_transfer_mode(host, data); 516 517 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) 518 return -1; 519 520 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 521 flags |= DWMCI_CMD_ABORT_STOP; 522 else 523 flags |= DWMCI_CMD_PRV_DAT_WAIT; 524 525 if (cmd->resp_type & MMC_RSP_PRESENT) { 526 flags |= DWMCI_CMD_RESP_EXP; 527 if (cmd->resp_type & MMC_RSP_136) 528 flags |= DWMCI_CMD_RESP_LENGTH; 529 } 530 531 if (cmd->resp_type & MMC_RSP_CRC) 532 flags |= DWMCI_CMD_CHECK_CRC; 533 534 flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG); 535 536 debug("Sending CMD%d\n", cmd->cmdidx); 537 538 dwmci_writel(host, DWMCI_CMD, flags); 539 540 for (i = 0; i < retry; i++) { 541 mask = dwmci_readl(host, DWMCI_RINTSTS); 542 if (mask & DWMCI_INTMSK_CDONE) { 543 if (!data) 544 dwmci_writel(host, DWMCI_RINTSTS, mask); 545 break; 546 } 547 } 548 549 if (i == retry) { 550 debug("%s: Timeout.\n", __func__); 551 return -ETIMEDOUT; 552 } 553 554 if (mask & DWMCI_INTMSK_RTO) { 555 /* 556 * Timeout here is not necessarily fatal. (e)MMC cards 557 * will splat here when they receive CMD55 as they do 558 * not support this command and that is exactly the way 559 * to tell them apart from SD cards. Thus, this output 560 * below shall be debug(). eMMC cards also do not favor 561 * CMD8, please keep that in mind. 562 */ 563 debug("%s: Response Timeout.\n", __func__); 564 return -ETIMEDOUT; 565 } else if (mask & DWMCI_INTMSK_RE) { 566 debug("%s: Response Error.\n", __func__); 567 return -EIO; 568 } 569 570 if (cmd->resp_type & MMC_RSP_PRESENT) { 571 if (cmd->resp_type & MMC_RSP_136) { 572 cmd->response[0] = dwmci_readl(host, DWMCI_RESP3); 573 cmd->response[1] = dwmci_readl(host, DWMCI_RESP2); 574 cmd->response[2] = dwmci_readl(host, DWMCI_RESP1); 575 cmd->response[3] = dwmci_readl(host, DWMCI_RESP0); 576 } else { 577 cmd->response[0] = dwmci_readl(host, DWMCI_RESP0); 578 } 579 } 580 581 return ret; 582 } 583 #endif 584 585 static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) 586 { 587 u32 div, status; 588 int timeout = 10000; 589 unsigned long sclk; 590 591 if (freq == 0) 592 return 0; 593 /* 594 * If host->get_mmc_clk isn't defined, 595 * then assume that host->bus_hz is source clock value. 596 * host->bus_hz should be set by user. 597 */ 598 if (host->get_mmc_clk) 599 sclk = host->get_mmc_clk(host, freq); 600 else if (host->bus_hz) 601 sclk = host->bus_hz; 602 else { 603 debug("%s: Didn't get source clock value.\n", __func__); 604 return -EINVAL; 605 } 606 607 if (sclk == freq) 608 div = 0; /* bypass mode */ 609 else 610 div = DIV_ROUND_UP(sclk, 2 * freq); 611 612 dwmci_writel(host, DWMCI_CLKENA, 0); 613 dwmci_writel(host, DWMCI_CLKSRC, 0); 614 615 dwmci_writel(host, DWMCI_CLKDIV, div); 616 dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT | 617 DWMCI_CMD_UPD_CLK | DWMCI_CMD_START); 618 619 do { 620 status = dwmci_readl(host, DWMCI_CMD); 621 if (timeout-- < 0) { 622 debug("%s: Timeout!\n", __func__); 623 return -ETIMEDOUT; 624 } 625 } while (status & DWMCI_CMD_START); 626 627 dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE | 628 DWMCI_CLKEN_LOW_PWR); 629 630 dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT | 631 DWMCI_CMD_UPD_CLK | DWMCI_CMD_START); 632 633 timeout = 10000; 634 do { 635 status = dwmci_readl(host, DWMCI_CMD); 636 if (timeout-- < 0) { 637 debug("%s: Timeout!\n", __func__); 638 return -ETIMEDOUT; 639 } 640 } while (status & DWMCI_CMD_START); 641 642 host->clock = freq; 643 644 return 0; 645 } 646 647 #ifdef CONFIG_DM_MMC 648 static bool dwmci_card_busy(struct udevice *dev) 649 { 650 struct mmc *mmc = mmc_get_mmc_dev(dev); 651 #else 652 static bool dwmci_card_busy(struct mmc *mmc) 653 { 654 #endif 655 u32 status; 656 struct dwmci_host *host = (struct dwmci_host *)mmc->priv; 657 658 /* 659 * Check the busy bit which is low when DAT[3:0] 660 * (the data lines) are 0000 661 */ 662 status = dwmci_readl(host, DWMCI_STATUS); 663 664 return !!(status & DWMCI_BUSY); 665 } 666 667 #ifdef CONFIG_DM_MMC 668 static int dwmci_execute_tuning(struct udevice *dev, u32 opcode) 669 { 670 struct mmc *mmc = mmc_get_mmc_dev(dev); 671 #else 672 static int dwmci_execute_tuning(struct mmc *mmc, u32 opcode) 673 { 674 #endif 675 struct dwmci_host *host = (struct dwmci_host *)mmc->priv; 676 677 if (!host->execute_tuning) 678 return -EIO; 679 680 return host->execute_tuning(host, opcode); 681 } 682 683 #ifdef CONFIG_DM_MMC 684 static int dwmci_set_ios(struct udevice *dev) 685 { 686 struct mmc *mmc = mmc_get_mmc_dev(dev); 687 #else 688 static int dwmci_set_ios(struct mmc *mmc) 689 { 690 #endif 691 struct dwmci_host *host = (struct dwmci_host *)mmc->priv; 692 u32 ctype, regs; 693 694 debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock); 695 696 dwmci_setup_bus(host, mmc->clock); 697 switch (mmc->bus_width) { 698 case 8: 699 ctype = DWMCI_CTYPE_8BIT; 700 break; 701 case 4: 702 ctype = DWMCI_CTYPE_4BIT; 703 break; 704 default: 705 ctype = DWMCI_CTYPE_1BIT; 706 break; 707 } 708 709 dwmci_writel(host, DWMCI_CTYPE, ctype); 710 711 regs = dwmci_readl(host, DWMCI_UHS_REG); 712 if (mmc_card_ddr(mmc)) 713 regs |= DWMCI_DDR_MODE; 714 else 715 regs &= ~DWMCI_DDR_MODE; 716 717 dwmci_writel(host, DWMCI_UHS_REG, regs); 718 719 if (host->clksel) 720 host->clksel(host); 721 722 return 0; 723 } 724 725 static int dwmci_init(struct mmc *mmc) 726 { 727 struct dwmci_host *host = mmc->priv; 728 uint32_t use_dma; 729 uint32_t verid; 730 731 if (host->board_init) 732 host->board_init(host); 733 #ifdef CONFIG_ARCH_ROCKCHIP 734 if (host->dev_index == 0) 735 dwmci_writel(host, DWMCI_PWREN, 1); 736 else if (host->dev_index == 1) 737 dwmci_writel(host, DWMCI_PWREN, 0); 738 else 739 dwmci_writel(host, DWMCI_PWREN, 1); 740 #else 741 dwmci_writel(host, DWMCI_PWREN, 1); 742 #endif 743 744 verid = dwmci_readl(host, DWMCI_VERID) & 0x0000ffff; 745 if (verid >= DW_MMC_240A) 746 dwmci_writel(host, DWMCI_CARDTHRCTL, DWMCI_CDTHRCTRL_CONFIG); 747 748 if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) { 749 debug("%s[%d] Fail-reset!!\n", __func__, __LINE__); 750 return -EIO; 751 } 752 753 use_dma = SDMMC_GET_TRANS_MODE(dwmci_readl(host, DWMCI_HCON)); 754 if (use_dma == DMA_INTERFACE_IDMA) { 755 host->fifo_mode = 0; 756 } else { 757 host->fifo_mode = 1; 758 } 759 760 /* Enumerate at 400KHz */ 761 dwmci_setup_bus(host, mmc->cfg->f_min); 762 763 dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF); 764 dwmci_writel(host, DWMCI_INTMASK, 0); 765 766 dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF); 767 768 dwmci_writel(host, DWMCI_IDINTEN, 0); 769 dwmci_writel(host, DWMCI_BMOD, 1); 770 771 if (!host->fifoth_val) { 772 uint32_t fifo_size; 773 774 fifo_size = dwmci_readl(host, DWMCI_FIFOTH); 775 fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1; 776 host->fifoth_val = MSIZE(DWMCI_MSIZE) | 777 RX_WMARK(fifo_size / 2 - 1) | 778 TX_WMARK(fifo_size / 2); 779 } 780 dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val); 781 782 dwmci_writel(host, DWMCI_CLKENA, 0); 783 dwmci_writel(host, DWMCI_CLKSRC, 0); 784 785 return 0; 786 } 787 788 static int dwmci_get_cd(struct udevice *dev) 789 { 790 int ret = -1; 791 #ifndef CONFIG_SPL_BUILD 792 #ifdef CONFIG_DM_GPIO 793 struct gpio_desc detect; 794 795 ret = gpio_request_by_name(dev, "cd-gpios", 0, &detect, GPIOD_IS_IN); 796 if (ret) { 797 return ret; 798 } 799 800 ret = !dm_gpio_get_value(&detect); 801 #endif 802 #endif 803 return ret; 804 } 805 806 #ifdef CONFIG_DM_MMC 807 int dwmci_probe(struct udevice *dev) 808 { 809 struct mmc *mmc = mmc_get_mmc_dev(dev); 810 811 return dwmci_init(mmc); 812 } 813 814 const struct dm_mmc_ops dm_dwmci_ops = { 815 .card_busy = dwmci_card_busy, 816 .send_cmd = dwmci_send_cmd, 817 #ifdef CONFIG_SPL_BLK_READ_PREPARE 818 .send_cmd_prepare = dwmci_send_cmd_prepare, 819 #endif 820 .set_ios = dwmci_set_ios, 821 .get_cd = dwmci_get_cd, 822 .execute_tuning = dwmci_execute_tuning, 823 }; 824 825 #else 826 static const struct mmc_ops dwmci_ops = { 827 .card_busy = dwmci_card_busy, 828 .send_cmd = dwmci_send_cmd, 829 .set_ios = dwmci_set_ios, 830 .get_cd = dwmci_get_cd, 831 .init = dwmci_init, 832 .execute_tuning = dwmci_execute_tuning, 833 }; 834 #endif 835 836 void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host, 837 u32 max_clk, u32 min_clk) 838 { 839 cfg->name = host->name; 840 #ifndef CONFIG_DM_MMC 841 cfg->ops = &dwmci_ops; 842 #endif 843 cfg->f_min = min_clk; 844 cfg->f_max = max_clk; 845 846 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 847 848 cfg->host_caps = host->caps; 849 850 if (host->buswidth == 8) { 851 cfg->host_caps |= MMC_MODE_8BIT | MMC_MODE_4BIT; 852 } else { 853 cfg->host_caps |= MMC_MODE_4BIT; 854 cfg->host_caps &= ~MMC_MODE_8BIT; 855 } 856 cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz; 857 858 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 859 } 860 861 #ifdef CONFIG_BLK 862 int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg) 863 { 864 return mmc_bind(dev, mmc, cfg); 865 } 866 #else 867 int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk) 868 { 869 dwmci_setup_cfg(&host->cfg, host, max_clk, min_clk); 870 871 host->mmc = mmc_create(&host->cfg, host); 872 if (host->mmc == NULL) 873 return -1; 874 875 return 0; 876 } 877 #endif 878