1 /* 2 * (C) Copyright 2012 SAMSUNG Electronics 3 * Jaehoon Chung <jh80.chung@samsung.com> 4 * Rajeshawari Shinde <rajeshwari.s@samsung.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <bouncebuf.h> 11 #include <div64.h> 12 #include <errno.h> 13 #include <malloc.h> 14 #include <memalign.h> 15 #include <mmc.h> 16 #include <dwmmc.h> 17 #include <dm/pinctrl.h> 18 #include <dm.h> 19 #ifdef CONFIG_DM_GPIO 20 #include <asm/gpio.h> 21 #include <asm-generic/gpio.h> 22 #endif 23 24 #define PAGE_SIZE 4096 25 #define MSEC_PER_SEC 1000ULL 26 27 /* 28 * Currently it supports read/write up to 8*8*4 Bytes per 29 * stride as a burst mode. Please note that if you change 30 * MAX_STRIDE, you should also update dwmci_memcpy_fromio 31 * to augment the groups of {ldm, stm}. 32 */ 33 #define MAX_STRIDE 64 34 #if (CONFIG_ARM && CONFIG_CPU_V7 && !defined(CONFIG_MMC_SIMPLE)) 35 void noinline dwmci_memcpy_fromio(void *buffer, void *fifo_addr) 36 { 37 __asm__ __volatile__ ( 38 "push {r2, r3, r4, r5, r6, r7, r8, r9}\n" 39 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 40 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 41 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 42 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 43 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 44 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 45 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 46 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 47 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 48 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 49 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 50 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 51 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 52 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 53 "ldm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 54 "stm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 55 "pop {r2, r3, r4, r5, r6,r7,r8,r9}\n" 56 :::"memory" 57 ); 58 } 59 60 void noinline dwmci_memcpy_toio(void *buffer, void *fifo_addr) 61 { 62 __asm__ __volatile__ ( 63 "push {r2, r3, r4, r5, r6, r7, r8, r9}\n" 64 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 65 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 66 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 67 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 68 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 69 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 70 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 71 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 72 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 73 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 74 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 75 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 76 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 77 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 78 "ldm r0!, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 79 "stm r1, {r2,r3,r4,r5,r6,r7,r8,r9}\n" 80 "pop {r2, r3, r4, r5, r6,r7,r8,r9}\n" 81 :::"memory" 82 ); 83 } 84 #else 85 void dwmci_memcpy_fromio(void *buffer, void *fifo_addr) {}; 86 void dwmci_memcpy_toio(void *buffer, void *fifo_addr) {}; 87 #endif 88 89 static int dwmci_wait_reset(struct dwmci_host *host, u32 value) 90 { 91 unsigned long timeout = 1000; 92 u32 ctrl; 93 94 dwmci_writel(host, DWMCI_CTRL, value); 95 96 while (timeout--) { 97 ctrl = dwmci_readl(host, DWMCI_CTRL); 98 if (!(ctrl & DWMCI_RESET_ALL)) 99 return 1; 100 } 101 return 0; 102 } 103 104 static void dwmci_set_idma_desc(struct dwmci_idmac *idmac, 105 u32 desc0, u32 desc1, u32 desc2) 106 { 107 struct dwmci_idmac *desc = idmac; 108 109 desc->flags = desc0; 110 desc->cnt = desc1; 111 desc->addr = desc2; 112 desc->next_addr = (ulong)desc + sizeof(struct dwmci_idmac); 113 } 114 115 static void dwmci_prepare_data(struct dwmci_host *host, 116 struct mmc_data *data, 117 struct dwmci_idmac *cur_idmac, 118 void *bounce_buffer) 119 { 120 unsigned long ctrl; 121 unsigned int i = 0, flags, cnt, blk_cnt; 122 ulong data_start, data_end; 123 124 125 blk_cnt = data->blocks; 126 127 dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET); 128 129 data_start = (ulong)cur_idmac; 130 dwmci_writel(host, DWMCI_DBADDR, (ulong)cur_idmac); 131 132 do { 133 flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ; 134 flags |= (i == 0) ? DWMCI_IDMAC_FS : 0; 135 if (blk_cnt <= 8) { 136 flags |= DWMCI_IDMAC_LD; 137 cnt = data->blocksize * blk_cnt; 138 } else 139 cnt = data->blocksize * 8; 140 141 dwmci_set_idma_desc(cur_idmac, flags, cnt, 142 (ulong)bounce_buffer + (i * PAGE_SIZE)); 143 144 if (blk_cnt <= 8) 145 break; 146 blk_cnt -= 8; 147 cur_idmac++; 148 i++; 149 } while(1); 150 151 data_end = (ulong)cur_idmac; 152 flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN); 153 154 ctrl = dwmci_readl(host, DWMCI_CTRL); 155 ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN; 156 dwmci_writel(host, DWMCI_CTRL, ctrl); 157 158 ctrl = dwmci_readl(host, DWMCI_BMOD); 159 ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN; 160 dwmci_writel(host, DWMCI_BMOD, ctrl); 161 162 dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize); 163 dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks); 164 } 165 166 #ifdef CONFIG_SPL_BUILD 167 static unsigned int dwmci_get_drto(struct dwmci_host *host, 168 const unsigned int size) 169 { 170 unsigned int drto_clks; 171 unsigned int drto_div; 172 unsigned int drto_ms; 173 174 drto_clks = dwmci_readl(host, DWMCI_TMOUT) >> 8; 175 drto_div = (dwmci_readl(host, DWMCI_CLKDIV) & 0xff) * 2; 176 if (drto_div == 0) 177 drto_div = 1; 178 179 drto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * drto_clks * drto_div, 180 host->mmc->clock); 181 182 /* add a bit spare time */ 183 drto_ms += 10; 184 185 return drto_ms; 186 } 187 #else 188 static unsigned int dwmci_get_drto(struct dwmci_host *host, 189 const unsigned int size) 190 { 191 unsigned int timeout; 192 193 timeout = size * 8; /* counting in bits */ 194 timeout *= 10; /* wait 10 times as long */ 195 timeout /= host->mmc->clock; 196 timeout /= host->mmc->bus_width; 197 timeout *= 1000; /* counting in msec */ 198 timeout = (timeout < 10000) ? 10000 : timeout; 199 200 return timeout; 201 } 202 #endif 203 204 static unsigned int dwmci_get_cto(struct dwmci_host *host) 205 { 206 unsigned int cto_clks; 207 unsigned int cto_div; 208 unsigned int cto_ms; 209 210 cto_clks = dwmci_readl(host, DWMCI_TMOUT) & 0xff; 211 cto_div = (dwmci_readl(host, DWMCI_CLKDIV) & 0xff) * 2; 212 if (cto_div == 0) 213 cto_div = 1; 214 215 cto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * cto_clks * cto_div, 216 host->mmc->clock); 217 218 /* add a bit spare time */ 219 cto_ms += 10; 220 221 return cto_ms; 222 } 223 224 static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data) 225 { 226 int ret = 0; 227 int reset_timeout = 100; 228 u32 timeout, status, ctrl, mask, size, i, len = 0; 229 u32 *buf = NULL; 230 ulong start = get_timer(0); 231 u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >> 232 RX_WMARK_SHIFT) + 1) * 2; 233 bool stride; 234 235 size = data->blocksize * data->blocks; 236 /* Still use legacy PIO mode if size < 512(128 * 4) Bytes */ 237 stride = host->stride_pio && size > 128; 238 if (data->flags == MMC_DATA_READ) 239 buf = (unsigned int *)data->dest; 240 else 241 buf = (unsigned int *)data->src; 242 243 timeout = dwmci_get_drto(host, size); 244 /* The tuning data is 128bytes, a timeout of 1ms is sufficient.*/ 245 if ((dwmci_readl(host, DWMCI_CMD) & 0x1F) == MMC_SEND_TUNING_BLOCK_HS200) 246 timeout = 1; 247 248 size /= 4; 249 250 for (;;) { 251 mask = dwmci_readl(host, DWMCI_RINTSTS); 252 /* Error during data transfer. */ 253 if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) { 254 debug("%s: DATA ERROR!\n", __func__); 255 dwmci_wait_reset(host, DWMCI_RESET_ALL); 256 dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT | 257 DWMCI_CMD_UPD_CLK | DWMCI_CMD_START); 258 259 do { 260 status = dwmci_readl(host, DWMCI_CMD); 261 if (reset_timeout-- < 0) 262 break; 263 udelay(100); 264 } while (status & DWMCI_CMD_START); 265 266 if (!host->fifo_mode) { 267 ctrl = dwmci_readl(host, DWMCI_BMOD); 268 ctrl |= DWMCI_BMOD_IDMAC_RESET; 269 dwmci_writel(host, DWMCI_BMOD, ctrl); 270 } 271 272 ret = -EINVAL; 273 break; 274 } 275 276 if (host->fifo_mode && size) { 277 len = 0; 278 if (data->flags == MMC_DATA_READ && 279 (mask & DWMCI_INTMSK_RXDR)) { 280 while (size) { 281 len = dwmci_readl(host, DWMCI_STATUS); 282 len = (len >> DWMCI_FIFO_SHIFT) & 283 DWMCI_FIFO_MASK; 284 len = min(size, len); 285 if (!stride) { 286 /* Legacy pio mode */ 287 for (i = 0; i < len; i++) 288 *buf++ = dwmci_readl(host, DWMCI_DATA); 289 goto read_again; 290 } 291 292 /* dwmci_memcpy_fromio now bursts 256 Bytes once */ 293 if (len < MAX_STRIDE) 294 continue; 295 296 for (i = 0; i < len / MAX_STRIDE; i++) { 297 dwmci_memcpy_fromio(buf, host->ioaddr + DWMCI_DATA); 298 buf += MAX_STRIDE; 299 } 300 301 len = i * MAX_STRIDE; 302 read_again: 303 size = size > len ? (size - len) : 0; 304 } 305 dwmci_writel(host, DWMCI_RINTSTS, 306 DWMCI_INTMSK_RXDR); 307 start = get_timer(0); 308 } else if (data->flags == MMC_DATA_WRITE && 309 (mask & DWMCI_INTMSK_TXDR)) { 310 while (size) { 311 len = dwmci_readl(host, DWMCI_STATUS); 312 len = fifo_depth - ((len >> 313 DWMCI_FIFO_SHIFT) & 314 DWMCI_FIFO_MASK); 315 len = min(size, len); 316 if (!stride) { 317 for (i = 0; i < len; i++) 318 dwmci_writel(host, DWMCI_DATA, 319 *buf++); 320 goto write_again; 321 } 322 /* dwmci_memcpy_toio now bursts 256 Bytes once */ 323 if (len < MAX_STRIDE) 324 continue; 325 326 for (i = 0; i < len / MAX_STRIDE; i++) { 327 dwmci_memcpy_toio(buf, host->ioaddr + DWMCI_DATA); 328 buf += MAX_STRIDE; 329 } 330 331 len = i * MAX_STRIDE; 332 write_again: 333 size = size > len ? (size - len) : 0; 334 } 335 dwmci_writel(host, DWMCI_RINTSTS, 336 DWMCI_INTMSK_TXDR); 337 start = get_timer(0); 338 } 339 } 340 341 /* Data arrived correctly. */ 342 if (mask & DWMCI_INTMSK_DTO) { 343 ret = 0; 344 break; 345 } 346 347 /* Check for timeout. */ 348 if (get_timer(start) > timeout) { 349 debug("%s: Timeout waiting for data!\n", 350 __func__); 351 ret = -ETIMEDOUT; 352 break; 353 } 354 } 355 356 dwmci_writel(host, DWMCI_RINTSTS, mask); 357 358 return ret; 359 } 360 361 static int dwmci_set_transfer_mode(struct dwmci_host *host, 362 struct mmc_data *data) 363 { 364 unsigned long mode; 365 366 mode = DWMCI_CMD_DATA_EXP; 367 if (data->flags & MMC_DATA_WRITE) 368 mode |= DWMCI_CMD_RW; 369 370 return mode; 371 } 372 373 #ifdef CONFIG_DM_MMC 374 static int dwmci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, 375 struct mmc_data *data) 376 { 377 struct mmc *mmc = mmc_get_mmc_dev(dev); 378 #else 379 static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, 380 struct mmc_data *data) 381 { 382 #endif 383 struct dwmci_host *host = mmc->priv; 384 ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac, 385 data ? DIV_ROUND_UP(data->blocks, 8) : 0); 386 int ret = 0, flags = 0; 387 unsigned int timeout = 500; 388 u32 mask, ctrl; 389 ulong start = get_timer(0); 390 struct bounce_buffer bbstate; 391 392 while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) { 393 if (get_timer(start) > timeout) { 394 debug("%s: Timeout on data busy\n", __func__); 395 return -ETIMEDOUT; 396 } 397 } 398 399 dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL); 400 401 if (data) { 402 if (host->fifo_mode) { 403 dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize); 404 dwmci_writel(host, DWMCI_BYTCNT, 405 data->blocksize * data->blocks); 406 dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET); 407 } else { 408 if (data->flags == MMC_DATA_READ) { 409 ret = bounce_buffer_start(&bbstate, 410 (void*)data->dest, 411 data->blocksize * 412 data->blocks, GEN_BB_WRITE); 413 } else { 414 ret = bounce_buffer_start(&bbstate, 415 (void*)data->src, 416 data->blocksize * 417 data->blocks, GEN_BB_READ); 418 } 419 420 if (ret) 421 return ret; 422 423 dwmci_prepare_data(host, data, cur_idmac, 424 bbstate.bounce_buffer); 425 } 426 } 427 428 dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg); 429 430 if (data) 431 flags = dwmci_set_transfer_mode(host, data); 432 433 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) 434 return -1; 435 436 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 437 flags |= DWMCI_CMD_ABORT_STOP; 438 else 439 flags |= DWMCI_CMD_PRV_DAT_WAIT; 440 441 if (cmd->resp_type & MMC_RSP_PRESENT) { 442 flags |= DWMCI_CMD_RESP_EXP; 443 if (cmd->resp_type & MMC_RSP_136) 444 flags |= DWMCI_CMD_RESP_LENGTH; 445 } 446 447 if (cmd->resp_type & MMC_RSP_CRC) 448 flags |= DWMCI_CMD_CHECK_CRC; 449 450 flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG); 451 452 debug("Sending CMD%d\n",cmd->cmdidx); 453 454 dwmci_writel(host, DWMCI_CMD, flags); 455 456 timeout = dwmci_get_cto(host); 457 start = get_timer(0); 458 do { 459 mask = dwmci_readl(host, DWMCI_RINTSTS); 460 if (mask & DWMCI_INTMSK_CDONE) { 461 if (!data) 462 dwmci_writel(host, DWMCI_RINTSTS, mask); 463 break; 464 } 465 } while (!(get_timer(start) > timeout)); 466 467 if (get_timer(start) > timeout) { 468 debug("%s: Timeout.\n", __func__); 469 return -ETIMEDOUT; 470 } 471 472 if (mask & DWMCI_INTMSK_RTO) { 473 /* 474 * Timeout here is not necessarily fatal. (e)MMC cards 475 * will splat here when they receive CMD55 as they do 476 * not support this command and that is exactly the way 477 * to tell them apart from SD cards. Thus, this output 478 * below shall be debug(). eMMC cards also do not favor 479 * CMD8, please keep that in mind. 480 */ 481 debug("%s: Response Timeout.\n", __func__); 482 return -ETIMEDOUT; 483 } else if (mask & DWMCI_INTMSK_RE) { 484 debug("%s: Response Error.\n", __func__); 485 return -EIO; 486 } 487 488 489 if (cmd->resp_type & MMC_RSP_PRESENT) { 490 if (cmd->resp_type & MMC_RSP_136) { 491 cmd->response[0] = dwmci_readl(host, DWMCI_RESP3); 492 cmd->response[1] = dwmci_readl(host, DWMCI_RESP2); 493 cmd->response[2] = dwmci_readl(host, DWMCI_RESP1); 494 cmd->response[3] = dwmci_readl(host, DWMCI_RESP0); 495 } else { 496 cmd->response[0] = dwmci_readl(host, DWMCI_RESP0); 497 } 498 } 499 500 if (data) { 501 ret = dwmci_data_transfer(host, data); 502 503 /* only dma mode need it */ 504 if (!host->fifo_mode) { 505 ctrl = dwmci_readl(host, DWMCI_CTRL); 506 ctrl &= ~(DWMCI_DMA_EN); 507 dwmci_writel(host, DWMCI_CTRL, ctrl); 508 bounce_buffer_stop(&bbstate); 509 } 510 } 511 512 return ret; 513 } 514 515 #ifdef CONFIG_SPL_BLK_READ_PREPARE 516 #ifdef CONFIG_DM_MMC 517 static int dwmci_send_cmd_prepare(struct udevice *dev, struct mmc_cmd *cmd, 518 struct mmc_data *data) 519 { 520 struct mmc *mmc = mmc_get_mmc_dev(dev); 521 #else 522 static int dwmci_send_cmd_prepare(struct mmc *mmc, struct mmc_cmd *cmd, 523 struct mmc_data *data) 524 { 525 #endif 526 struct dwmci_host *host = mmc->priv; 527 struct dwmci_idmac *cur_idmac; 528 int ret = 0, flags = 0; 529 unsigned int timeout = 500; 530 u32 mask; 531 ulong start = get_timer(0); 532 struct bounce_buffer bbstate; 533 534 cur_idmac = malloc(ROUND(DIV_ROUND_UP(data->blocks, 8) * 535 sizeof(struct dwmci_idmac), 536 ARCH_DMA_MINALIGN) + ARCH_DMA_MINALIGN - 1); 537 if (!cur_idmac) 538 return -ENODATA; 539 540 while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) { 541 if (get_timer(start) > timeout) { 542 debug("%s: Timeout on data busy\n", __func__); 543 return -ETIMEDOUT; 544 } 545 } 546 547 dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL); 548 549 if (data) { 550 if (host->fifo_mode) { 551 dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize); 552 dwmci_writel(host, DWMCI_BYTCNT, 553 data->blocksize * data->blocks); 554 dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET); 555 } else { 556 if (data->flags == MMC_DATA_READ) { 557 bounce_buffer_start(&bbstate, (void *)data->dest, 558 data->blocksize * 559 data->blocks, GEN_BB_WRITE); 560 } else { 561 bounce_buffer_start(&bbstate, (void *)data->src, 562 data->blocksize * 563 data->blocks, GEN_BB_READ); 564 } 565 dwmci_prepare_data(host, data, cur_idmac, 566 bbstate.bounce_buffer); 567 } 568 } 569 570 dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg); 571 572 if (data) 573 flags = dwmci_set_transfer_mode(host, data); 574 575 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) 576 return -1; 577 578 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) 579 flags |= DWMCI_CMD_ABORT_STOP; 580 else 581 flags |= DWMCI_CMD_PRV_DAT_WAIT; 582 583 if (cmd->resp_type & MMC_RSP_PRESENT) { 584 flags |= DWMCI_CMD_RESP_EXP; 585 if (cmd->resp_type & MMC_RSP_136) 586 flags |= DWMCI_CMD_RESP_LENGTH; 587 } 588 589 if (cmd->resp_type & MMC_RSP_CRC) 590 flags |= DWMCI_CMD_CHECK_CRC; 591 592 flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG); 593 594 debug("Sending CMD%d\n", cmd->cmdidx); 595 596 dwmci_writel(host, DWMCI_CMD, flags); 597 598 timeout = dwmci_get_cto(host); 599 start = get_timer(0); 600 do { 601 mask = dwmci_readl(host, DWMCI_RINTSTS); 602 if (mask & DWMCI_INTMSK_CDONE) { 603 if (!data) 604 dwmci_writel(host, DWMCI_RINTSTS, mask); 605 break; 606 } 607 } while (!(get_timer(start) > timeout)); 608 609 if (get_timer(start) > timeout) { 610 debug("%s: Timeout.\n", __func__); 611 return -ETIMEDOUT; 612 } 613 614 if (mask & DWMCI_INTMSK_RTO) { 615 /* 616 * Timeout here is not necessarily fatal. (e)MMC cards 617 * will splat here when they receive CMD55 as they do 618 * not support this command and that is exactly the way 619 * to tell them apart from SD cards. Thus, this output 620 * below shall be debug(). eMMC cards also do not favor 621 * CMD8, please keep that in mind. 622 */ 623 debug("%s: Response Timeout.\n", __func__); 624 return -ETIMEDOUT; 625 } else if (mask & DWMCI_INTMSK_RE) { 626 debug("%s: Response Error.\n", __func__); 627 return -EIO; 628 } 629 630 if (cmd->resp_type & MMC_RSP_PRESENT) { 631 if (cmd->resp_type & MMC_RSP_136) { 632 cmd->response[0] = dwmci_readl(host, DWMCI_RESP3); 633 cmd->response[1] = dwmci_readl(host, DWMCI_RESP2); 634 cmd->response[2] = dwmci_readl(host, DWMCI_RESP1); 635 cmd->response[3] = dwmci_readl(host, DWMCI_RESP0); 636 } else { 637 cmd->response[0] = dwmci_readl(host, DWMCI_RESP0); 638 } 639 } 640 641 return ret; 642 } 643 #endif 644 645 static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) 646 { 647 u32 div, status; 648 int timeout = 10000; 649 unsigned long sclk; 650 651 if (freq == 0) 652 return 0; 653 /* 654 * If host->get_mmc_clk isn't defined, 655 * then assume that host->bus_hz is source clock value. 656 * host->bus_hz should be set by user. 657 */ 658 if (host->get_mmc_clk) 659 sclk = host->get_mmc_clk(host, freq); 660 else if (host->bus_hz) 661 sclk = host->bus_hz; 662 else { 663 debug("%s: Didn't get source clock value.\n", __func__); 664 return -EINVAL; 665 } 666 667 if (sclk == 0) 668 return -EINVAL; 669 670 if (sclk == freq) 671 div = 0; /* bypass mode */ 672 else 673 div = DIV_ROUND_UP(sclk, 2 * freq); 674 675 dwmci_writel(host, DWMCI_CLKENA, 0); 676 dwmci_writel(host, DWMCI_CLKSRC, 0); 677 678 dwmci_writel(host, DWMCI_CLKDIV, div); 679 dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT | 680 DWMCI_CMD_UPD_CLK | DWMCI_CMD_START); 681 682 do { 683 status = dwmci_readl(host, DWMCI_CMD); 684 if (timeout-- < 0) { 685 debug("%s: Timeout!\n", __func__); 686 return -ETIMEDOUT; 687 } 688 } while (status & DWMCI_CMD_START); 689 690 dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE | 691 DWMCI_CLKEN_LOW_PWR); 692 693 dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT | 694 DWMCI_CMD_UPD_CLK | DWMCI_CMD_START); 695 696 timeout = 10000; 697 do { 698 status = dwmci_readl(host, DWMCI_CMD); 699 if (timeout-- < 0) { 700 debug("%s: Timeout!\n", __func__); 701 return -ETIMEDOUT; 702 } 703 } while (status & DWMCI_CMD_START); 704 705 host->clock = freq; 706 707 return 0; 708 } 709 710 #ifdef CONFIG_DM_MMC 711 static bool dwmci_card_busy(struct udevice *dev) 712 { 713 struct mmc *mmc = mmc_get_mmc_dev(dev); 714 #else 715 static bool dwmci_card_busy(struct mmc *mmc) 716 { 717 #endif 718 u32 status; 719 struct dwmci_host *host = (struct dwmci_host *)mmc->priv; 720 721 /* 722 * Check the busy bit which is low when DAT[3:0] 723 * (the data lines) are 0000 724 */ 725 status = dwmci_readl(host, DWMCI_STATUS); 726 727 return !!(status & DWMCI_BUSY); 728 } 729 730 #ifdef CONFIG_DM_MMC 731 static int dwmci_execute_tuning(struct udevice *dev, u32 opcode) 732 { 733 struct mmc *mmc = mmc_get_mmc_dev(dev); 734 #else 735 static int dwmci_execute_tuning(struct mmc *mmc, u32 opcode) 736 { 737 #endif 738 struct dwmci_host *host = (struct dwmci_host *)mmc->priv; 739 740 if (!host->execute_tuning) 741 return -EIO; 742 743 return host->execute_tuning(host, opcode); 744 } 745 746 #ifdef CONFIG_DM_MMC 747 static int dwmci_set_ios(struct udevice *dev) 748 { 749 struct mmc *mmc = mmc_get_mmc_dev(dev); 750 #else 751 static int dwmci_set_ios(struct mmc *mmc) 752 { 753 #endif 754 struct dwmci_host *host = (struct dwmci_host *)mmc->priv; 755 u32 ctype, regs; 756 757 debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock); 758 759 dwmci_setup_bus(host, mmc->clock); 760 switch (mmc->bus_width) { 761 case 8: 762 ctype = DWMCI_CTYPE_8BIT; 763 break; 764 case 4: 765 ctype = DWMCI_CTYPE_4BIT; 766 break; 767 default: 768 ctype = DWMCI_CTYPE_1BIT; 769 break; 770 } 771 772 dwmci_writel(host, DWMCI_CTYPE, ctype); 773 774 regs = dwmci_readl(host, DWMCI_UHS_REG); 775 if (mmc_card_ddr(mmc)) 776 regs |= DWMCI_DDR_MODE; 777 else 778 regs &= ~DWMCI_DDR_MODE; 779 780 dwmci_writel(host, DWMCI_UHS_REG, regs); 781 782 if (host->clksel) 783 host->clksel(host); 784 785 return 0; 786 } 787 788 static int dwmci_init(struct mmc *mmc) 789 { 790 struct dwmci_host *host = mmc->priv; 791 uint32_t use_dma; 792 uint32_t verid; 793 794 #if defined(CONFIG_DM_GPIO) && (defined(CONFIG_SPL_GPIO_SUPPORT) || !defined(CONFIG_SPL_BUILD)) 795 struct gpio_desc pwr_en_gpio; 796 u32 delay_ms; 797 798 if (mmc_getcd(mmc) == 1 && 799 !gpio_request_by_name(mmc->dev, "pwr-en-gpios", 0, &pwr_en_gpio, GPIOD_IS_OUT)) { 800 dm_gpio_set_value(&pwr_en_gpio, 0); 801 pinctrl_select_state(mmc->dev, "idle"); 802 delay_ms = dev_read_u32_default(mmc->dev, "power-off-delay-ms", 200); 803 mdelay(delay_ms); 804 dm_gpio_set_value(&pwr_en_gpio, 1); 805 pinctrl_select_state(mmc->dev, "default"); 806 dm_gpio_free(mmc->dev, &pwr_en_gpio); 807 } 808 #endif 809 810 if (host->board_init) 811 host->board_init(host); 812 #ifdef CONFIG_ARCH_ROCKCHIP 813 if (host->dev_index == 0) 814 dwmci_writel(host, DWMCI_PWREN, 1); 815 else if (host->dev_index == 1) 816 dwmci_writel(host, DWMCI_PWREN, 0); 817 else 818 dwmci_writel(host, DWMCI_PWREN, 1); 819 #else 820 dwmci_writel(host, DWMCI_PWREN, 1); 821 #endif 822 823 verid = dwmci_readl(host, DWMCI_VERID) & 0x0000ffff; 824 if (verid >= DW_MMC_240A) 825 dwmci_writel(host, DWMCI_CARDTHRCTL, DWMCI_CDTHRCTRL_CONFIG); 826 827 if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) { 828 debug("%s[%d] Fail-reset!!\n", __func__, __LINE__); 829 return -EIO; 830 } 831 832 use_dma = SDMMC_GET_TRANS_MODE(dwmci_readl(host, DWMCI_HCON)); 833 if (use_dma == DMA_INTERFACE_IDMA) { 834 host->fifo_mode = 0; 835 } else { 836 host->fifo_mode = 1; 837 } 838 839 /* Enumerate at 400KHz */ 840 dwmci_setup_bus(host, mmc->cfg->f_min); 841 842 dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF); 843 dwmci_writel(host, DWMCI_INTMASK, 0); 844 845 dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF); 846 847 dwmci_writel(host, DWMCI_IDINTEN, 0); 848 dwmci_writel(host, DWMCI_BMOD, 1); 849 850 if (!host->fifoth_val) { 851 uint32_t fifo_size; 852 853 fifo_size = dwmci_readl(host, DWMCI_FIFOTH); 854 fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1; 855 host->fifoth_val = MSIZE(DWMCI_MSIZE) | 856 RX_WMARK(fifo_size / 2 - 1) | 857 TX_WMARK(fifo_size / 2); 858 } 859 dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val); 860 861 dwmci_writel(host, DWMCI_CLKENA, 0); 862 dwmci_writel(host, DWMCI_CLKSRC, 0); 863 864 return 0; 865 } 866 867 static int dwmci_get_cd(struct udevice *dev) 868 { 869 int ret = -1; 870 871 #if defined(CONFIG_DM_GPIO) && (defined(CONFIG_SPL_GPIO_SUPPORT) || !defined(CONFIG_SPL_BUILD)) 872 struct gpio_desc detect; 873 874 ret = gpio_request_by_name(dev, "cd-gpios", 0, &detect, GPIOD_IS_IN); 875 if (ret) { 876 return ret; 877 } 878 879 ret = !dm_gpio_get_value(&detect); 880 dm_gpio_free(dev, &detect); 881 #endif 882 return ret; 883 } 884 885 #ifdef CONFIG_DM_MMC 886 int dwmci_probe(struct udevice *dev) 887 { 888 struct mmc *mmc = mmc_get_mmc_dev(dev); 889 890 return dwmci_init(mmc); 891 } 892 893 const struct dm_mmc_ops dm_dwmci_ops = { 894 .card_busy = dwmci_card_busy, 895 .send_cmd = dwmci_send_cmd, 896 #ifdef CONFIG_SPL_BLK_READ_PREPARE 897 .send_cmd_prepare = dwmci_send_cmd_prepare, 898 #endif 899 .set_ios = dwmci_set_ios, 900 .get_cd = dwmci_get_cd, 901 .execute_tuning = dwmci_execute_tuning, 902 }; 903 904 #else 905 static const struct mmc_ops dwmci_ops = { 906 .card_busy = dwmci_card_busy, 907 .send_cmd = dwmci_send_cmd, 908 .set_ios = dwmci_set_ios, 909 .get_cd = dwmci_get_cd, 910 .init = dwmci_init, 911 .execute_tuning = dwmci_execute_tuning, 912 }; 913 #endif 914 915 void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host, 916 u32 max_clk, u32 min_clk) 917 { 918 cfg->name = host->name; 919 #ifndef CONFIG_DM_MMC 920 cfg->ops = &dwmci_ops; 921 #endif 922 cfg->f_min = min_clk; 923 cfg->f_max = max_clk; 924 925 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 926 927 cfg->host_caps = host->caps; 928 929 switch (host->buswidth) { 930 case 8: 931 cfg->host_caps |= MMC_MODE_8BIT | MMC_MODE_4BIT; 932 break; 933 case 4: 934 cfg->host_caps |= MMC_MODE_4BIT; 935 cfg->host_caps &= ~MMC_MODE_8BIT; 936 break; 937 case 1: 938 cfg->host_caps &= ~MMC_MODE_4BIT; 939 cfg->host_caps &= ~MMC_MODE_8BIT; 940 break; 941 default: 942 printf("Unsupported bus width: %d\n", host->buswidth); 943 break; 944 } 945 cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz; 946 947 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 948 } 949 950 #ifdef CONFIG_BLK 951 int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg) 952 { 953 return mmc_bind(dev, mmc, cfg); 954 } 955 #else 956 int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk) 957 { 958 dwmci_setup_cfg(&host->cfg, host, max_clk, min_clk); 959 960 host->mmc = mmc_create(&host->cfg, host); 961 if (host->mmc == NULL) 962 return -1; 963 964 return 0; 965 } 966 #endif 967