1 /* 2 * (C) Copyright 2020 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <dm.h> 8 #include <malloc.h> 9 #include "irq-internal.h" 10 11 typedef enum GPIOIntType { 12 GPIOLevelLow = 0, 13 GPIOLevelHigh, 14 GPIOEdgelFalling, 15 GPIOEdgelRising 16 } eGPIOIntType_t; 17 18 typedef enum eGPIOPinLevel { 19 GPIO_LOW = 0, 20 GPIO_HIGH 21 } eGPIOPinLevel_t; 22 23 typedef enum eGPIOPinDirection { 24 GPIO_IN = 0, 25 GPIO_OUT 26 } eGPIOPinDirection_t; 27 28 #define GPIO_SWPORT_DR 0x00 29 #define GPIO_SWPORT_DDR 0x08 30 #define GPIO_INTEN 0x10 31 #define GPIO_INTEN_L 0x10 32 #define GPIO_INTEN_H 0x14 33 #define GPIO_INTMASK 0x18 34 #define GPIO_INTTYPE_LEVEL 0x20 35 #define GPIO_INTTYPE_LEVEL_L 0x20 36 #define GPIO_INTTYPE_LEVEL_H 0x24 37 #define GPIO_INT_POLARITY 0x28 38 #define GPIO_DEBOUNCE 0x38 39 #define GPIO_INT_STATUS 0x50 40 #define GPIO_INT_RAWSTATUS 0x58 41 #define GPIO_PORTS_EOI 0x60 42 #define GPIO_EXT_PORT 0x70 43 44 #define WMSK_SETBIT(n) (n << 16 | n) 45 #define WMSK_CLRBIT(n) (n << 16) 46 #define REG_PLUS4(off, n) (off + (n >= BIT(16) ? 4 : 0)) 47 #define BIT_SUB16(n) (n >= BIT(16) ? (n >> 16) : n) 48 49 static inline unsigned offset_to_bit(unsigned offset) 50 { 51 return (1 << offset); 52 } 53 54 static void gpio_bit_op(void __iomem *regbase, unsigned int offset, 55 u32 bit, unsigned char flag) 56 { 57 u32 val; 58 59 offset = REG_PLUS4(offset, bit); 60 bit = BIT_SUB16(bit); 61 62 val = flag ? WMSK_SETBIT(bit) : WMSK_CLRBIT(bit); 63 writel(val, regbase + offset); 64 } 65 66 static int gpio_bit_rd(void __iomem *regbase, unsigned int offset, u32 bit) 67 { 68 offset = REG_PLUS4(offset, bit); 69 bit = BIT_SUB16(bit); 70 71 return readl(regbase + offset) & bit ? 1 : 0; 72 } 73 74 static void gpio_irq_unmask(void __iomem *regbase, unsigned int bit) 75 { 76 gpio_bit_op(regbase, GPIO_INTEN, bit, 1); 77 } 78 79 static void gpio_irq_mask(void __iomem *regbase, unsigned int bit) 80 { 81 gpio_bit_op(regbase, GPIO_INTEN, bit, 0); 82 } 83 84 static void gpio_irq_ack(void __iomem *regbase, unsigned int bit) 85 { 86 gpio_bit_op(regbase, GPIO_PORTS_EOI, bit, 1); 87 } 88 89 static void generic_gpio_handle_irq(int irq, void *data __always_unused) 90 { 91 struct gpio_bank *bank = gpio_id_to_bank(irq - IRQ_GPIO0); 92 unsigned gpio_irq, pin, h_pin, unmasked = 0; 93 u32 isr, ilr_l, ilr_h; 94 95 isr = readl(bank->regbase + GPIO_INT_STATUS); 96 ilr_l = readl(bank->regbase + GPIO_INTTYPE_LEVEL_L); 97 ilr_h = readl(bank->regbase + GPIO_INTTYPE_LEVEL_H); 98 gpio_irq = bank->irq_base; 99 100 while (isr) { 101 pin = fls(isr) - 1; 102 103 /* first mask and ack irq */ 104 gpio_irq_mask(bank->regbase, offset_to_bit(pin)); 105 gpio_irq_ack(bank->regbase, offset_to_bit(pin)); 106 107 /* 108 * If gpio is edge triggered, clear condition before executing 109 * the handler, so that we don't miss next edges trigger. 110 */ 111 if (pin < 16) { 112 if (ilr_l & (1 << pin)) { 113 unmasked = 1; 114 gpio_irq_unmask(bank->regbase, offset_to_bit(pin)); 115 } 116 } else { 117 h_pin = pin - 16; 118 if (ilr_h & (1 << h_pin)) { 119 unmasked = 1; 120 gpio_irq_unmask(bank->regbase, offset_to_bit(pin)); 121 } 122 } 123 __generic_gpio_handle_irq(gpio_irq + pin); 124 125 isr &= ~(1 << pin); 126 127 if (!unmasked) 128 gpio_irq_unmask(bank->regbase, offset_to_bit(pin)); 129 } 130 } 131 132 static void gpio_set_intr_type(void __iomem *regbase, 133 unsigned int bit, 134 eGPIOIntType_t type) 135 { 136 switch (type) { 137 case GPIOLevelLow: 138 gpio_bit_op(regbase, GPIO_INT_POLARITY, bit, 0); 139 gpio_bit_op(regbase, GPIO_INTTYPE_LEVEL, bit, 0); 140 break; 141 case GPIOLevelHigh: 142 gpio_bit_op(regbase, GPIO_INTTYPE_LEVEL, bit, 0); 143 gpio_bit_op(regbase, GPIO_INT_POLARITY, bit, 1); 144 break; 145 case GPIOEdgelFalling: 146 gpio_bit_op(regbase, GPIO_INTTYPE_LEVEL, bit, 1); 147 gpio_bit_op(regbase, GPIO_INT_POLARITY, bit, 0); 148 break; 149 case GPIOEdgelRising: 150 gpio_bit_op(regbase, GPIO_INTTYPE_LEVEL, bit, 1); 151 gpio_bit_op(regbase, GPIO_INT_POLARITY, bit, 1); 152 break; 153 } 154 } 155 156 static int gpio_get_intr_type(void __iomem *regbase, 157 unsigned int bit) 158 { 159 u32 polarity, level, magic = 0; 160 int type; 161 162 polarity = gpio_bit_rd(regbase, GPIO_INT_POLARITY, bit); 163 level = gpio_bit_rd(regbase, GPIO_INTTYPE_LEVEL, bit); 164 magic = (polarity << 1) | (level << 0); 165 166 switch (magic) { 167 case 0x00: 168 type = GPIOLevelLow; 169 break; 170 case 0x02: 171 type = GPIOLevelHigh; 172 break; 173 case 0x01: 174 type = GPIOEdgelFalling; 175 break; 176 case 0x03: 177 type = GPIOEdgelRising; 178 break; 179 default: 180 type = -EINVAL; 181 } 182 183 return type; 184 } 185 186 static int gpio_irq_set_type(int gpio_irq, unsigned int type) 187 { 188 int gpio = irq_to_gpio(gpio_irq); 189 struct gpio_bank *bank = gpio_to_bank(gpio); 190 eGPIOIntType_t int_type = 0; 191 192 if (!bank) 193 return -EINVAL; 194 195 gpio &= GPIO_PIN_MASK; 196 if (gpio >= bank->ngpio) 197 return -EINVAL; 198 199 switch (type) { 200 case IRQ_TYPE_EDGE_RISING: 201 int_type = GPIOEdgelRising; 202 break; 203 case IRQ_TYPE_EDGE_FALLING: 204 int_type = GPIOEdgelFalling; 205 break; 206 case IRQ_TYPE_LEVEL_HIGH: 207 int_type = GPIOLevelHigh; 208 break; 209 case IRQ_TYPE_LEVEL_LOW: 210 int_type = GPIOLevelLow; 211 break; 212 default: 213 return -EINVAL; 214 } 215 216 /* Before set interrupt type, gpio must set input */ 217 gpio_bit_op(bank->regbase, GPIO_SWPORT_DDR, 218 offset_to_bit(gpio), GPIO_IN); 219 gpio_set_intr_type(bank->regbase, offset_to_bit(gpio), int_type); 220 221 return 0; 222 } 223 224 static int gpio_irq_revert_type(int gpio_irq) 225 { 226 int gpio = irq_to_gpio(gpio_irq); 227 struct gpio_bank *bank = gpio_to_bank(gpio); 228 eGPIOIntType_t int_type = 0; 229 int type; 230 231 if (!bank) 232 return -EINVAL; 233 234 gpio &= GPIO_PIN_MASK; 235 if (gpio >= bank->ngpio) 236 return -EINVAL; 237 238 type = gpio_get_intr_type(bank->regbase, offset_to_bit(gpio)); 239 switch (type) { 240 case GPIOEdgelFalling: 241 int_type = GPIOEdgelRising; 242 break; 243 case GPIOEdgelRising: 244 int_type = GPIOEdgelFalling; 245 break; 246 case GPIOLevelHigh: 247 int_type = GPIOLevelLow; 248 break; 249 case GPIOLevelLow: 250 int_type = GPIOLevelHigh; 251 break; 252 default: 253 return -EINVAL; 254 } 255 256 gpio_set_intr_type(bank->regbase, offset_to_bit(gpio), int_type); 257 258 return 0; 259 } 260 261 static int gpio_irq_get_gpio_level(int gpio_irq) 262 { 263 int gpio = irq_to_gpio(gpio_irq); 264 struct gpio_bank *bank = gpio_to_bank(gpio); 265 266 if (!bank) 267 return -EINVAL; 268 269 gpio &= GPIO_PIN_MASK; 270 if (gpio >= bank->ngpio) 271 return -EINVAL; 272 273 /* NOTE: GPIO_EXT_PORT doesn't have _H/_L registers */ 274 return readl(bank->regbase + GPIO_EXT_PORT) & offset_to_bit(gpio) ? 1 : 0; 275 } 276 277 static int gpio_irq_enable(int gpio_irq) 278 { 279 int gpio = irq_to_gpio(gpio_irq); 280 struct gpio_bank *bank = gpio_to_bank(gpio); 281 282 if (!bank) 283 return -EINVAL; 284 285 gpio &= GPIO_PIN_MASK; 286 if (gpio >= bank->ngpio) 287 return -EINVAL; 288 289 gpio_irq_unmask(bank->regbase, offset_to_bit(gpio)); 290 291 if (bank->use_count == 0) 292 irq_handler_enable(IRQ_GPIO0 + bank->id); 293 bank->use_count++; 294 295 return 0; 296 } 297 298 static int gpio_irq_disable(int irq) 299 { 300 int gpio = irq_to_gpio(irq); 301 struct gpio_bank *bank = gpio_to_bank(gpio); 302 303 if (!bank) 304 return -EINVAL; 305 306 if (bank->use_count <= 0) 307 return 0; 308 309 gpio &= GPIO_PIN_MASK; 310 if (gpio >= bank->ngpio) 311 return -EINVAL; 312 313 gpio_irq_mask(bank->regbase, offset_to_bit(gpio)); 314 315 if (bank->use_count == 1) 316 irq_handler_disable(IRQ_GPIO0 + bank->id); 317 bank->use_count--; 318 319 return 0; 320 } 321 322 static int gpio_irq_init(void) 323 { 324 struct gpio_bank *bank = NULL; 325 int i = 0; 326 327 for (i = 0; i < GPIO_BANK_NUM; i++) { 328 struct udevice *dev; 329 330 dev = malloc(sizeof(*dev)); 331 if (!dev) 332 return -ENOMEM; 333 334 bank = gpio_id_to_bank(i); 335 if (bank) { 336 dev->name = bank->name; 337 338 /* disable gpio pin interrupt */ 339 writel(0xffff0000, bank->regbase + GPIO_INTEN_L); 340 writel(0xffff0000, bank->regbase + GPIO_INTEN_H); 341 342 /* register gpio group irq handler */ 343 irq_install_handler(IRQ_GPIO0 + bank->id, 344 (interrupt_handler_t *)generic_gpio_handle_irq, dev); 345 346 /* default disable all gpio group interrupt */ 347 irq_handler_disable(IRQ_GPIO0 + bank->id); 348 } 349 } 350 351 return 0; 352 } 353 354 static struct irq_chip gpio_irq_chip = { 355 .name = "gpio-irq-chip", 356 .irq_init = gpio_irq_init, 357 .irq_enable = gpio_irq_enable, 358 .irq_disable = gpio_irq_disable, 359 .irq_set_type = gpio_irq_set_type, 360 .irq_revert_type = gpio_irq_revert_type, 361 .irq_get_gpio_level = gpio_irq_get_gpio_level, 362 }; 363 364 struct irq_chip *arch_gpio_get_irqchip(void) 365 { 366 return &gpio_irq_chip; 367 } 368 369