1 /* 2 * (C) Copyright 2015 Google, Inc 3 * 4 * (C) Copyright 2008-2014 Rockchip Electronics 5 * Peter, Software Engineering, <superpeter.cai@gmail.com>. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <clk.h> 12 #include <dm.h> 13 #include <errno.h> 14 #include <i2c.h> 15 #include <asm/io.h> 16 #include <asm/arch/clock.h> 17 #include <asm/arch/i2c.h> 18 #include <asm/arch/periph.h> 19 #include <dm/pinctrl.h> 20 #include <linux/sizes.h> 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 /* i2c timerout */ 25 #define I2C_TIMEOUT_MS 100 26 #define I2C_RETRY_COUNT 3 27 28 /* rk i2c fifo max transfer bytes */ 29 #define RK_I2C_FIFO_SIZE 32 30 31 struct rk_i2c { 32 struct clk clk; 33 struct i2c_regs *regs; 34 unsigned int speed; 35 }; 36 37 static inline void rk_i2c_get_div(int div, int *divh, int *divl) 38 { 39 *divl = div / 2; 40 if (div % 2 == 0) 41 *divh = div / 2; 42 else 43 *divh = DIV_ROUND_UP(div, 2); 44 } 45 46 /* 47 * SCL Divisor = 8 * (CLKDIVL+1 + CLKDIVH+1) 48 * SCL = PCLK / SCLK Divisor 49 * i2c_rate = PCLK 50 */ 51 static void rk_i2c_set_clk(struct rk_i2c *i2c, uint32_t scl_rate) 52 { 53 uint32_t i2c_rate; 54 int div, divl, divh; 55 56 /* First get i2c rate from pclk */ 57 i2c_rate = clk_get_rate(&i2c->clk); 58 59 div = DIV_ROUND_UP(i2c_rate, scl_rate * 8) - 2; 60 divh = 0; 61 divl = 0; 62 if (div >= 0) 63 rk_i2c_get_div(div, &divh, &divl); 64 writel(I2C_CLKDIV_VAL(divl, divh), &i2c->regs->clkdiv); 65 66 debug("rk_i2c_set_clk: i2c rate = %d, scl rate = %d\n", i2c_rate, 67 scl_rate); 68 debug("set i2c clk div = %d, divh = %d, divl = %d\n", div, divh, divl); 69 debug("set clk(I2C_CLKDIV: 0x%08x)\n", readl(&i2c->regs->clkdiv)); 70 } 71 72 static void rk_i2c_show_regs(struct i2c_regs *regs) 73 { 74 #ifdef DEBUG 75 uint i; 76 77 debug("i2c_con: 0x%08x\n", readl(®s->con)); 78 debug("i2c_clkdiv: 0x%08x\n", readl(®s->clkdiv)); 79 debug("i2c_mrxaddr: 0x%08x\n", readl(®s->mrxaddr)); 80 debug("i2c_mrxraddR: 0x%08x\n", readl(®s->mrxraddr)); 81 debug("i2c_mtxcnt: 0x%08x\n", readl(®s->mtxcnt)); 82 debug("i2c_mrxcnt: 0x%08x\n", readl(®s->mrxcnt)); 83 debug("i2c_ien: 0x%08x\n", readl(®s->ien)); 84 debug("i2c_ipd: 0x%08x\n", readl(®s->ipd)); 85 debug("i2c_fcnt: 0x%08x\n", readl(®s->fcnt)); 86 for (i = 0; i < 8; i++) 87 debug("i2c_txdata%d: 0x%08x\n", i, readl(®s->txdata[i])); 88 for (i = 0; i < 8; i++) 89 debug("i2c_rxdata%d: 0x%08x\n", i, readl(®s->rxdata[i])); 90 #endif 91 } 92 93 static int rk_i2c_send_start_bit(struct rk_i2c *i2c, u32 con) 94 { 95 struct i2c_regs *regs = i2c->regs; 96 ulong start; 97 98 debug("I2c Send Start bit.\n"); 99 writel(I2C_IPD_ALL_CLEAN, ®s->ipd); 100 101 writel(I2C_STARTIEN, ®s->ien); 102 writel(I2C_CON_EN | I2C_CON_START | con, ®s->con); 103 104 start = get_timer(0); 105 while (1) { 106 if (readl(®s->ipd) & I2C_STARTIPD) { 107 writel(I2C_STARTIPD, ®s->ipd); 108 break; 109 } 110 if (get_timer(start) > I2C_TIMEOUT_MS) { 111 debug("I2C Send Start Bit Timeout\n"); 112 rk_i2c_show_regs(regs); 113 return -ETIMEDOUT; 114 } 115 udelay(1); 116 } 117 118 /* clean start bit */ 119 writel(I2C_CON_EN | con, ®s->con); 120 121 return 0; 122 } 123 124 static int rk_i2c_send_stop_bit(struct rk_i2c *i2c) 125 { 126 struct i2c_regs *regs = i2c->regs; 127 ulong start; 128 129 debug("I2c Send Stop bit.\n"); 130 writel(I2C_IPD_ALL_CLEAN, ®s->ipd); 131 132 writel(I2C_CON_EN | I2C_CON_STOP, ®s->con); 133 writel(I2C_CON_STOP, ®s->ien); 134 135 start = get_timer(0); 136 while (1) { 137 if (readl(®s->ipd) & I2C_STOPIPD) { 138 writel(I2C_STOPIPD, ®s->ipd); 139 break; 140 } 141 if (get_timer(start) > I2C_TIMEOUT_MS) { 142 debug("I2C Send Start Bit Timeout\n"); 143 rk_i2c_show_regs(regs); 144 return -ETIMEDOUT; 145 } 146 udelay(1); 147 } 148 149 udelay(1); 150 return 0; 151 } 152 153 static inline void rk_i2c_disable(struct rk_i2c *i2c) 154 { 155 writel(0, &i2c->regs->ien); 156 writel(I2C_IPD_ALL_CLEAN, &i2c->regs->ipd); 157 writel(0, &i2c->regs->con); 158 } 159 160 static int rk_i2c_read(struct rk_i2c *i2c, uchar chip, uint reg, uint r_len, 161 uchar *buf, uint b_len, bool snd) 162 { 163 struct i2c_regs *regs = i2c->regs; 164 uchar *pbuf = buf; 165 uint bytes_remain_len = b_len; 166 uint bytes_xferred = 0; 167 uint words_xferred = 0; 168 ulong start; 169 uint con = 0; 170 uint rxdata; 171 uint i, j; 172 int err = 0; 173 bool snd_chunk = false; 174 175 debug("rk_i2c_read: chip = %d, reg = %d, r_len = %d, b_len = %d\n", 176 chip, reg, r_len, b_len); 177 178 /* If the second message for TRX read, resetting internal state. */ 179 if (snd) 180 writel(0, ®s->con); 181 182 writel(I2C_MRXADDR_SET(1, chip << 1 | 1), ®s->mrxaddr); 183 if (r_len == 0) { 184 writel(0, ®s->mrxraddr); 185 } else if (r_len < 4) { 186 writel(I2C_MRXRADDR_SET(r_len, reg), ®s->mrxraddr); 187 } else { 188 debug("I2C Read: addr len %d not supported\n", r_len); 189 return -EIO; 190 } 191 192 while (bytes_remain_len) { 193 if (bytes_remain_len > RK_I2C_FIFO_SIZE) { 194 con = I2C_CON_EN; 195 bytes_xferred = 32; 196 } else { 197 /* 198 * The hw can read up to 32 bytes at a time. If we need 199 * more than one chunk, send an ACK after the last byte. 200 */ 201 con = I2C_CON_EN | I2C_CON_LASTACK; 202 bytes_xferred = bytes_remain_len; 203 } 204 words_xferred = DIV_ROUND_UP(bytes_xferred, 4); 205 206 /* 207 * make sure we are in plain RX mode if we read a second chunk; 208 * and first rx read need to send start bit. 209 */ 210 if (snd_chunk) { 211 con |= I2C_CON_MOD(I2C_MODE_RX); 212 writel(con, ®s->con); 213 } else { 214 con |= I2C_CON_MOD(I2C_MODE_TRX); 215 err = rk_i2c_send_start_bit(i2c, con); 216 if (err) 217 return err; 218 } 219 220 writel(I2C_MBRFIEN | I2C_NAKRCVIEN, ®s->ien); 221 writel(bytes_xferred, ®s->mrxcnt); 222 223 start = get_timer(0); 224 while (1) { 225 if (readl(®s->ipd) & I2C_NAKRCVIPD) { 226 writel(I2C_NAKRCVIPD, ®s->ipd); 227 err = -EREMOTEIO; 228 } 229 if (readl(®s->ipd) & I2C_MBRFIPD) { 230 writel(I2C_MBRFIPD, ®s->ipd); 231 break; 232 } 233 if (get_timer(start) > I2C_TIMEOUT_MS) { 234 debug("I2C Read Data Timeout\n"); 235 err = -ETIMEDOUT; 236 rk_i2c_show_regs(regs); 237 goto i2c_exit; 238 } 239 udelay(1); 240 } 241 242 for (i = 0; i < words_xferred; i++) { 243 rxdata = readl(®s->rxdata[i]); 244 debug("I2c Read RXDATA[%d] = 0x%x\n", i, rxdata); 245 for (j = 0; j < 4; j++) { 246 if ((i * 4 + j) == bytes_xferred) 247 break; 248 *pbuf++ = (rxdata >> (j * 8)) & 0xff; 249 } 250 } 251 252 bytes_remain_len -= bytes_xferred; 253 snd_chunk = true; 254 debug("I2C Read bytes_remain_len %d\n", bytes_remain_len); 255 } 256 257 i2c_exit: 258 return err; 259 } 260 261 static int rk_i2c_write(struct rk_i2c *i2c, uchar chip, uint reg, uint r_len, 262 uchar *buf, uint b_len) 263 { 264 struct i2c_regs *regs = i2c->regs; 265 int err = 0; 266 uchar *pbuf = buf; 267 uint bytes_remain_len = b_len + r_len + 1; 268 uint bytes_xferred = 0; 269 uint words_xferred = 0; 270 bool next = false; 271 ulong start; 272 uint txdata; 273 uint i, j; 274 275 debug("rk_i2c_write: chip = %d, reg = %d, r_len = %d, b_len = %d\n", 276 chip, reg, r_len, b_len); 277 278 while (bytes_remain_len) { 279 if (bytes_remain_len > RK_I2C_FIFO_SIZE) 280 bytes_xferred = RK_I2C_FIFO_SIZE; 281 else 282 bytes_xferred = bytes_remain_len; 283 words_xferred = DIV_ROUND_UP(bytes_xferred, 4); 284 285 for (i = 0; i < words_xferred; i++) { 286 txdata = 0; 287 for (j = 0; j < 4; j++) { 288 if ((i * 4 + j) == bytes_xferred) 289 break; 290 291 if (i == 0 && j == 0 && pbuf == buf) { 292 txdata |= (chip << 1); 293 } else if (i == 0 && j <= r_len && pbuf == buf) { 294 txdata |= (reg & 295 (0xff << ((j - 1) * 8))) << 8; 296 } else { 297 txdata |= (*pbuf++)<<(j * 8); 298 } 299 } 300 writel(txdata, ®s->txdata[i]); 301 debug("I2c Write TXDATA[%d] = 0x%08x\n", i, txdata); 302 } 303 304 /* If the write is the first, need to send start bit */ 305 if (!next) { 306 err = rk_i2c_send_start_bit(i2c, I2C_CON_EN | I2C_CON_MOD(I2C_MODE_TX)); 307 if (err) 308 return err; 309 next = true; 310 } else { 311 writel(I2C_CON_EN | I2C_CON_MOD(I2C_MODE_TX), ®s->con); 312 } 313 writel(I2C_MBTFIEN | I2C_NAKRCVIEN, ®s->ien); 314 writel(bytes_xferred, ®s->mtxcnt); 315 316 start = get_timer(0); 317 while (1) { 318 if (readl(®s->ipd) & I2C_NAKRCVIPD) { 319 writel(I2C_NAKRCVIPD, ®s->ipd); 320 err = -EREMOTEIO; 321 } 322 if (readl(®s->ipd) & I2C_MBTFIPD) { 323 writel(I2C_MBTFIPD, ®s->ipd); 324 break; 325 } 326 if (get_timer(start) > I2C_TIMEOUT_MS) { 327 debug("I2C Write Data Timeout\n"); 328 err = -ETIMEDOUT; 329 rk_i2c_show_regs(regs); 330 goto i2c_exit; 331 } 332 udelay(1); 333 } 334 335 bytes_remain_len -= bytes_xferred; 336 debug("I2C Write bytes_remain_len %d\n", bytes_remain_len); 337 } 338 339 i2c_exit: 340 return err; 341 } 342 343 static int rockchip_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, 344 int nmsgs) 345 { 346 struct rk_i2c *i2c = dev_get_priv(bus); 347 bool snd = false; /* second message for TRX read */ 348 int ret; 349 350 debug("i2c_xfer: %d messages\n", nmsgs); 351 if (nmsgs > 2 || ((nmsgs == 2) && (msg->flags & I2C_M_RD))) { 352 debug("Not support more messages now, split them\n"); 353 return -EINVAL; 354 } 355 356 for (; nmsgs > 0; nmsgs--, msg++) { 357 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len); 358 359 if (msg->flags & I2C_M_RD) { 360 /* If snd is true, it is TRX mode. */ 361 ret = rk_i2c_read(i2c, msg->addr, 0, 0, msg->buf, 362 msg->len, snd); 363 } else { 364 snd = true; 365 ret = rk_i2c_write(i2c, msg->addr, 0, 0, msg->buf, 366 msg->len); 367 } 368 369 if (ret) { 370 debug("i2c_write: error sending\n"); 371 ret = -EREMOTEIO; 372 goto exit; 373 } 374 } 375 376 exit: 377 rk_i2c_send_stop_bit(i2c); 378 rk_i2c_disable(i2c); 379 380 return ret; 381 } 382 383 int rockchip_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) 384 { 385 struct rk_i2c *i2c = dev_get_priv(bus); 386 387 rk_i2c_set_clk(i2c, speed); 388 389 return 0; 390 } 391 392 static int rockchip_i2c_ofdata_to_platdata(struct udevice *bus) 393 { 394 struct rk_i2c *priv = dev_get_priv(bus); 395 int ret; 396 397 ret = clk_get_by_index(bus, 0, &priv->clk); 398 if (ret < 0) { 399 debug("%s: Could not get clock for %s: %d\n", __func__, 400 bus->name, ret); 401 return ret; 402 } 403 404 return 0; 405 } 406 407 static int rockchip_i2c_probe(struct udevice *bus) 408 { 409 struct rk_i2c *priv = dev_get_priv(bus); 410 411 priv->regs = dev_read_addr_ptr(bus); 412 413 return 0; 414 } 415 416 static const struct dm_i2c_ops rockchip_i2c_ops = { 417 .xfer = rockchip_i2c_xfer, 418 .set_bus_speed = rockchip_i2c_set_bus_speed, 419 }; 420 421 static const struct udevice_id rockchip_i2c_ids[] = { 422 { .compatible = "rockchip,rk3066-i2c" }, 423 { .compatible = "rockchip,rk3188-i2c" }, 424 { .compatible = "rockchip,rk3288-i2c" }, 425 { .compatible = "rockchip,rk3328-i2c" }, 426 { .compatible = "rockchip,rk3399-i2c" }, 427 { .compatible = "rockchip,rk3228-i2c" }, 428 { .compatible = "rockchip,rv1108-i2c" }, 429 { } 430 }; 431 432 U_BOOT_DRIVER(i2c_rockchip) = { 433 .name = "i2c_rockchip", 434 .id = UCLASS_I2C, 435 .of_match = rockchip_i2c_ids, 436 .ofdata_to_platdata = rockchip_i2c_ofdata_to_platdata, 437 .probe = rockchip_i2c_probe, 438 .priv_auto_alloc_size = sizeof(struct rk_i2c), 439 .ops = &rockchip_i2c_ops, 440 }; 441