1 /* 2 * Copyright (c) 2012 The Chromium OS Authors. 3 * See file CREDITS for list of people who contributed to this 4 * project. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * MA 02111-1307 USA 20 */ 21 22 /* 23 * This is a GPIO driver for Intel ICH6 and later. The x86 GPIOs are accessed 24 * through the PCI bus. Each PCI device has 256 bytes of configuration space, 25 * consisting of a standard header and a device-specific set of registers. PCI 26 * bus 0, device 31, function 0 gives us access to the chipset GPIOs (among 27 * other things). Within the PCI configuration space, the GPIOBASE register 28 * tells us where in the device's I/O region we can find more registers to 29 * actually access the GPIOs. 30 * 31 * PCI bus/device/function 0:1f:0 => PCI config registers 32 * PCI config register "GPIOBASE" 33 * PCI I/O space + [GPIOBASE] => start of GPIO registers 34 * GPIO registers => gpio pin function, direction, value 35 */ 36 37 #include <common.h> 38 #include <pci.h> 39 #include <asm/gpio.h> 40 #include <asm/io.h> 41 42 /* Where in config space is the register that points to the GPIO registers? */ 43 #define PCI_CFG_GPIOBASE 0x48 44 45 /* 46 * There are often more than 32 GPIOs, depending on the ICH version. 47 * For now, we just support bank 0 because it's the same for all. 48 */ 49 #define GPIO_MAX 31 50 51 /* Within the I/O space, where are the registers to control the GPIOs? */ 52 #define OFS_GPIO_USE_SEL 0x00 53 #define OFS_GPIO_IO_SEL 0x04 54 #define OFS_GP_LVL 0x0C 55 56 static pci_dev_t dev; /* handle for 0:1f:0 */ 57 static u32 gpiobase; /* offset into I/O space */ 58 static int found_it_once; /* valid GPIO device? */ 59 static int in_use[GPIO_MAX]; /* "lock" for access to pins */ 60 61 static int gpio_init(void) 62 { 63 u8 tmpbyte; 64 u16 tmpword; 65 u32 tmplong; 66 67 /* Have we already done this? */ 68 if (found_it_once) 69 return 0; 70 71 /* Where should it be? */ 72 dev = PCI_BDF(0, 0x1f, 0); 73 74 /* Is the device present? */ 75 pci_read_config_word(dev, PCI_VENDOR_ID, &tmpword); 76 if (tmpword != PCI_VENDOR_ID_INTEL) { 77 debug("%s: wrong VendorID\n", __func__); 78 return -1; 79 } 80 /* 81 * We'd like to check the Device ID too, but pretty much any 82 * value is either a) correct with slight differences, or b) 83 * correct but undocumented. We'll have to check other things 84 * instead... 85 */ 86 87 /* I/O should already be enabled (it's a RO bit). */ 88 pci_read_config_word(dev, PCI_COMMAND, &tmpword); 89 if (!(tmpword & PCI_COMMAND_IO)) { 90 debug("%s: device IO not enabled\n", __func__); 91 return -1; 92 } 93 94 /* Header Type must be normal (bits 6-0 only; see spec.) */ 95 pci_read_config_byte(dev, PCI_HEADER_TYPE, &tmpbyte); 96 if ((tmpbyte & 0x7f) != PCI_HEADER_TYPE_NORMAL) { 97 debug("%s: invalid Header type\n", __func__); 98 return -1; 99 } 100 101 /* Base Class must be a bridge device */ 102 pci_read_config_byte(dev, PCI_CLASS_CODE, &tmpbyte); 103 if (tmpbyte != PCI_CLASS_CODE_BRIDGE) { 104 debug("%s: invalid class\n", __func__); 105 return -1; 106 } 107 /* Sub Class must be ISA */ 108 pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &tmpbyte); 109 if (tmpbyte != PCI_CLASS_SUB_CODE_BRIDGE_ISA) { 110 debug("%s: invalid subclass\n", __func__); 111 return -1; 112 } 113 114 /* Programming Interface must be 0x00 (no others exist) */ 115 pci_read_config_byte(dev, PCI_CLASS_PROG, &tmpbyte); 116 if (tmpbyte != 0x00) { 117 debug("%s: invalid interface type\n", __func__); 118 return -1; 119 } 120 121 /* 122 * GPIOBASE moved to its current offset with ICH6, but prior to 123 * that it was unused (or undocumented). Check that it looks 124 * okay: not all ones or zeros, and mapped to I/O space (bit 0). 125 */ 126 pci_read_config_dword(dev, PCI_CFG_GPIOBASE, &tmplong); 127 if (tmplong == 0x00000000 || tmplong == 0xffffffff || 128 !(tmplong & 0x00000001)) { 129 debug("%s: unexpected GPIOBASE value\n", __func__); 130 return -1; 131 } 132 133 /* 134 * Okay, I guess we're looking at the right device. The actual 135 * GPIO registers are in the PCI device's I/O space, starting 136 * at the offset that we just read. Bit 0 indicates that it's 137 * an I/O address, not a memory address, so mask that off. 138 */ 139 gpiobase = tmplong & 0xfffffffe; 140 141 /* Finally. These are the droids we're looking for. */ 142 found_it_once = 1; 143 return 0; 144 } 145 146 int gpio_request(unsigned gpio, const char *label /* UNUSED */) 147 { 148 u32 tmplong; 149 150 /* Are we doing it wrong? */ 151 if (gpio > GPIO_MAX || in_use[gpio]) { 152 debug("%s: gpio unavailable\n", __func__); 153 return -1; 154 } 155 156 /* Is the hardware ready? */ 157 if (gpio_init()) { 158 debug("%s: gpio_init failed\n", __func__); 159 return -1; 160 } 161 162 /* 163 * Make sure that the GPIO pin we want isn't already in use for some 164 * built-in hardware function. We have to check this for every 165 * requested pin. 166 */ 167 tmplong = inl(gpiobase + OFS_GPIO_USE_SEL); 168 if (!(tmplong & (1UL << gpio))) { 169 debug("%s: reserved for internal use\n", __func__); 170 return -1; 171 } 172 173 in_use[gpio] = 1; 174 return 0; 175 } 176 177 int gpio_free(unsigned gpio) 178 { 179 if (gpio > GPIO_MAX || !in_use[gpio]) { 180 debug("%s: gpio unavailable\n", __func__); 181 return -1; 182 } 183 in_use[gpio] = 0; 184 return 0; 185 } 186 187 int gpio_direction_input(unsigned gpio) 188 { 189 u32 tmplong; 190 191 if (gpio > GPIO_MAX || !in_use[gpio]) { 192 debug("%s: gpio unavailable\n", __func__); 193 return -1; 194 } 195 tmplong = inl(gpiobase + OFS_GPIO_IO_SEL); 196 tmplong |= (1UL << gpio); 197 outl(gpiobase + OFS_GPIO_IO_SEL, tmplong); 198 return 0; 199 } 200 201 int gpio_direction_output(unsigned gpio, int value) 202 { 203 u32 tmplong; 204 205 if (gpio > GPIO_MAX || !in_use[gpio]) { 206 debug("%s: gpio unavailable\n", __func__); 207 return -1; 208 } 209 tmplong = inl(gpiobase + OFS_GPIO_IO_SEL); 210 tmplong &= ~(1UL << gpio); 211 outl(gpiobase + OFS_GPIO_IO_SEL, tmplong); 212 return 0; 213 } 214 215 int gpio_get_value(unsigned gpio) 216 { 217 u32 tmplong; 218 219 if (gpio > GPIO_MAX || !in_use[gpio]) { 220 debug("%s: gpio unavailable\n", __func__); 221 return -1; 222 } 223 tmplong = inl(gpiobase + OFS_GP_LVL); 224 return (tmplong & (1UL << gpio)) ? 1 : 0; 225 } 226 227 int gpio_set_value(unsigned gpio, int value) 228 { 229 u32 tmplong; 230 231 if (gpio > GPIO_MAX || !in_use[gpio]) { 232 debug("%s: gpio unavailable\n", __func__); 233 return -1; 234 } 235 tmplong = inl(gpiobase + OFS_GP_LVL); 236 if (value) 237 tmplong |= (1UL << gpio); 238 else 239 tmplong &= ~(1UL << gpio); 240 outl(gpiobase + OFS_GP_LVL, tmplong); 241 return 0; 242 } 243