1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2022 Fuzhou Rockchip Electronics Co., Ltd 4 * Author: Joseph Chen <chenjh@rock-chips.com> 5 */ 6 7 #include <common.h> 8 #include <clk-uclass.h> 9 #include <dm.h> 10 #include <syscon.h> 11 #include <asm/arch/clock.h> 12 #include <asm/arch/cru_rk3528.h> 13 #include <asm/arch/grf_rk3528.h> 14 #include <asm/arch/hardware.h> 15 #include <asm/io.h> 16 #include <dm/lists.h> 17 #include <dt-bindings/clock/rk3528-cru.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) 22 23 /* 24 * PLL attention. 25 * 26 * [FRAC PLL]: GPLL, PPLL, DPLL 27 * - frac mode: refdiv can be 1 or 2 only 28 * - int mode: refdiv has no special limit 29 * - VCO range: [950, 3800] MHZ 30 * 31 * [INT PLL]: CPLL, APLL 32 * - int mode: refdiv can be 1 or 2 only 33 * - VCO range: [475, 1900] MHZ 34 * 35 * [PPLL]: normal mode only. 36 * 37 */ 38 static struct rockchip_pll_rate_table rk3528_pll_rates[] = { 39 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ 40 RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0), 41 RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0), 42 RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0), 43 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), 44 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), 45 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), 46 RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), 47 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), 48 RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0), /* GPLL */ 49 RK3036_PLL_RATE(1092000000, 2, 91, 1, 1, 1, 0), 50 RK3036_PLL_RATE(1008000000, 1, 42, 1, 1, 1, 0), 51 RK3036_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0), /* PPLL */ 52 RK3036_PLL_RATE(996000000, 2, 83, 1, 1, 1, 0), /* CPLL */ 53 RK3036_PLL_RATE(960000000, 1, 40, 1, 1, 1, 0), 54 RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0), 55 RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), 56 RK3036_PLL_RATE(600000000, 1, 50, 2, 1, 1, 0), 57 RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0), 58 RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0), 59 RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0), 60 RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0), 61 RK3036_PLL_RATE(96000000, 1, 24, 3, 2, 1, 0), 62 { /* sentinel */ }, 63 }; 64 65 static struct rockchip_pll_clock rk3528_pll_clks[] = { 66 [APLL] = PLL(pll_rk3328, PLL_APLL, RK3528_PLL_CON(0), 67 RK3528_MODE_CON, 0, 10, 0, rk3528_pll_rates), 68 69 [CPLL] = PLL(pll_rk3328, PLL_CPLL, RK3528_PLL_CON(8), 70 RK3528_MODE_CON, 2, 10, 0, rk3528_pll_rates), 71 72 [GPLL] = PLL(pll_rk3328, PLL_GPLL, RK3528_PLL_CON(24), 73 RK3528_MODE_CON, 4, 10, 0, rk3528_pll_rates), 74 75 [PPLL] = PLL(pll_rk3328, PLL_PPLL, RK3528_PCIE_PLL_CON(32), 76 RK3528_MODE_CON, 6, 10, ROCKCHIP_PLL_FIXED_MODE, rk3528_pll_rates), 77 78 [DPLL] = PLL(pll_rk3328, PLL_DPLL, RK3528_DDRPHY_PLL_CON(16), 79 RK3528_DDRPHY_MODE_CON, 0, 10, 0, rk3528_pll_rates), 80 }; 81 82 #define RK3528_CPUCLK_RATE(_rate, _aclk_m_core, _pclk_dbg) \ 83 { \ 84 .rate = _rate##U, \ 85 .aclk_div = (_aclk_m_core), \ 86 .pclk_div = (_pclk_dbg), \ 87 } 88 89 /* sign-off: _aclk_m_core: 550M, _pclk_dbg: 137.5M, */ 90 static struct rockchip_cpu_rate_table rk3528_cpu_rates[] = { 91 RK3528_CPUCLK_RATE(1896000000, 1, 13), 92 RK3528_CPUCLK_RATE(1800000000, 1, 12), 93 RK3528_CPUCLK_RATE(1704000000, 1, 11), 94 RK3528_CPUCLK_RATE(1608000000, 1, 11), 95 RK3528_CPUCLK_RATE(1512000000, 1, 11), 96 RK3528_CPUCLK_RATE(1416000000, 1, 9), 97 RK3528_CPUCLK_RATE(1296000000, 1, 8), 98 RK3528_CPUCLK_RATE(1200000000, 1, 8), 99 RK3528_CPUCLK_RATE(1188000000, 1, 8), 100 RK3528_CPUCLK_RATE(1092000000, 1, 7), 101 RK3528_CPUCLK_RATE(1008000000, 1, 6), 102 RK3528_CPUCLK_RATE(1000000000, 1, 6), 103 RK3528_CPUCLK_RATE(996000000, 1, 6), 104 RK3528_CPUCLK_RATE(960000000, 1, 6), 105 RK3528_CPUCLK_RATE(912000000, 1, 6), 106 RK3528_CPUCLK_RATE(816000000, 1, 5), 107 RK3528_CPUCLK_RATE(600000000, 1, 3), 108 RK3528_CPUCLK_RATE(594000000, 1, 3), 109 RK3528_CPUCLK_RATE(408000000, 1, 2), 110 RK3528_CPUCLK_RATE(312000000, 1, 2), 111 RK3528_CPUCLK_RATE(216000000, 1, 1), 112 RK3528_CPUCLK_RATE(96000000, 1, 0), 113 }; 114 115 #ifndef CONFIG_SPL_BUILD 116 #define RK3528_CLK_DUMP(_id, _name) \ 117 { \ 118 .id = _id, \ 119 .name = _name, \ 120 } 121 122 static const struct rk3528_clk_info clks_dump[] = { 123 RK3528_CLK_DUMP(PLL_APLL, "apll"), 124 RK3528_CLK_DUMP(PLL_GPLL, "gpll"), 125 RK3528_CLK_DUMP(PLL_CPLL, "cpll"), 126 RK3528_CLK_DUMP(PLL_DPLL, "dpll"), 127 RK3528_CLK_DUMP(PLL_PPLL, "ppll"), 128 RK3528_CLK_DUMP(CLK_MATRIX_50M_SRC, "clk_50m"), 129 RK3528_CLK_DUMP(CLK_MATRIX_100M_SRC, "clk_100m"), 130 RK3528_CLK_DUMP(CLK_MATRIX_150M_SRC, "clk_150m"), 131 RK3528_CLK_DUMP(CLK_MATRIX_200M_SRC, "clk_200m"), 132 RK3528_CLK_DUMP(CLK_MATRIX_250M_SRC, "clk_250m"), 133 RK3528_CLK_DUMP(CLK_MATRIX_300M_SRC, "clk_300m"), 134 RK3528_CLK_DUMP(CLK_MATRIX_339M_SRC, "clk_339m"), 135 RK3528_CLK_DUMP(CLK_MATRIX_400M_SRC, "clk_400m"), 136 RK3528_CLK_DUMP(CLK_MATRIX_500M_SRC, "clk_500m"), 137 RK3528_CLK_DUMP(CLK_MATRIX_600M_SRC, "clk_600m"), 138 RK3528_CLK_DUMP(CLK_PPLL_50M_MATRIX, "clk_ppll_50m"), 139 RK3528_CLK_DUMP(CLK_PPLL_100M_MATRIX, "clk_ppll_100m"), 140 RK3528_CLK_DUMP(CLK_PPLL_125M_MATRIX, "clk_ppll_125m"), 141 }; 142 #endif 143 144 /* 145 * 146 * rational_best_approximation(31415, 10000, 147 * (1 << 8) - 1, (1 << 5) - 1, &n, &d); 148 * 149 * you may look at given_numerator as a fixed point number, 150 * with the fractional part size described in given_denominator. 151 * 152 * for theoretical background, see: 153 * http://en.wikipedia.org/wiki/Continued_fraction 154 */ 155 static void rational_best_approximation(unsigned long given_numerator, 156 unsigned long given_denominator, 157 unsigned long max_numerator, 158 unsigned long max_denominator, 159 unsigned long *best_numerator, 160 unsigned long *best_denominator) 161 { 162 unsigned long n, d, n0, d0, n1, d1; 163 164 n = given_numerator; 165 d = given_denominator; 166 n0 = 0; 167 d1 = 0; 168 n1 = 1; 169 d0 = 1; 170 for (;;) { 171 unsigned long t, a; 172 173 if (n1 > max_numerator || d1 > max_denominator) { 174 n1 = n0; 175 d1 = d0; 176 break; 177 } 178 if (d == 0) 179 break; 180 t = d; 181 a = n / d; 182 d = n % d; 183 n = t; 184 t = n0 + a * n1; 185 n0 = n1; 186 n1 = t; 187 t = d0 + a * d1; 188 d0 = d1; 189 d1 = t; 190 } 191 *best_numerator = n1; 192 *best_denominator = d1; 193 } 194 195 static int rk3528_armclk_set_clk(struct rk3528_clk_priv *priv, ulong new_rate) 196 { 197 const struct rockchip_cpu_rate_table *rate; 198 struct rk3528_cru *cru = priv->cru; 199 ulong old_rate; 200 201 rate = rockchip_get_cpu_settings(rk3528_cpu_rates, new_rate); 202 if (!rate) { 203 printf("%s unsupported rate\n", __func__); 204 return -EINVAL; 205 } 206 207 /* 208 * set up dependent divisors for DBG and ACLK clocks. 209 */ 210 old_rate = rockchip_pll_get_rate(&rk3528_pll_clks[APLL], priv->cru, APLL); 211 if (old_rate > new_rate) { 212 if (rockchip_pll_set_rate(&rk3528_pll_clks[APLL], 213 priv->cru, APLL, new_rate)) 214 return -EINVAL; 215 216 rk_clrsetreg(&cru->clksel_con[40], RK3528_DIV_PCLK_DBG_MASK, 217 rate->pclk_div << RK3528_DIV_PCLK_DBG_SHIFT); 218 219 rk_clrsetreg(&cru->clksel_con[5], RK3528_DIV_ACLK_M_CORE_MASK, 220 rate->aclk_div << RK3528_DIV_ACLK_M_CORE_SHIFT); 221 } else if (old_rate < new_rate) { 222 rk_clrsetreg(&cru->clksel_con[40], RK3528_DIV_PCLK_DBG_MASK, 223 rate->pclk_div << RK3528_DIV_PCLK_DBG_SHIFT); 224 225 rk_clrsetreg(&cru->clksel_con[5], RK3528_DIV_ACLK_M_CORE_MASK, 226 rate->aclk_div << RK3528_DIV_ACLK_M_CORE_SHIFT); 227 228 if (rockchip_pll_set_rate(&rk3528_pll_clks[APLL], 229 priv->cru, APLL, new_rate)) 230 return -EINVAL; 231 } 232 233 return 0; 234 } 235 236 static ulong rk3528_ppll_matrix_get_rate(struct rk3528_clk_priv *priv, 237 ulong clk_id) 238 { 239 struct rk3528_cru *cru = priv->cru; 240 u32 div, mask, shift; 241 void *reg; 242 243 switch (clk_id) { 244 case CLK_PPLL_50M_MATRIX: 245 case CLK_GMAC1_RMII_VPU: 246 mask = PCIE_CLK_MATRIX_50M_SRC_DIV_MASK; 247 shift = PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT; 248 reg = &cru->pcieclksel_con[1]; 249 break; 250 251 case CLK_PPLL_100M_MATRIX: 252 mask = PCIE_CLK_MATRIX_100M_SRC_DIV_MASK; 253 shift = PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT; 254 reg = &cru->pcieclksel_con[1]; 255 break; 256 257 case CLK_PPLL_125M_MATRIX: 258 case CLK_GMAC1_SRC_VPU: 259 mask = CLK_MATRIX_125M_SRC_DIV_MASK; 260 shift = CLK_MATRIX_125M_SRC_DIV_SHIFT; 261 reg = &cru->clksel_con[60]; 262 break; 263 264 case CLK_GMAC1_VPU_25M: 265 mask = CLK_MATRIX_25M_SRC_DIV_MASK; 266 shift = CLK_MATRIX_25M_SRC_DIV_SHIFT; 267 reg = &cru->clksel_con[60]; 268 break; 269 default: 270 return -ENOENT; 271 } 272 273 div = (readl(reg) & mask) >> shift; 274 275 return DIV_TO_RATE(priv->ppll_hz, div); 276 } 277 278 static ulong rk3528_ppll_matrix_set_rate(struct rk3528_clk_priv *priv, 279 ulong clk_id, ulong rate) 280 { 281 struct rk3528_cru *cru = priv->cru; 282 u32 id, div, mask, shift; 283 u8 is_pciecru = 0; 284 285 switch (clk_id) { 286 case CLK_PPLL_50M_MATRIX: 287 id = 1; 288 mask = PCIE_CLK_MATRIX_50M_SRC_DIV_MASK; 289 shift = PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT; 290 is_pciecru = 1; 291 break; 292 293 case CLK_PPLL_100M_MATRIX: 294 id = 1; 295 mask = PCIE_CLK_MATRIX_100M_SRC_DIV_MASK; 296 shift = PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT; 297 is_pciecru = 1; 298 break; 299 300 case CLK_PPLL_125M_MATRIX: 301 id = 60; 302 mask = CLK_MATRIX_125M_SRC_DIV_MASK; 303 shift = CLK_MATRIX_125M_SRC_DIV_SHIFT; 304 break; 305 case CLK_GMAC1_VPU_25M: 306 id = 60; 307 mask = CLK_MATRIX_25M_SRC_DIV_MASK; 308 shift = CLK_MATRIX_25M_SRC_DIV_SHIFT; 309 break; 310 default: 311 return -ENOENT; 312 } 313 314 div = DIV_ROUND_UP(priv->ppll_hz, rate); 315 if (is_pciecru) 316 rk_clrsetreg(&cru->pcieclksel_con[id], mask, (div - 1) << shift); 317 else 318 rk_clrsetreg(&cru->clksel_con[id], mask, (div - 1) << shift); 319 320 return rk3528_ppll_matrix_get_rate(priv, clk_id); 321 } 322 323 static ulong rk3528_cgpll_matrix_get_rate(struct rk3528_clk_priv *priv, 324 ulong clk_id) 325 { 326 struct rk3528_cru *cru = priv->cru; 327 u32 sel, div, mask, shift, con; 328 u32 sel_mask = 0, sel_shift; 329 u8 is_gpll_parent = 1; 330 u8 is_halfdiv = 0; 331 ulong prate; 332 333 switch (clk_id) { 334 case CLK_MATRIX_50M_SRC: 335 con = 0; 336 mask = CLK_MATRIX_50M_SRC_DIV_MASK; 337 shift = CLK_MATRIX_50M_SRC_DIV_SHIFT; 338 is_gpll_parent = 0; 339 break; 340 341 case CLK_MATRIX_100M_SRC: 342 con = 0; 343 mask = CLK_MATRIX_100M_SRC_DIV_MASK; 344 shift = CLK_MATRIX_100M_SRC_DIV_SHIFT; 345 is_gpll_parent = 0; 346 break; 347 348 case CLK_MATRIX_150M_SRC: 349 con = 1; 350 mask = CLK_MATRIX_150M_SRC_DIV_MASK; 351 shift = CLK_MATRIX_150M_SRC_DIV_SHIFT; 352 break; 353 354 case CLK_MATRIX_200M_SRC: 355 con = 1; 356 mask = CLK_MATRIX_200M_SRC_DIV_MASK; 357 shift = CLK_MATRIX_200M_SRC_DIV_SHIFT; 358 break; 359 360 case CLK_MATRIX_250M_SRC: 361 con = 1; 362 mask = CLK_MATRIX_250M_SRC_DIV_MASK; 363 shift = CLK_MATRIX_250M_SRC_DIV_SHIFT; 364 sel_mask = CLK_MATRIX_250M_SRC_SEL_MASK; 365 sel_shift = CLK_MATRIX_250M_SRC_SEL_SHIFT; 366 break; 367 368 case CLK_MATRIX_300M_SRC: 369 con = 2; 370 mask = CLK_MATRIX_300M_SRC_DIV_MASK; 371 shift = CLK_MATRIX_300M_SRC_DIV_SHIFT; 372 break; 373 374 case CLK_MATRIX_339M_SRC: 375 con = 2; 376 mask = CLK_MATRIX_339M_SRC_DIV_MASK; 377 shift = CLK_MATRIX_339M_SRC_DIV_SHIFT; 378 is_halfdiv = 1; 379 break; 380 381 case CLK_MATRIX_400M_SRC: 382 con = 2; 383 mask = CLK_MATRIX_400M_SRC_DIV_MASK; 384 shift = CLK_MATRIX_400M_SRC_DIV_SHIFT; 385 break; 386 387 case CLK_MATRIX_500M_SRC: 388 con = 3; 389 mask = CLK_MATRIX_500M_SRC_DIV_MASK; 390 shift = CLK_MATRIX_500M_SRC_DIV_SHIFT; 391 sel_mask = CLK_MATRIX_500M_SRC_SEL_MASK; 392 sel_shift = CLK_MATRIX_500M_SRC_SEL_SHIFT; 393 break; 394 395 case CLK_MATRIX_600M_SRC: 396 con = 4; 397 mask = CLK_MATRIX_600M_SRC_DIV_MASK; 398 shift = CLK_MATRIX_600M_SRC_DIV_SHIFT; 399 break; 400 401 case ACLK_BUS_VOPGL_ROOT: 402 case ACLK_BUS_VOPGL_BIU: 403 con = 43; 404 mask = ACLK_BUS_VOPGL_ROOT_DIV_MASK; 405 shift = ACLK_BUS_VOPGL_ROOT_DIV_SHIFT; 406 break; 407 408 default: 409 return -ENOENT; 410 } 411 412 if (sel_mask) { 413 sel = (readl(&cru->clksel_con[con]) & sel_mask) >> sel_shift; 414 if (sel == CLK_MATRIX_250M_SRC_SEL_CLK_GPLL_MUX) // TODO 415 prate = priv->gpll_hz; 416 else 417 prate = priv->cpll_hz; 418 } else { 419 if (is_gpll_parent) 420 prate = priv->gpll_hz; 421 else 422 prate = priv->cpll_hz; 423 } 424 425 div = (readl(&cru->clksel_con[con]) & mask) >> shift; 426 427 return is_halfdiv ? DIV_TO_RATE(prate * 2, (3 + 2 * div) + 1) : DIV_TO_RATE(prate, div); 428 } 429 430 static ulong rk3528_cgpll_matrix_set_rate(struct rk3528_clk_priv *priv, 431 ulong clk_id, ulong rate) 432 { 433 struct rk3528_cru *cru = priv->cru; 434 u32 sel, div, mask, shift, con; 435 u32 sel_mask = 0, sel_shift; 436 u8 is_gpll_parent = 1; 437 u8 is_halfdiv = 0; 438 ulong prate = 0; 439 440 switch (clk_id) { 441 case CLK_MATRIX_50M_SRC: 442 con = 0; 443 mask = CLK_MATRIX_50M_SRC_DIV_MASK; 444 shift = CLK_MATRIX_50M_SRC_DIV_SHIFT; 445 is_gpll_parent = 0; 446 break; 447 448 case CLK_MATRIX_100M_SRC: 449 con = 0; 450 mask = CLK_MATRIX_100M_SRC_DIV_MASK; 451 shift = CLK_MATRIX_100M_SRC_DIV_SHIFT; 452 is_gpll_parent = 0; 453 break; 454 455 case CLK_MATRIX_150M_SRC: 456 con = 1; 457 mask = CLK_MATRIX_150M_SRC_DIV_MASK; 458 shift = CLK_MATRIX_150M_SRC_DIV_SHIFT; 459 break; 460 461 case CLK_MATRIX_200M_SRC: 462 con = 1; 463 mask = CLK_MATRIX_200M_SRC_DIV_MASK; 464 shift = CLK_MATRIX_200M_SRC_DIV_SHIFT; 465 break; 466 467 case CLK_MATRIX_250M_SRC: 468 con = 1; 469 mask = CLK_MATRIX_250M_SRC_DIV_MASK; 470 shift = CLK_MATRIX_250M_SRC_DIV_SHIFT; 471 sel_mask = CLK_MATRIX_250M_SRC_SEL_MASK; 472 sel_shift = CLK_MATRIX_250M_SRC_SEL_SHIFT; 473 break; 474 475 case CLK_MATRIX_300M_SRC: 476 con = 2; 477 mask = CLK_MATRIX_300M_SRC_DIV_MASK; 478 shift = CLK_MATRIX_300M_SRC_DIV_SHIFT; 479 break; 480 481 case CLK_MATRIX_339M_SRC: 482 con = 2; 483 mask = CLK_MATRIX_339M_SRC_DIV_MASK; 484 shift = CLK_MATRIX_339M_SRC_DIV_SHIFT; 485 is_halfdiv = 1; 486 break; 487 488 case CLK_MATRIX_400M_SRC: 489 con = 2; 490 mask = CLK_MATRIX_400M_SRC_DIV_MASK; 491 shift = CLK_MATRIX_400M_SRC_DIV_SHIFT; 492 break; 493 494 case CLK_MATRIX_500M_SRC: 495 con = 3; 496 mask = CLK_MATRIX_500M_SRC_DIV_MASK; 497 shift = CLK_MATRIX_500M_SRC_DIV_SHIFT; 498 sel_mask = CLK_MATRIX_500M_SRC_SEL_MASK; 499 sel_shift = CLK_MATRIX_500M_SRC_SEL_SHIFT; 500 break; 501 502 case CLK_MATRIX_600M_SRC: 503 con = 4; 504 mask = CLK_MATRIX_600M_SRC_DIV_MASK; 505 shift = CLK_MATRIX_600M_SRC_DIV_SHIFT; 506 break; 507 508 case ACLK_BUS_VOPGL_ROOT: 509 case ACLK_BUS_VOPGL_BIU: 510 con = 43; 511 mask = ACLK_BUS_VOPGL_ROOT_DIV_MASK; 512 shift = ACLK_BUS_VOPGL_ROOT_DIV_SHIFT; 513 break; 514 515 default: 516 return -ENOENT; 517 } 518 519 if (sel_mask) { 520 if (priv->gpll_hz % rate == 0) { 521 sel = CLK_MATRIX_250M_SRC_SEL_CLK_GPLL_MUX; // TODO 522 prate = priv->gpll_hz; 523 } else { 524 sel = CLK_MATRIX_250M_SRC_SEL_CLK_CPLL_MUX; 525 prate = priv->cpll_hz; 526 } 527 } else { 528 if (is_gpll_parent) 529 prate = priv->gpll_hz; 530 else 531 prate = priv->cpll_hz; 532 } 533 534 if (is_halfdiv) 535 div = DIV_ROUND_UP((prate * 2) - (3 * rate), 2 * rate); 536 else 537 div = DIV_ROUND_UP(prate, rate); 538 539 rk_clrsetreg(&cru->clksel_con[con], mask, (div - 1) << shift); 540 if (sel_mask) 541 rk_clrsetreg(&cru->clksel_con[con], sel_mask, sel << sel_shift); 542 543 return rk3528_cgpll_matrix_get_rate(priv, clk_id); 544 } 545 546 static ulong rk3528_i2c_get_clk(struct rk3528_clk_priv *priv, ulong clk_id) 547 { 548 struct rk3528_cru *cru = priv->cru; 549 u32 id, sel, con, mask, shift; 550 u8 is_pmucru = 0; 551 ulong rate; 552 553 switch (clk_id) { 554 case CLK_I2C0: 555 id = 79; 556 mask = CLK_I2C0_SEL_MASK; 557 shift = CLK_I2C0_SEL_SHIFT; 558 break; 559 560 case CLK_I2C1: 561 id = 79; 562 mask = CLK_I2C1_SEL_MASK; 563 shift = CLK_I2C1_SEL_SHIFT; 564 break; 565 566 case CLK_I2C2: 567 id = 0; 568 mask = CLK_I2C2_SEL_MASK; 569 shift = CLK_I2C2_SEL_SHIFT; 570 is_pmucru = 1; 571 break; 572 573 case CLK_I2C3: 574 id = 63; 575 mask = CLK_I2C3_SEL_MASK; 576 shift = CLK_I2C3_SEL_SHIFT; 577 break; 578 579 case CLK_I2C4: 580 id = 85; 581 mask = CLK_I2C4_SEL_MASK; 582 shift = CLK_I2C4_SEL_SHIFT; 583 break; 584 585 case CLK_I2C5: 586 id = 63; 587 mask = CLK_I2C5_SEL_MASK; 588 shift = CLK_I2C5_SEL_SHIFT; 589 break; 590 591 case CLK_I2C6: 592 id = 64; 593 mask = CLK_I2C6_SEL_MASK; 594 shift = CLK_I2C6_SEL_SHIFT; 595 break; 596 597 case CLK_I2C7: 598 id = 86; 599 mask = CLK_I2C7_SEL_MASK; 600 shift = CLK_I2C7_SEL_SHIFT; 601 break; 602 603 default: 604 return -ENOENT; 605 } 606 607 if (is_pmucru) 608 con = readl(&cru->pmuclksel_con[id]); 609 else 610 con = readl(&cru->clksel_con[id]); 611 sel = (con & mask) >> shift; 612 if (sel == CLK_I2C3_SEL_CLK_MATRIX_200M_SRC) 613 rate = 200 * MHz; 614 else if (sel == CLK_I2C3_SEL_CLK_MATRIX_100M_SRC) 615 rate = 100 * MHz; 616 else if (sel == CLK_I2C3_SEL_CLK_MATRIX_50M_SRC) 617 rate = 50 * MHz; 618 else 619 rate = OSC_HZ; 620 621 return rate; 622 } 623 624 static ulong rk3528_i2c_set_clk(struct rk3528_clk_priv *priv, ulong clk_id, 625 ulong rate) 626 { 627 struct rk3528_cru *cru = priv->cru; 628 u32 id, sel, mask, shift; 629 u8 is_pmucru = 0; 630 631 if (rate == 200 * MHz) 632 sel = CLK_I2C3_SEL_CLK_MATRIX_200M_SRC; 633 else if (rate == 100 * MHz) 634 sel = CLK_I2C3_SEL_CLK_MATRIX_100M_SRC; 635 else if (rate == 50 * MHz) 636 sel = CLK_I2C3_SEL_CLK_MATRIX_50M_SRC; 637 else 638 sel = CLK_I2C3_SEL_XIN_OSC0_FUNC; 639 640 switch (clk_id) { 641 case CLK_I2C0: 642 id = 79; 643 mask = CLK_I2C0_SEL_MASK; 644 shift = CLK_I2C0_SEL_SHIFT; 645 break; 646 647 case CLK_I2C1: 648 id = 79; 649 mask = CLK_I2C1_SEL_MASK; 650 shift = CLK_I2C1_SEL_SHIFT; 651 break; 652 653 case CLK_I2C2: 654 id = 0; 655 mask = CLK_I2C2_SEL_MASK; 656 shift = CLK_I2C2_SEL_SHIFT; 657 is_pmucru = 1; 658 break; 659 660 case CLK_I2C3: 661 id = 63; 662 mask = CLK_I2C3_SEL_MASK; 663 shift = CLK_I2C3_SEL_SHIFT; 664 break; 665 666 case CLK_I2C4: 667 id = 85; 668 mask = CLK_I2C4_SEL_MASK; 669 shift = CLK_I2C4_SEL_SHIFT; 670 break; 671 672 case CLK_I2C5: 673 id = 63; 674 mask = CLK_I2C5_SEL_MASK; 675 shift = CLK_I2C5_SEL_SHIFT; 676 677 case CLK_I2C6: 678 id = 64; 679 mask = CLK_I2C6_SEL_MASK; 680 shift = CLK_I2C6_SEL_SHIFT; 681 break; 682 683 case CLK_I2C7: 684 id = 86; 685 mask = CLK_I2C7_SEL_MASK; 686 shift = CLK_I2C7_SEL_SHIFT; 687 break; 688 689 default: 690 return -ENOENT; 691 } 692 693 if (is_pmucru) 694 rk_clrsetreg(&cru->pmuclksel_con[id], mask, sel << shift); 695 else 696 rk_clrsetreg(&cru->clksel_con[id], mask, sel << shift); 697 698 return rk3528_i2c_get_clk(priv, clk_id); 699 } 700 701 static ulong rk3528_spi_get_clk(struct rk3528_clk_priv *priv, ulong clk_id) 702 { 703 struct rk3528_cru *cru = priv->cru; 704 u32 id, sel, con, mask, shift; 705 ulong rate; 706 707 switch (clk_id) { 708 case CLK_SPI0: 709 id = 79; 710 mask = CLK_SPI0_SEL_MASK; 711 shift = CLK_SPI0_SEL_SHIFT; 712 break; 713 714 case CLK_SPI1: 715 id = 63; 716 mask = CLK_SPI1_SEL_MASK; 717 shift = CLK_SPI1_SEL_SHIFT; 718 break; 719 default: 720 return -ENOENT; 721 } 722 723 con = readl(&cru->clksel_con[id]); 724 sel = (con & mask) >> shift; 725 if (sel == CLK_SPI1_SEL_CLK_MATRIX_200M_SRC) 726 rate = 200 * MHz; 727 else if (sel == CLK_SPI1_SEL_CLK_MATRIX_100M_SRC) 728 rate = 100 * MHz; 729 else if (sel == CLK_SPI1_SEL_CLK_MATRIX_50M_SRC) 730 rate = 50 * MHz; 731 else 732 rate = OSC_HZ; 733 734 return rate; 735 } 736 737 static ulong rk3528_spi_set_clk(struct rk3528_clk_priv *priv, 738 ulong clk_id, ulong rate) 739 { 740 struct rk3528_cru *cru = priv->cru; 741 u32 id, sel, mask, shift; 742 743 if (rate == 200 * MHz) 744 sel = CLK_SPI1_SEL_CLK_MATRIX_200M_SRC; 745 else if (rate == 100 * MHz) 746 sel = CLK_SPI1_SEL_CLK_MATRIX_100M_SRC; 747 else if (rate == 50 * MHz) 748 sel = CLK_SPI1_SEL_CLK_MATRIX_50M_SRC; 749 else 750 sel = CLK_SPI1_SEL_XIN_OSC0_FUNC; 751 752 switch (clk_id) { 753 case CLK_SPI0: 754 id = 79; 755 mask = CLK_SPI0_SEL_MASK; 756 shift = CLK_SPI0_SEL_SHIFT; 757 break; 758 759 case CLK_SPI1: 760 id = 63; 761 mask = CLK_SPI1_SEL_MASK; 762 shift = CLK_SPI1_SEL_SHIFT; 763 break; 764 default: 765 return -ENOENT; 766 } 767 768 rk_clrsetreg(&cru->clksel_con[id], mask, sel << shift); 769 770 return rk3528_spi_get_clk(priv, clk_id); 771 } 772 773 static ulong rk3528_pwm_get_clk(struct rk3528_clk_priv *priv, ulong clk_id) 774 { 775 struct rk3528_cru *cru = priv->cru; 776 u32 id, sel, con, mask, shift; 777 ulong rate; 778 779 switch (clk_id) { 780 case CLK_PWM0: 781 id = 44; 782 mask = CLK_PWM0_SEL_MASK; 783 shift = CLK_PWM0_SEL_SHIFT; 784 break; 785 786 case CLK_PWM1: 787 id = 44; 788 mask = CLK_PWM1_SEL_MASK; 789 shift = CLK_PWM1_SEL_SHIFT; 790 break; 791 792 default: 793 return -ENOENT; 794 } 795 796 con = readl(&cru->clksel_con[id]); 797 sel = (con & mask) >> shift; 798 if (sel == CLK_PWM0_SEL_CLK_MATRIX_100M_SRC) 799 rate = 100 * MHz; 800 if (sel == CLK_PWM0_SEL_CLK_MATRIX_50M_SRC) 801 rate = 50 * MHz; 802 else 803 rate = OSC_HZ; 804 805 return rate; 806 } 807 808 static ulong rk3528_pwm_set_clk(struct rk3528_clk_priv *priv, 809 ulong clk_id, ulong rate) 810 { 811 struct rk3528_cru *cru = priv->cru; 812 u32 id, sel, mask, shift; 813 814 if (rate == 100 * MHz) 815 sel = CLK_PWM0_SEL_CLK_MATRIX_100M_SRC; 816 else if (rate == 50 * MHz) 817 sel = CLK_PWM0_SEL_CLK_MATRIX_50M_SRC; 818 else 819 sel = CLK_PWM0_SEL_XIN_OSC0_FUNC; 820 821 switch (clk_id) { 822 case CLK_PWM0: 823 id = 44; 824 mask = CLK_PWM0_SEL_MASK; 825 shift = CLK_PWM0_SEL_SHIFT; 826 break; 827 828 case CLK_PWM1: 829 id = 44; 830 mask = CLK_PWM1_SEL_MASK; 831 shift = CLK_PWM1_SEL_SHIFT; 832 break; 833 834 default: 835 return -ENOENT; 836 } 837 838 rk_clrsetreg(&cru->clksel_con[id], mask, sel << shift); 839 840 return rk3528_pwm_get_clk(priv, clk_id); 841 } 842 843 static ulong rk3528_adc_get_clk(struct rk3528_clk_priv *priv, ulong clk_id) 844 { 845 struct rk3528_cru *cru = priv->cru; 846 u32 div, con; 847 848 con = readl(&cru->clksel_con[74]); 849 switch (clk_id) { 850 case CLK_SARADC: 851 div = (con & CLK_SARADC_DIV_MASK) >> 852 CLK_SARADC_DIV_SHIFT; 853 break; 854 855 case CLK_TSADC_TSEN: 856 div = (con & CLK_TSADC_TSEN_DIV_MASK) >> 857 CLK_TSADC_TSEN_DIV_SHIFT; 858 break; 859 860 case CLK_TSADC: 861 div = (con & CLK_TSADC_DIV_MASK) >> 862 CLK_TSADC_DIV_SHIFT; 863 break; 864 865 default: 866 return -ENOENT; 867 } 868 869 return DIV_TO_RATE(OSC_HZ, div); 870 } 871 872 static ulong rk3528_adc_set_clk(struct rk3528_clk_priv *priv, 873 ulong clk_id, ulong rate) 874 { 875 struct rk3528_cru *cru = priv->cru; 876 u32 div, mask, shift; 877 878 switch (clk_id) { 879 case CLK_SARADC: 880 mask = CLK_SARADC_DIV_MASK; 881 shift = CLK_SARADC_DIV_SHIFT; 882 break; 883 884 case CLK_TSADC_TSEN: 885 mask = CLK_TSADC_TSEN_DIV_MASK; 886 shift = CLK_TSADC_TSEN_DIV_SHIFT; 887 break; 888 889 case CLK_TSADC: 890 mask = CLK_TSADC_DIV_MASK; 891 shift = CLK_TSADC_DIV_SHIFT; 892 break; 893 894 default: 895 return -ENOENT; 896 } 897 898 div = DIV_ROUND_UP(OSC_HZ, rate); 899 rk_clrsetreg(&cru->clksel_con[74], mask, (div - 1) << shift); 900 901 return rk3528_adc_get_clk(priv, clk_id); 902 } 903 904 static ulong rk3528_sdmmc_get_clk(struct rk3528_clk_priv *priv, ulong clk_id) 905 { 906 struct rk3528_cru *cru = priv->cru; 907 u32 div, sel, con; 908 ulong prate; 909 910 con = readl(&cru->clksel_con[85]); 911 div = (con & CCLK_SRC_SDMMC0_DIV_MASK) >> 912 CCLK_SRC_SDMMC0_DIV_SHIFT; 913 sel = (con & CCLK_SRC_SDMMC0_SEL_MASK) >> 914 CCLK_SRC_SDMMC0_SEL_SHIFT; 915 916 if (sel == CCLK_SRC_SDMMC0_SEL_CLK_GPLL_MUX) 917 prate = priv->gpll_hz; 918 else if (sel == CCLK_SRC_SDMMC0_SEL_CLK_CPLL_MUX) 919 prate = priv->cpll_hz; 920 else 921 prate = OSC_HZ; 922 923 return DIV_TO_RATE(prate, div); 924 } 925 926 static ulong rk3528_sdmmc_set_clk(struct rk3528_clk_priv *priv, 927 ulong clk_id, ulong rate) 928 { 929 struct rk3528_cru *cru = priv->cru; 930 u32 div, sel; 931 932 if (OSC_HZ % rate == 0) { 933 div = DIV_ROUND_UP(OSC_HZ, rate); 934 sel = CCLK_SRC_SDMMC0_SEL_XIN_OSC0_FUNC; 935 } else if ((priv->cpll_hz % rate) == 0) { 936 div = DIV_ROUND_UP(priv->cpll_hz, rate); 937 sel = CCLK_SRC_SDMMC0_SEL_CLK_CPLL_MUX; 938 } else { 939 div = DIV_ROUND_UP(priv->gpll_hz, rate); 940 sel = CCLK_SRC_SDMMC0_SEL_CLK_GPLL_MUX; 941 } 942 943 assert(div - 1 <= 31); 944 rk_clrsetreg(&cru->clksel_con[85], 945 CCLK_SRC_SDMMC0_SEL_MASK | 946 CCLK_SRC_SDMMC0_DIV_MASK, 947 sel << CCLK_SRC_SDMMC0_SEL_SHIFT | 948 (div - 1) << CCLK_SRC_SDMMC0_DIV_SHIFT); 949 950 return rk3528_sdmmc_get_clk(priv, clk_id); 951 } 952 953 static ulong rk3528_sfc_get_clk(struct rk3528_clk_priv *priv) 954 { 955 struct rk3528_cru *cru = priv->cru; 956 u32 div, sel, con, parent; 957 958 con = readl(&cru->clksel_con[61]); 959 div = (con & SCLK_SFC_DIV_MASK) >> 960 SCLK_SFC_DIV_SHIFT; 961 sel = (con & SCLK_SFC_SEL_MASK) >> 962 SCLK_SFC_SEL_SHIFT; 963 if (sel == SCLK_SFC_SEL_CLK_GPLL_MUX) 964 parent = priv->gpll_hz; 965 else if (sel == SCLK_SFC_SEL_CLK_CPLL_MUX) 966 parent = priv->cpll_hz; 967 else 968 parent = OSC_HZ; 969 970 return DIV_TO_RATE(parent, div); 971 } 972 973 static ulong rk3528_sfc_set_clk(struct rk3528_clk_priv *priv, ulong rate) 974 { 975 struct rk3528_cru *cru = priv->cru; 976 int div, sel; 977 978 if (OSC_HZ % rate == 0) { 979 div = DIV_ROUND_UP(OSC_HZ, rate); 980 sel = SCLK_SFC_SEL_XIN_OSC0_FUNC; 981 } else if ((priv->cpll_hz % rate) == 0) { 982 div = DIV_ROUND_UP(priv->cpll_hz, rate); 983 sel = SCLK_SFC_SEL_CLK_CPLL_MUX; 984 } else { 985 div = DIV_ROUND_UP(priv->gpll_hz, rate); 986 sel = SCLK_SFC_SEL_CLK_GPLL_MUX; 987 } 988 989 assert(div - 1 <= 63); 990 rk_clrsetreg(&cru->clksel_con[61], 991 SCLK_SFC_SEL_MASK | 992 SCLK_SFC_DIV_MASK, 993 sel << SCLK_SFC_SEL_SHIFT | 994 (div - 1) << SCLK_SFC_DIV_SHIFT); 995 996 return rk3528_sfc_get_clk(priv); 997 } 998 999 static ulong rk3528_emmc_get_clk(struct rk3528_clk_priv *priv) 1000 { 1001 struct rk3528_cru *cru = priv->cru; 1002 u32 div, sel, con, parent; 1003 1004 con = readl(&cru->clksel_con[62]); 1005 div = (con & CCLK_SRC_EMMC_DIV_MASK) >> 1006 CCLK_SRC_EMMC_DIV_SHIFT; 1007 sel = (con & CCLK_SRC_EMMC_SEL_MASK) >> 1008 CCLK_SRC_EMMC_SEL_SHIFT; 1009 1010 if (sel == CCLK_SRC_EMMC_SEL_CLK_GPLL_MUX) 1011 parent = priv->gpll_hz; 1012 else if (sel == CCLK_SRC_EMMC_SEL_CLK_CPLL_MUX) 1013 parent = priv->cpll_hz; 1014 else 1015 parent = OSC_HZ; 1016 1017 return DIV_TO_RATE(parent, div); 1018 } 1019 1020 static ulong rk3528_emmc_set_clk(struct rk3528_clk_priv *priv, ulong rate) 1021 { 1022 struct rk3528_cru *cru = priv->cru; 1023 u32 div, sel; 1024 1025 if (OSC_HZ % rate == 0) { 1026 div = DIV_ROUND_UP(OSC_HZ, rate); 1027 sel = CCLK_SRC_EMMC_SEL_XIN_OSC0_FUNC; 1028 } else if ((priv->cpll_hz % rate) == 0) { 1029 div = DIV_ROUND_UP(priv->cpll_hz, rate); 1030 sel = CCLK_SRC_EMMC_SEL_CLK_CPLL_MUX; 1031 } else { 1032 div = DIV_ROUND_UP(priv->gpll_hz, rate); 1033 sel = CCLK_SRC_EMMC_SEL_CLK_GPLL_MUX; 1034 } 1035 1036 assert(div - 1 <= 31); 1037 rk_clrsetreg(&cru->clksel_con[62], 1038 CCLK_SRC_EMMC_SEL_MASK | 1039 CCLK_SRC_EMMC_DIV_MASK, 1040 sel << CCLK_SRC_EMMC_SEL_SHIFT | 1041 (div - 1) << CCLK_SRC_EMMC_DIV_SHIFT); 1042 1043 return rk3528_emmc_get_clk(priv); 1044 } 1045 1046 static ulong rk3528_dclk_vop_get_clk(struct rk3528_clk_priv *priv, ulong clk_id) 1047 { 1048 struct rk3528_cru *cru = priv->cru; 1049 u32 div_mask, div_shift; 1050 u32 sel_mask, sel_shift; 1051 u32 id, con, sel, div; 1052 ulong prate; 1053 1054 switch (clk_id) { 1055 case DCLK_VOP0: 1056 id = 32; 1057 sel_mask = DCLK_VOP_SRC0_SEL_MASK; 1058 sel_shift = DCLK_VOP_SRC0_SEL_SHIFT; 1059 /* FIXME if need src: clk_hdmiphy_pixel_io */ 1060 div_mask = DCLK_VOP_SRC0_DIV_MASK; 1061 div_shift = DCLK_VOP_SRC0_DIV_SHIFT; 1062 break; 1063 1064 case DCLK_VOP1: 1065 id = 33; 1066 sel_mask = DCLK_VOP_SRC1_SEL_MASK; 1067 sel_shift = DCLK_VOP_SRC1_SEL_SHIFT; 1068 div_mask = DCLK_VOP_SRC1_DIV_MASK; 1069 div_shift = DCLK_VOP_SRC1_DIV_SHIFT; 1070 break; 1071 1072 default: 1073 return -ENOENT; 1074 } 1075 1076 con = readl(&cru->clksel_con[id]); 1077 div = (con & div_mask) >> div_shift; 1078 sel = (con & sel_mask) >> sel_shift; 1079 if (sel == DCLK_VOP_SRC_SEL_CLK_GPLL_MUX) 1080 prate = priv->gpll_hz; 1081 else 1082 prate = priv->cpll_hz; 1083 1084 return DIV_TO_RATE(prate, div); 1085 } 1086 1087 static ulong rk3528_dclk_vop_set_clk(struct rk3528_clk_priv *priv, 1088 ulong clk_id, ulong rate) 1089 { 1090 struct rk3528_cru *cru = priv->cru; 1091 u32 div_mask, div_shift; 1092 u32 sel_mask, sel_shift; 1093 u32 id, sel, div; 1094 ulong prate; 1095 1096 switch (clk_id) { 1097 case DCLK_VOP0: 1098 id = 32; 1099 sel_mask = DCLK_VOP_SRC0_SEL_MASK; 1100 sel_shift = DCLK_VOP_SRC0_SEL_SHIFT; 1101 /* FIXME if need src: clk_hdmiphy_pixel_io */ 1102 div_mask = DCLK_VOP_SRC0_DIV_MASK; 1103 div_shift = DCLK_VOP_SRC0_DIV_SHIFT; 1104 break; 1105 1106 case DCLK_VOP1: 1107 id = 33; 1108 sel_mask = DCLK_VOP_SRC1_SEL_MASK; 1109 sel_shift = DCLK_VOP_SRC1_SEL_SHIFT; 1110 div_mask = DCLK_VOP_SRC1_DIV_MASK; 1111 div_shift = DCLK_VOP_SRC1_DIV_SHIFT; 1112 break; 1113 1114 default: 1115 return -ENOENT; 1116 } 1117 1118 if ((priv->gpll_hz % rate) == 0) { 1119 prate = priv->gpll_hz; 1120 sel = (DCLK_VOP_SRC_SEL_CLK_GPLL_MUX << sel_shift) & sel_mask; 1121 } else { 1122 prate = priv->cpll_hz; 1123 sel = (DCLK_VOP_SRC_SEL_CLK_CPLL_MUX << sel_shift) & sel_mask; 1124 } 1125 1126 div = ((DIV_ROUND_UP(prate, rate) - 1) << div_shift) & div_mask; 1127 rk_clrsetreg(&cru->clksel_con[id], sel, div); 1128 1129 return rk3528_dclk_vop_get_clk(priv, clk_id); 1130 } 1131 1132 static ulong rk3528_uart_get_rate(struct rk3528_clk_priv *priv, ulong clk_id) 1133 { 1134 struct rk3528_cru *cru = priv->cru; 1135 u32 sel_shift, sel_mask, div_shift, div_mask; 1136 u32 sel, id, con, frac_div, div; 1137 ulong m, n, rate; 1138 1139 switch (clk_id) { 1140 case SCLK_UART0: 1141 id = 6; 1142 sel_shift = SCLK_UART0_SRC_SEL_SHIFT; 1143 sel_mask = SCLK_UART0_SRC_SEL_MASK; 1144 div_shift = CLK_UART0_SRC_DIV_SHIFT; 1145 div_mask = CLK_UART0_SRC_DIV_MASK; 1146 break; 1147 1148 case SCLK_UART1: 1149 id = 8; 1150 sel_shift = SCLK_UART1_SRC_SEL_SHIFT; 1151 sel_mask = SCLK_UART1_SRC_SEL_MASK; 1152 div_shift = CLK_UART1_SRC_DIV_SHIFT; 1153 div_mask = CLK_UART1_SRC_DIV_MASK; 1154 break; 1155 1156 case SCLK_UART2: 1157 id = 10; 1158 sel_shift = SCLK_UART2_SRC_SEL_SHIFT; 1159 sel_mask = SCLK_UART2_SRC_SEL_MASK; 1160 div_shift = CLK_UART2_SRC_DIV_SHIFT; 1161 div_mask = CLK_UART2_SRC_DIV_MASK; 1162 break; 1163 1164 case SCLK_UART3: 1165 id = 12; 1166 sel_shift = SCLK_UART3_SRC_SEL_SHIFT; 1167 sel_mask = SCLK_UART3_SRC_SEL_MASK; 1168 div_shift = CLK_UART3_SRC_DIV_SHIFT; 1169 div_mask = CLK_UART3_SRC_DIV_MASK; 1170 break; 1171 1172 case SCLK_UART4: 1173 id = 14; 1174 sel_shift = SCLK_UART4_SRC_SEL_SHIFT; 1175 sel_mask = SCLK_UART4_SRC_SEL_MASK; 1176 div_shift = CLK_UART4_SRC_DIV_SHIFT; 1177 div_mask = CLK_UART4_SRC_DIV_MASK; 1178 break; 1179 1180 case SCLK_UART5: 1181 id = 16; 1182 sel_shift = SCLK_UART5_SRC_SEL_SHIFT; 1183 sel_mask = SCLK_UART5_SRC_SEL_MASK; 1184 div_shift = CLK_UART5_SRC_DIV_SHIFT; 1185 div_mask = CLK_UART5_SRC_DIV_MASK; 1186 break; 1187 1188 case SCLK_UART6: 1189 id = 18; 1190 sel_shift = SCLK_UART6_SRC_SEL_SHIFT; 1191 sel_mask = SCLK_UART6_SRC_SEL_MASK; 1192 div_shift = CLK_UART6_SRC_DIV_SHIFT; 1193 div_mask = CLK_UART6_SRC_DIV_MASK; 1194 break; 1195 1196 case SCLK_UART7: 1197 id = 20; 1198 sel_shift = SCLK_UART7_SRC_SEL_SHIFT; 1199 sel_mask = SCLK_UART7_SRC_SEL_MASK; 1200 div_shift = CLK_UART7_SRC_DIV_SHIFT; 1201 div_mask = CLK_UART7_SRC_DIV_MASK; 1202 break; 1203 1204 default: 1205 return -ENOENT; 1206 } 1207 1208 con = readl(&cru->clksel_con[id - 2]); 1209 div = (con & div_mask) >> div_shift; 1210 1211 con = readl(&cru->clksel_con[id]); 1212 sel = (con & sel_mask) >> sel_shift; 1213 1214 if (sel == SCLK_UART0_SRC_SEL_CLK_UART0_SRC) { 1215 rate = DIV_TO_RATE(priv->gpll_hz, div); 1216 } else if (sel == SCLK_UART0_SRC_SEL_CLK_UART0_FRAC) { 1217 frac_div = readl(&cru->clksel_con[id - 1]); 1218 n = (frac_div & 0xffff0000) >> 16; 1219 m = frac_div & 0x0000ffff; 1220 rate = DIV_TO_RATE(priv->gpll_hz, div) * n / m; 1221 } else { 1222 rate = OSC_HZ; 1223 } 1224 1225 return rate; 1226 } 1227 1228 static ulong rk3528_uart_set_rate(struct rk3528_clk_priv *priv, 1229 ulong clk_id, ulong rate) 1230 { 1231 struct rk3528_cru *cru = priv->cru; 1232 u32 sel_shift, sel_mask, div_shift, div_mask; 1233 u32 sel, id, div; 1234 ulong m = 0, n = 0, val; 1235 1236 if (rate == OSC_HZ) { 1237 sel = SCLK_UART0_SRC_SEL_XIN_OSC0_FUNC; 1238 div = DIV_ROUND_UP(OSC_HZ, rate); 1239 } else if (priv->gpll_hz % rate == 0) { 1240 sel = SCLK_UART0_SRC_SEL_CLK_UART0_SRC; 1241 div = DIV_ROUND_UP(priv->gpll_hz, rate); 1242 } else { 1243 sel = SCLK_UART0_SRC_SEL_CLK_UART0_FRAC; 1244 div = 2; 1245 rational_best_approximation(rate, priv->gpll_hz / div, 1246 GENMASK(16 - 1, 0), 1247 GENMASK(16 - 1, 0), 1248 &n, &m); 1249 } 1250 1251 switch (clk_id) { 1252 case SCLK_UART0: 1253 id = 6; 1254 sel_shift = SCLK_UART0_SRC_SEL_SHIFT; 1255 sel_mask = SCLK_UART0_SRC_SEL_MASK; 1256 div_shift = CLK_UART0_SRC_DIV_SHIFT; 1257 div_mask = CLK_UART0_SRC_DIV_MASK; 1258 break; 1259 1260 case SCLK_UART1: 1261 id = 8; 1262 sel_shift = SCLK_UART1_SRC_SEL_SHIFT; 1263 sel_mask = SCLK_UART1_SRC_SEL_MASK; 1264 div_shift = CLK_UART1_SRC_DIV_SHIFT; 1265 div_mask = CLK_UART1_SRC_DIV_MASK; 1266 break; 1267 1268 case SCLK_UART2: 1269 id = 10; 1270 sel_shift = SCLK_UART2_SRC_SEL_SHIFT; 1271 sel_mask = SCLK_UART2_SRC_SEL_MASK; 1272 div_shift = CLK_UART2_SRC_DIV_SHIFT; 1273 div_mask = CLK_UART2_SRC_DIV_MASK; 1274 break; 1275 1276 case SCLK_UART3: 1277 id = 12; 1278 sel_shift = SCLK_UART3_SRC_SEL_SHIFT; 1279 sel_mask = SCLK_UART3_SRC_SEL_MASK; 1280 div_shift = CLK_UART3_SRC_DIV_SHIFT; 1281 div_mask = CLK_UART3_SRC_DIV_MASK; 1282 break; 1283 1284 case SCLK_UART4: 1285 id = 14; 1286 sel_shift = SCLK_UART4_SRC_SEL_SHIFT; 1287 sel_mask = SCLK_UART4_SRC_SEL_MASK; 1288 div_shift = CLK_UART4_SRC_DIV_SHIFT; 1289 div_mask = CLK_UART4_SRC_DIV_MASK; 1290 break; 1291 1292 case SCLK_UART5: 1293 id = 16; 1294 sel_shift = SCLK_UART5_SRC_SEL_SHIFT; 1295 sel_mask = SCLK_UART5_SRC_SEL_MASK; 1296 div_shift = CLK_UART5_SRC_DIV_SHIFT; 1297 div_mask = CLK_UART5_SRC_DIV_MASK; 1298 break; 1299 1300 case SCLK_UART6: 1301 id = 18; 1302 sel_shift = SCLK_UART6_SRC_SEL_SHIFT; 1303 sel_mask = SCLK_UART6_SRC_SEL_MASK; 1304 div_shift = CLK_UART6_SRC_DIV_SHIFT; 1305 div_mask = CLK_UART6_SRC_DIV_MASK; 1306 break; 1307 1308 case SCLK_UART7: 1309 id = 20; 1310 sel_shift = SCLK_UART7_SRC_SEL_SHIFT; 1311 sel_mask = SCLK_UART7_SRC_SEL_MASK; 1312 div_shift = CLK_UART7_SRC_DIV_SHIFT; 1313 div_mask = CLK_UART7_SRC_DIV_MASK; 1314 break; 1315 1316 default: 1317 return -ENOENT; 1318 } 1319 1320 rk_clrsetreg(&cru->clksel_con[id - 2], div_mask, (div - 1) << div_shift); 1321 rk_clrsetreg(&cru->clksel_con[id], sel_mask, sel << sel_shift); 1322 if (m && n) { 1323 val = n << 16 | m; 1324 writel(val, &cru->clksel_con[id - 1]); 1325 } 1326 1327 return rk3528_uart_get_rate(priv, clk_id); 1328 } 1329 1330 static ulong rk3528_clk_get_rate(struct clk *clk) 1331 { 1332 struct rk3528_clk_priv *priv = dev_get_priv(clk->dev); 1333 ulong rate = 0; 1334 1335 if (!priv->gpll_hz || !priv->cpll_hz) { 1336 printf("%s: gpll=%lu, cpll=%ld\n", 1337 __func__, priv->gpll_hz, priv->cpll_hz); 1338 return -ENOENT; 1339 } 1340 1341 switch (clk->id) { 1342 case PLL_APLL: 1343 case ARMCLK: 1344 rate = rockchip_pll_get_rate(&rk3528_pll_clks[APLL], priv->cru, 1345 APLL); 1346 break; 1347 case PLL_CPLL: 1348 rate = rockchip_pll_get_rate(&rk3528_pll_clks[CPLL], priv->cru, 1349 CPLL); 1350 break; 1351 case PLL_GPLL: 1352 rate = rockchip_pll_get_rate(&rk3528_pll_clks[GPLL], priv->cru, 1353 GPLL); 1354 break; 1355 1356 case PLL_PPLL: 1357 rate = rockchip_pll_get_rate(&rk3528_pll_clks[PPLL], priv->cru, 1358 PPLL); 1359 break; 1360 case PLL_DPLL: 1361 rate = rockchip_pll_get_rate(&rk3528_pll_clks[DPLL], priv->cru, 1362 DPLL); 1363 break; 1364 1365 case TCLK_WDT_NS: 1366 rate = OSC_HZ; 1367 break; 1368 case CLK_I2C0: 1369 case CLK_I2C1: 1370 case CLK_I2C2: 1371 case CLK_I2C3: 1372 case CLK_I2C4: 1373 case CLK_I2C5: 1374 case CLK_I2C6: 1375 case CLK_I2C7: 1376 rate = rk3528_i2c_get_clk(priv, clk->id); 1377 break; 1378 case CLK_SPI0: 1379 case CLK_SPI1: 1380 rate = rk3528_spi_get_clk(priv, clk->id); 1381 break; 1382 case CLK_PWM0: 1383 case CLK_PWM1: 1384 rate = rk3528_pwm_get_clk(priv, clk->id); 1385 break; 1386 case CLK_SARADC: 1387 case CLK_TSADC: 1388 case CLK_TSADC_TSEN: 1389 rate = rk3528_adc_get_clk(priv, clk->id); 1390 break; 1391 case CCLK_SRC_EMMC: 1392 rate = rk3528_emmc_get_clk(priv); 1393 break; 1394 case HCLK_SDMMC0: 1395 case CCLK_SRC_SDMMC0: 1396 rate = rk3528_sdmmc_get_clk(priv, clk->id); 1397 break; 1398 case SCLK_SFC: 1399 rate = rk3528_sfc_get_clk(priv); 1400 break; 1401 case DCLK_VOP0: 1402 case DCLK_VOP1: 1403 rate = rk3528_dclk_vop_get_clk(priv, clk->id); 1404 break; 1405 case DCLK_CVBS: 1406 rate = rk3528_dclk_vop_get_clk(priv, DCLK_VOP1) / 4; 1407 break; 1408 case DCLK_4X_CVBS: 1409 rate = rk3528_dclk_vop_get_clk(priv, DCLK_VOP1); 1410 break; 1411 case SCLK_UART0: 1412 case SCLK_UART1: 1413 case SCLK_UART2: 1414 case SCLK_UART3: 1415 case SCLK_UART4: 1416 case SCLK_UART5: 1417 case SCLK_UART6: 1418 case SCLK_UART7: 1419 rate = rk3528_uart_get_rate(priv, clk->id); 1420 break; 1421 case CLK_MATRIX_50M_SRC: 1422 case CLK_MATRIX_100M_SRC: 1423 case CLK_MATRIX_150M_SRC: 1424 case CLK_MATRIX_200M_SRC: 1425 case CLK_MATRIX_250M_SRC: 1426 case CLK_MATRIX_300M_SRC: 1427 case CLK_MATRIX_339M_SRC: 1428 case CLK_MATRIX_400M_SRC: 1429 case CLK_MATRIX_500M_SRC: 1430 case CLK_MATRIX_600M_SRC: 1431 case ACLK_BUS_VOPGL_BIU: 1432 rate = rk3528_cgpll_matrix_get_rate(priv, clk->id); 1433 break; 1434 case CLK_PPLL_50M_MATRIX: 1435 case CLK_PPLL_100M_MATRIX: 1436 case CLK_PPLL_125M_MATRIX: 1437 case CLK_GMAC1_VPU_25M: 1438 case CLK_GMAC1_RMII_VPU: 1439 case CLK_GMAC1_SRC_VPU: 1440 rate = rk3528_ppll_matrix_get_rate(priv, clk->id); 1441 break; 1442 default: 1443 return -ENOENT; 1444 } 1445 1446 return rate; 1447 }; 1448 1449 static ulong rk3528_clk_set_rate(struct clk *clk, ulong rate) 1450 { 1451 struct rk3528_clk_priv *priv = dev_get_priv(clk->dev); 1452 ulong ret = 0; 1453 1454 if (!priv->gpll_hz) { 1455 printf("%s gpll=%lu\n", __func__, priv->gpll_hz); 1456 return -ENOENT; 1457 } 1458 1459 switch (clk->id) { 1460 case PLL_APLL: 1461 case ARMCLK: 1462 if (priv->armclk_hz) 1463 rk3528_armclk_set_clk(priv, rate); 1464 priv->armclk_hz = rate; 1465 break; 1466 case PLL_CPLL: 1467 ret = rockchip_pll_set_rate(&rk3528_pll_clks[CPLL], priv->cru, 1468 CPLL, rate); 1469 priv->cpll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[CPLL], 1470 priv->cru, CPLL); 1471 break; 1472 case PLL_GPLL: 1473 ret = rockchip_pll_set_rate(&rk3528_pll_clks[GPLL], priv->cru, 1474 GPLL, rate); 1475 priv->gpll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[GPLL], 1476 priv->cru, GPLL); 1477 break; 1478 case PLL_PPLL: 1479 ret = rockchip_pll_set_rate(&rk3528_pll_clks[PPLL], priv->cru, 1480 PPLL, rate); 1481 priv->ppll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[PPLL], 1482 priv->cru, PPLL); 1483 break; 1484 case TCLK_WDT_NS: 1485 return (rate == OSC_HZ) ? 0 : -EINVAL; 1486 case CLK_I2C0: 1487 case CLK_I2C1: 1488 case CLK_I2C2: 1489 case CLK_I2C3: 1490 case CLK_I2C4: 1491 case CLK_I2C5: 1492 case CLK_I2C6: 1493 case CLK_I2C7: 1494 ret = rk3528_i2c_set_clk(priv, clk->id, rate); 1495 break; 1496 case CLK_SPI0: 1497 case CLK_SPI1: 1498 ret = rk3528_spi_set_clk(priv, clk->id, rate); 1499 break; 1500 case CLK_PWM0: 1501 case CLK_PWM1: 1502 ret = rk3528_pwm_set_clk(priv, clk->id, rate); 1503 break; 1504 case CLK_SARADC: 1505 case CLK_TSADC: 1506 case CLK_TSADC_TSEN: 1507 ret = rk3528_adc_set_clk(priv, clk->id, rate); 1508 break; 1509 case HCLK_SDMMC0: 1510 case CCLK_SRC_SDMMC0: 1511 ret = rk3528_sdmmc_set_clk(priv, clk->id, rate); 1512 break; 1513 case SCLK_SFC: 1514 ret = rk3528_sfc_set_clk(priv, rate); 1515 break; 1516 case CCLK_SRC_EMMC: 1517 ret = rk3528_emmc_set_clk(priv, rate); 1518 break; 1519 case DCLK_VOP0: 1520 case DCLK_VOP1: 1521 ret = rk3528_dclk_vop_set_clk(priv, clk->id, rate); 1522 break; 1523 case SCLK_UART0: 1524 case SCLK_UART1: 1525 case SCLK_UART2: 1526 case SCLK_UART3: 1527 case SCLK_UART4: 1528 case SCLK_UART5: 1529 case SCLK_UART6: 1530 case SCLK_UART7: 1531 ret = rk3528_uart_set_rate(priv, clk->id, rate); 1532 break; 1533 case CLK_MATRIX_50M_SRC: 1534 case CLK_MATRIX_100M_SRC: 1535 case CLK_MATRIX_150M_SRC: 1536 case CLK_MATRIX_200M_SRC: 1537 case CLK_MATRIX_250M_SRC: 1538 case CLK_MATRIX_300M_SRC: 1539 case CLK_MATRIX_339M_SRC: 1540 case CLK_MATRIX_400M_SRC: 1541 case CLK_MATRIX_500M_SRC: 1542 case CLK_MATRIX_600M_SRC: 1543 case ACLK_BUS_VOPGL_BIU: 1544 ret = rk3528_cgpll_matrix_set_rate(priv, clk->id, rate); 1545 break; 1546 case CLK_PPLL_50M_MATRIX: 1547 case CLK_PPLL_100M_MATRIX: 1548 case CLK_PPLL_125M_MATRIX: 1549 case CLK_GMAC1_VPU_25M: 1550 ret = rk3528_ppll_matrix_set_rate(priv, clk->id, rate); 1551 break; 1552 case CLK_GMAC1_RMII_VPU: 1553 case CLK_GMAC1_SRC_VPU: 1554 /* dummy set */ 1555 ret = rk3528_ppll_matrix_get_rate(priv, clk->id); 1556 break; 1557 default: 1558 return -ENOENT; 1559 } 1560 1561 return ret; 1562 }; 1563 1564 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 1565 static int rk3528_clk_set_parent(struct clk *clk, struct clk *parent) 1566 { 1567 struct rk3528_clk_priv *priv = dev_get_priv(clk->dev); 1568 const char *clock_dev_name = parent->dev->name; 1569 1570 switch (clk->id) { 1571 case DCLK_VOP0: 1572 if (!strcmp(clock_dev_name, "inno_hdmi_pll_clk")) 1573 /* clk_hdmiphy_pixel_io */ 1574 rk_clrsetreg(&priv->cru->clksel_con[84], 0x1, 1); 1575 else 1576 rk_clrsetreg(&priv->cru->clksel_con[84], 0x1, 0); 1577 break; 1578 1579 default: 1580 return -ENOENT; 1581 } 1582 1583 return 0; 1584 } 1585 #endif 1586 1587 static struct clk_ops rk3528_clk_ops = { 1588 .get_rate = rk3528_clk_get_rate, 1589 .set_rate = rk3528_clk_set_rate, 1590 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 1591 .set_parent = rk3528_clk_set_parent, 1592 #endif 1593 }; 1594 1595 static ulong rk3528_grfclk_get_rate(struct clk *clk) 1596 { 1597 struct rk3528_clk_priv *priv; 1598 struct udevice *cru_dev; 1599 ulong rate = 0; 1600 int ret; 1601 1602 ret = uclass_get_device_by_driver(UCLASS_CLK, 1603 DM_GET_DRIVER(rockchip_rk3528_cru), 1604 &cru_dev); 1605 if (ret) { 1606 printf("%s: could not find cru device\n", __func__); 1607 return ret; 1608 } 1609 priv = dev_get_priv(cru_dev); 1610 1611 switch (clk->id) { 1612 case SCLK_SDMMC_SAMPLE: 1613 rate = rk3528_sdmmc_get_clk(priv, CCLK_SRC_SDMMC0) / 2; 1614 break; 1615 default: 1616 return -ENOENT; 1617 } 1618 1619 return rate; 1620 }; 1621 1622 #define ROCKCHIP_MMC_DELAY_SEL BIT(11) 1623 #define ROCKCHIP_MMC_DEGREE_MASK 0x3 1624 #define ROCKCHIP_MMC_DELAYNUM_OFFSET 3 1625 #define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET) 1626 #define PSECS_PER_SEC 1000000000000LL 1627 /* 1628 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to 1629 * simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg. 1630 */ 1631 #define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60 1632 1633 int rk3528_mmc_get_phase(struct clk *clk) 1634 { 1635 struct rk3528_grf_clk_priv *priv = dev_get_priv(clk->dev); 1636 u32 raw_value = 0, delay_num; 1637 u16 degrees = 0; 1638 ulong rate; 1639 1640 rate = rk3528_grfclk_get_rate(clk); 1641 if (rate < 0) 1642 return rate; 1643 1644 if (clk->id == SCLK_SDMMC_SAMPLE) 1645 raw_value = readl(&priv->grf->sdmmc_con1); 1646 else 1647 return -ENONET; 1648 1649 raw_value >>= 1; 1650 degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90; 1651 1652 if (raw_value & ROCKCHIP_MMC_DELAY_SEL) { 1653 /* degrees/delaynum * 10000 */ 1654 unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) * 1655 36 * (rate / 1000000); 1656 1657 delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK); 1658 delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET; 1659 degrees += DIV_ROUND_CLOSEST(delay_num * factor, 10000); 1660 } 1661 1662 return degrees % 360; 1663 } 1664 1665 int rk3528_mmc_set_phase(struct clk *clk, u32 degrees) 1666 { 1667 struct rk3528_grf_clk_priv *priv = dev_get_priv(clk->dev); 1668 u8 nineties, remainder, delay_num; 1669 u32 raw_value, delay; 1670 ulong rate; 1671 1672 rate = rk3528_grfclk_get_rate(clk); 1673 if (rate < 0) 1674 return rate; 1675 1676 nineties = degrees / 90; 1677 remainder = (degrees % 90); 1678 1679 /* 1680 * Convert to delay; do a little extra work to make sure we 1681 * don't overflow 32-bit / 64-bit numbers. 1682 */ 1683 delay = 10000000; /* PSECS_PER_SEC / 10000 / 10 */ 1684 delay *= remainder; 1685 delay = DIV_ROUND_CLOSEST(delay, (rate / 1000) * 36 * 1686 (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10)); 1687 1688 delay_num = (u8)min_t(u32, delay, 255); 1689 1690 raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0; 1691 raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET; 1692 raw_value |= nineties; 1693 1694 raw_value <<= 1; 1695 if (clk->id == SCLK_SDMMC_SAMPLE) 1696 writel(raw_value | 0xffff0000, &priv->grf->sdmmc_con1); 1697 else 1698 return -ENONET; 1699 1700 debug("mmc set_phase(%d) delay_nums=%u reg=%#x actual_degrees=%d\n", 1701 degrees, delay_num, raw_value, rk3528_mmc_get_phase(clk)); 1702 1703 return 0; 1704 } 1705 1706 static int rk3528_grfclk_get_phase(struct clk *clk) 1707 { 1708 int ret; 1709 1710 debug("%s %ld\n", __func__, clk->id); 1711 switch (clk->id) { 1712 case SCLK_SDMMC_SAMPLE: 1713 ret = rk3528_mmc_get_phase(clk); 1714 break; 1715 default: 1716 return -ENOENT; 1717 } 1718 1719 return ret; 1720 } 1721 1722 static int rk3528_grfclk_set_phase(struct clk *clk, int degrees) 1723 { 1724 int ret; 1725 1726 debug("%s %ld\n", __func__, clk->id); 1727 switch (clk->id) { 1728 case SCLK_SDMMC_SAMPLE: 1729 ret = rk3528_mmc_set_phase(clk, degrees); 1730 break; 1731 default: 1732 return -ENOENT; 1733 } 1734 1735 return ret; 1736 } 1737 1738 static struct clk_ops rk3528_grfclk_ops = { 1739 .get_rate = rk3528_grfclk_get_rate, 1740 .get_phase = rk3528_grfclk_get_phase, 1741 .set_phase = rk3528_grfclk_set_phase, 1742 }; 1743 1744 #ifndef CONFIG_SPL_BUILD 1745 /** 1746 * soc_clk_dump() - Print clock frequencies 1747 * Returns zero on success 1748 * 1749 * Implementation for the clk dump command. 1750 */ 1751 int soc_clk_dump(void) 1752 { 1753 const struct rk3528_clk_info *clk_dump; 1754 struct rk3528_clk_priv *priv; 1755 struct udevice *cru_dev; 1756 struct clk clk; 1757 ulong clk_count = ARRAY_SIZE(clks_dump); 1758 ulong rate; 1759 int i, ret; 1760 1761 ret = uclass_get_device_by_driver(UCLASS_CLK, 1762 DM_GET_DRIVER(rockchip_rk3528_cru), 1763 &cru_dev); 1764 if (ret) { 1765 printf("%s failed to get cru device\n", __func__); 1766 return ret; 1767 } 1768 1769 priv = dev_get_priv(cru_dev); 1770 printf("CLK: (%s. arm: enter %lu KHz, init %lu KHz, kernel %lu%s)\n", 1771 priv->sync_kernel ? "sync kernel" : "uboot", 1772 priv->armclk_enter_hz / 1000, 1773 priv->armclk_init_hz / 1000, 1774 priv->set_armclk_rate ? priv->armclk_hz / 1000 : 0, 1775 priv->set_armclk_rate ? " KHz" : "N/A"); 1776 for (i = 0; i < clk_count; i++) { 1777 clk_dump = &clks_dump[i]; 1778 if (clk_dump->name) { 1779 clk.id = clk_dump->id; 1780 ret = clk_request(cru_dev, &clk); 1781 if (ret < 0) 1782 return ret; 1783 1784 rate = clk_get_rate(&clk); 1785 clk_free(&clk); 1786 if (i == 0) { 1787 if (rate < 0) 1788 printf(" %s %s\n", clk_dump->name, 1789 "unknown"); 1790 else 1791 printf(" %s %lu KHz\n", clk_dump->name, 1792 rate / 1000); 1793 } else { 1794 if (rate < 0) 1795 printf(" %s %s\n", clk_dump->name, 1796 "unknown"); 1797 else 1798 printf(" %s %lu KHz\n", clk_dump->name, 1799 rate / 1000); 1800 } 1801 } 1802 } 1803 1804 return 0; 1805 } 1806 #endif 1807 1808 static int rk3528_grfclk_probe(struct udevice *dev) 1809 { 1810 struct rk3528_grf_clk_priv *priv = dev_get_priv(dev); 1811 1812 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1813 if (IS_ERR(priv->grf)) 1814 return PTR_ERR(priv->grf); 1815 1816 return 0; 1817 } 1818 1819 static const struct udevice_id rk3528_grf_cru_ids[] = { 1820 { .compatible = "rockchip,rk3528-grf-cru" }, 1821 { } 1822 }; 1823 1824 U_BOOT_DRIVER(rockchip_rk3528_grf_cru) = { 1825 .name = "rockchip_rk3528_grf_cru", 1826 .id = UCLASS_CLK, 1827 .of_match = rk3528_grf_cru_ids, 1828 .priv_auto_alloc_size = sizeof(struct rk3528_grf_clk_priv), 1829 .ops = &rk3528_grfclk_ops, 1830 .probe = rk3528_grfclk_probe, 1831 }; 1832 1833 static int rk3528_clk_init(struct rk3528_clk_priv *priv) 1834 { 1835 int ret; 1836 1837 priv->sync_kernel = false; 1838 1839 #ifdef CONFIG_SPL_BUILD 1840 if (!priv->armclk_enter_hz) { 1841 priv->armclk_enter_hz = 1842 rockchip_pll_get_rate(&rk3528_pll_clks[APLL], 1843 priv->cru, APLL); 1844 priv->armclk_init_hz = priv->armclk_enter_hz; 1845 } 1846 1847 if (priv->armclk_init_hz != APLL_HZ) { 1848 ret = rk3528_armclk_set_clk(priv, APLL_HZ); 1849 if (!ret) 1850 priv->armclk_init_hz = APLL_HZ; 1851 } 1852 #else 1853 if (!priv->armclk_enter_hz) { 1854 struct clk clk; 1855 1856 ret = rockchip_get_scmi_clk(&clk.dev); 1857 if (ret) { 1858 printf("Failed to get scmi clk dev\n"); 1859 return ret; 1860 } 1861 1862 clk.id = SCMI_CLK_CPU; 1863 ret = clk_set_rate(&clk, CPU_PVTPLL_HZ); 1864 if (ret < 0) { 1865 printf("Failed to set scmi cpu %dhz\n", CPU_PVTPLL_HZ); 1866 return ret; 1867 } else { 1868 priv->armclk_enter_hz = 1869 rockchip_pll_get_rate(&rk3528_pll_clks[APLL], 1870 priv->cru, APLL); 1871 priv->armclk_init_hz = CPU_PVTPLL_HZ; 1872 } 1873 } 1874 #endif 1875 if (priv->cpll_hz != CPLL_HZ) { 1876 ret = rockchip_pll_set_rate(&rk3528_pll_clks[CPLL], priv->cru, 1877 CPLL, CPLL_HZ); 1878 if (!ret) 1879 priv->cpll_hz = CPLL_HZ; 1880 } 1881 1882 if (priv->gpll_hz != GPLL_HZ) { 1883 ret = rockchip_pll_set_rate(&rk3528_pll_clks[GPLL], priv->cru, 1884 GPLL, GPLL_HZ); 1885 if (!ret) 1886 priv->gpll_hz = GPLL_HZ; 1887 } 1888 1889 if (priv->ppll_hz != PPLL_HZ) { 1890 ret = rockchip_pll_set_rate(&rk3528_pll_clks[PPLL], priv->cru, 1891 PPLL, PPLL_HZ); 1892 if (!ret) 1893 priv->ppll_hz = PPLL_HZ; 1894 } 1895 1896 #ifdef CONFIG_SPL_BUILD 1897 /* Init to override bootrom config */ 1898 rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_50M_SRC, 50000000); 1899 rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_100M_SRC, 100000000); 1900 rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_150M_SRC, 150000000); 1901 rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_200M_SRC, 200000000); 1902 rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_250M_SRC, 250000000); 1903 rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_300M_SRC, 300000000); 1904 rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_339M_SRC, 340000000); 1905 rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_400M_SRC, 400000000); 1906 rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_500M_SRC, 500000000); 1907 rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_600M_SRC, 600000000); 1908 rk3528_cgpll_matrix_set_rate(priv, ACLK_BUS_VOPGL_BIU, 500000000); 1909 1910 /* The default rate is 100Mhz, it's not friendly for remote IR module */ 1911 rk3528_pwm_set_clk(priv, CLK_PWM0, 24000000); 1912 rk3528_pwm_set_clk(priv, CLK_PWM1, 24000000); 1913 #endif 1914 return 0; 1915 } 1916 1917 static int rk3528_clk_probe(struct udevice *dev) 1918 { 1919 struct rk3528_clk_priv *priv = dev_get_priv(dev); 1920 int ret; 1921 1922 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1923 if (IS_ERR(priv->grf)) 1924 return PTR_ERR(priv->grf); 1925 1926 ret = rk3528_clk_init(priv); 1927 if (ret) 1928 return ret; 1929 1930 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 1931 ret = clk_set_defaults(dev); 1932 if (ret) 1933 debug("%s clk_set_defaults failed %d\n", __func__, ret); 1934 else 1935 priv->sync_kernel = true; 1936 1937 return 0; 1938 } 1939 1940 static int rk3528_clk_ofdata_to_platdata(struct udevice *dev) 1941 { 1942 struct rk3528_clk_priv *priv = dev_get_priv(dev); 1943 1944 priv->cru = dev_read_addr_ptr(dev); 1945 1946 return 0; 1947 } 1948 1949 static int rk3528_clk_bind(struct udevice *dev) 1950 { 1951 struct udevice *sys_child, *sf_child; 1952 struct softreset_reg *sf_priv; 1953 struct sysreset_reg *priv; 1954 int ret; 1955 1956 /* The reset driver does not have a device node, so bind it here */ 1957 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", 1958 &sys_child); 1959 if (ret) { 1960 debug("Warning: No sysreset driver: ret=%d\n", ret); 1961 } else { 1962 priv = malloc(sizeof(struct sysreset_reg)); 1963 priv->glb_srst_fst_value = offsetof(struct rk3528_cru, 1964 glb_srst_fst); 1965 priv->glb_srst_snd_value = offsetof(struct rk3528_cru, 1966 glb_srst_snd); 1967 sys_child->priv = priv; 1968 } 1969 1970 ret = device_bind_driver_to_node(dev, "rockchip_reset", "reset", 1971 dev_ofnode(dev), &sf_child); 1972 if (ret) { 1973 debug("Warning: No rockchip reset driver: ret=%d\n", ret); 1974 } else { 1975 sf_priv = malloc(sizeof(struct softreset_reg)); 1976 sf_priv->sf_reset_offset = offsetof(struct rk3528_cru, 1977 softrst_con[0]); 1978 sf_priv->sf_reset_num = 47; 1979 sf_child->priv = sf_priv; 1980 } 1981 1982 return 0; 1983 } 1984 1985 static const struct udevice_id rk3528_clk_ids[] = { 1986 { .compatible = "rockchip,rk3528-cru" }, 1987 { } 1988 }; 1989 1990 U_BOOT_DRIVER(rockchip_rk3528_cru) = { 1991 .name = "rockchip_rk3528_cru", 1992 .id = UCLASS_CLK, 1993 .of_match = rk3528_clk_ids, 1994 .priv_auto_alloc_size = sizeof(struct rk3528_clk_priv), 1995 .ofdata_to_platdata = rk3528_clk_ofdata_to_platdata, 1996 .ops = &rk3528_clk_ops, 1997 .bind = rk3528_clk_bind, 1998 .probe = rk3528_clk_probe, 1999 }; 2000 2001 /* spl scmi clk */ 2002 #ifdef CONFIG_SPL_BUILD 2003 2004 static ulong rk3528_crypto_get_rate(struct rk3528_clk_priv *priv, struct clk *clk) 2005 { 2006 struct rk3528_cru *cru = priv->cru; 2007 u32 id, sel, con, mask, shift; 2008 ulong rate; 2009 2010 switch (clk->id) { 2011 case SCMI_CORE_CRYPTO: 2012 id = 43; 2013 mask = CLK_CORE_CRYPTO_SEL_MASK; 2014 shift = CLK_CORE_CRYPTO_SEL_SHIFT; 2015 break; 2016 2017 case SCMI_PKA_CRYPTO: 2018 id = 44; 2019 mask = CLK_PKA_CRYPTO_SEL_MASK; 2020 shift = CLK_PKA_CRYPTO_SEL_SHIFT; 2021 break; 2022 2023 default: 2024 return -ENOENT; 2025 } 2026 2027 con = readl(&cru->clksel_con[id]); 2028 sel = (con & mask) >> shift; 2029 if (sel == CLK_CORE_CRYPTO_SEL_CLK_MATRIX_300M_SRC) 2030 rate = 300 * MHz; 2031 else if (sel == CLK_CORE_CRYPTO_SEL_CLK_MATRIX_200M_SRC) 2032 rate = 200 * MHz; 2033 else if (sel == CLK_CORE_CRYPTO_SEL_CLK_MATRIX_100M_SRC) 2034 rate = 100 * MHz; 2035 else 2036 rate = OSC_HZ; 2037 2038 return rate; 2039 } 2040 2041 static ulong rk3528_crypto_set_rate(struct rk3528_clk_priv *priv, 2042 struct clk *clk, ulong rate) 2043 { 2044 struct rk3528_cru *cru = priv->cru; 2045 u32 id, sel, mask, shift; 2046 2047 if (rate == 300 * MHz) 2048 sel = CLK_CORE_CRYPTO_SEL_CLK_MATRIX_300M_SRC; 2049 else if (rate == 200 * MHz) 2050 sel = CLK_CORE_CRYPTO_SEL_CLK_MATRIX_200M_SRC; 2051 else if (rate == 100 * MHz) 2052 sel = CLK_CORE_CRYPTO_SEL_CLK_MATRIX_100M_SRC; 2053 else 2054 sel = CLK_CORE_CRYPTO_SEL_XIN_OSC0_FUNC; 2055 2056 switch (clk->id) { 2057 case SCMI_CORE_CRYPTO: 2058 id = 43; 2059 mask = CLK_CORE_CRYPTO_SEL_MASK; 2060 shift = CLK_CORE_CRYPTO_SEL_SHIFT; 2061 break; 2062 2063 case SCMI_PKA_CRYPTO: 2064 id = 44; 2065 mask = CLK_PKA_CRYPTO_SEL_MASK; 2066 shift = CLK_PKA_CRYPTO_SEL_SHIFT; 2067 break; 2068 2069 default: 2070 return -ENOENT; 2071 } 2072 2073 rk_clrsetreg(&cru->clksel_con[id], mask, sel << shift); 2074 2075 return rk3528_crypto_get_rate(priv, clk); 2076 } 2077 2078 static ulong rk3528_clk_scmi_get_rate(struct clk *clk) 2079 { 2080 struct rk3528_clk_priv *priv = dev_get_priv(clk->dev); 2081 2082 switch (clk->id) { 2083 case SCMI_CORE_CRYPTO: 2084 case SCMI_PKA_CRYPTO: 2085 return rk3528_crypto_get_rate(priv, clk); 2086 default: 2087 return -ENOENT; 2088 } 2089 }; 2090 2091 static ulong rk3528_clk_scmi_set_rate(struct clk *clk, ulong rate) 2092 { 2093 struct rk3528_clk_priv *priv = dev_get_priv(clk->dev); 2094 2095 switch (clk->id) { 2096 case SCMI_CORE_CRYPTO: 2097 case SCMI_PKA_CRYPTO: 2098 return rk3528_crypto_set_rate(priv, clk, rate); 2099 default: 2100 return -ENOENT; 2101 } 2102 2103 return 0; 2104 }; 2105 2106 static int rk3528_scmi_clk_ofdata_to_platdata(struct udevice *dev) 2107 { 2108 struct rk3528_clk_priv *priv = dev_get_priv(dev); 2109 2110 priv->cru = (struct rk3528_cru *)0xff4a0000; 2111 2112 return 0; 2113 } 2114 2115 /* A fake scmi driver for SPL/TPL where smccc agent is not available. */ 2116 static const struct clk_ops scmi_clk_ops = { 2117 .get_rate = rk3528_clk_scmi_get_rate, 2118 .set_rate = rk3528_clk_scmi_set_rate, 2119 }; 2120 2121 U_BOOT_DRIVER(scmi_clock) = { 2122 .name = "scmi_clk", 2123 .id = UCLASS_CLK, 2124 .ops = &scmi_clk_ops, 2125 .priv_auto_alloc_size = sizeof(struct rk3528_clk_priv), 2126 .ofdata_to_platdata = rk3528_scmi_clk_ofdata_to_platdata, 2127 }; 2128 #endif 2129