1 /* 2 * (C) Copyright 2015 Google, Inc 3 * (C) 2017 Theobroma Systems Design und Consulting GmbH 4 * 5 * SPDX-License-Identifier: GPL-2.0 6 */ 7 8 #include <common.h> 9 #include <clk-uclass.h> 10 #include <dm.h> 11 #include <dt-structs.h> 12 #include <errno.h> 13 #include <mapmem.h> 14 #include <syscon.h> 15 #include <bitfield.h> 16 #include <asm/io.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/cru_rk3399.h> 19 #include <asm/arch/hardware.h> 20 #include <dm/lists.h> 21 #include <dt-bindings/clock/rk3399-cru.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #if CONFIG_IS_ENABLED(OF_PLATDATA) 26 struct rk3399_clk_plat { 27 struct dtd_rockchip_rk3399_cru dtd; 28 }; 29 30 struct rk3399_pmuclk_plat { 31 struct dtd_rockchip_rk3399_pmucru dtd; 32 }; 33 #endif 34 35 struct pll_div { 36 u32 refdiv; 37 u32 fbdiv; 38 u32 postdiv1; 39 u32 postdiv2; 40 u32 frac; 41 u32 freq; 42 }; 43 44 #define RATE_TO_DIV(input_rate, output_rate) \ 45 ((input_rate) / (output_rate) - 1); 46 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) 47 48 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ 49 .refdiv = _refdiv,\ 50 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\ 51 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2, .freq = hz}; 52 53 #if !defined(CONFIG_SPL_BUILD) 54 static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1); 55 #endif 56 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 3, 1); 57 static const struct pll_div npll_init_cfg = PLL_DIVISORS(NPLL_HZ, 1, 3, 1); 58 static const struct pll_div apll_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1); 59 static const struct pll_div apll_816_cfg = PLL_DIVISORS(816 * MHz, 1, 2, 1); 60 static const struct pll_div apll_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1); 61 62 static const struct pll_div *apll_cfgs[] = { 63 [APLL_1600_MHZ] = &apll_1600_cfg, 64 [APLL_816_MHZ] = &apll_816_cfg, 65 [APLL_600_MHZ] = &apll_600_cfg, 66 }; 67 68 #ifndef CONFIG_SPL_BUILD 69 #define RK3399_CLK_DUMP(_id, _name, _iscru) \ 70 { \ 71 .id = _id, \ 72 .name = _name, \ 73 .is_cru = _iscru, \ 74 } 75 76 static const struct rk3399_clk_info clks_dump[] = { 77 RK3399_CLK_DUMP(PLL_APLLL, "aplll", true), 78 RK3399_CLK_DUMP(PLL_APLLB, "apllb", true), 79 RK3399_CLK_DUMP(PLL_DPLL, "dpll", true), 80 RK3399_CLK_DUMP(PLL_CPLL, "cpll", true), 81 RK3399_CLK_DUMP(PLL_GPLL, "gpll", true), 82 RK3399_CLK_DUMP(PLL_NPLL, "npll", true), 83 RK3399_CLK_DUMP(PLL_VPLL, "vpll", true), 84 RK3399_CLK_DUMP(ACLK_PERIHP, "aclk_perihp", true), 85 RK3399_CLK_DUMP(HCLK_PERIHP, "hclk_perihp", true), 86 RK3399_CLK_DUMP(PCLK_PERIHP, "pclk_perihp", true), 87 RK3399_CLK_DUMP(ACLK_PERILP0, "aclk_perilp0", true), 88 RK3399_CLK_DUMP(HCLK_PERILP0, "hclk_perilp0", true), 89 RK3399_CLK_DUMP(PCLK_PERILP0, "pclk_perilp0", true), 90 RK3399_CLK_DUMP(HCLK_PERILP1, "hclk_perilp1", true), 91 RK3399_CLK_DUMP(PCLK_PERILP1, "pclk_perilp1", true), 92 }; 93 #endif 94 95 enum { 96 /* PLL_CON0 */ 97 PLL_FBDIV_MASK = 0xfff, 98 PLL_FBDIV_SHIFT = 0, 99 100 /* PLL_CON1 */ 101 PLL_POSTDIV2_SHIFT = 12, 102 PLL_POSTDIV2_MASK = 0x7 << PLL_POSTDIV2_SHIFT, 103 PLL_POSTDIV1_SHIFT = 8, 104 PLL_POSTDIV1_MASK = 0x7 << PLL_POSTDIV1_SHIFT, 105 PLL_REFDIV_MASK = 0x3f, 106 PLL_REFDIV_SHIFT = 0, 107 108 /* PLL_CON2 */ 109 PLL_LOCK_STATUS_SHIFT = 31, 110 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, 111 PLL_FRACDIV_MASK = 0xffffff, 112 PLL_FRACDIV_SHIFT = 0, 113 114 /* PLL_CON3 */ 115 PLL_MODE_SHIFT = 8, 116 PLL_MODE_MASK = 3 << PLL_MODE_SHIFT, 117 PLL_MODE_SLOW = 0, 118 PLL_MODE_NORM, 119 PLL_MODE_DEEP, 120 PLL_DSMPD_SHIFT = 3, 121 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, 122 PLL_INTEGER_MODE = 1, 123 124 /* PMUCRU_CLKSEL_CON0 */ 125 PMU_PCLK_DIV_CON_MASK = 0x1f, 126 PMU_PCLK_DIV_CON_SHIFT = 0, 127 128 /* PMUCRU_CLKSEL_CON1 */ 129 SPI3_PLL_SEL_SHIFT = 7, 130 SPI3_PLL_SEL_MASK = 1 << SPI3_PLL_SEL_SHIFT, 131 SPI3_PLL_SEL_24M = 0, 132 SPI3_PLL_SEL_PPLL = 1, 133 SPI3_DIV_CON_SHIFT = 0x0, 134 SPI3_DIV_CON_MASK = 0x7f, 135 136 /* PMUCRU_CLKSEL_CON2 */ 137 I2C_DIV_CON_MASK = 0x7f, 138 CLK_I2C8_DIV_CON_SHIFT = 8, 139 CLK_I2C0_DIV_CON_SHIFT = 0, 140 141 /* PMUCRU_CLKSEL_CON3 */ 142 CLK_I2C4_DIV_CON_SHIFT = 0, 143 144 /* CLKSEL_CON0 / CLKSEL_CON2 */ 145 ACLKM_CORE_DIV_CON_MASK = 0x1f, 146 ACLKM_CORE_DIV_CON_SHIFT = 8, 147 CLK_CORE_PLL_SEL_MASK = 3, 148 CLK_CORE_PLL_SEL_SHIFT = 6, 149 CLK_CORE_PLL_SEL_ALPLL = 0x0, 150 CLK_CORE_PLL_SEL_ABPLL = 0x1, 151 CLK_CORE_PLL_SEL_DPLL = 0x10, 152 CLK_CORE_PLL_SEL_GPLL = 0x11, 153 CLK_CORE_DIV_MASK = 0x1f, 154 CLK_CORE_DIV_SHIFT = 0, 155 156 /* CLKSEL_CON1 / CLKSEL_CON3 */ 157 PCLK_DBG_DIV_MASK = 0x1f, 158 PCLK_DBG_DIV_SHIFT = 0x8, 159 ATCLK_CORE_DIV_MASK = 0x1f, 160 ATCLK_CORE_DIV_SHIFT = 0, 161 162 /* CLKSEL_CON14 */ 163 PCLK_PERIHP_DIV_CON_SHIFT = 12, 164 PCLK_PERIHP_DIV_CON_MASK = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT, 165 HCLK_PERIHP_DIV_CON_SHIFT = 8, 166 HCLK_PERIHP_DIV_CON_MASK = 3 << HCLK_PERIHP_DIV_CON_SHIFT, 167 ACLK_PERIHP_PLL_SEL_SHIFT = 7, 168 ACLK_PERIHP_PLL_SEL_MASK = 1 << ACLK_PERIHP_PLL_SEL_SHIFT, 169 ACLK_PERIHP_PLL_SEL_CPLL = 0, 170 ACLK_PERIHP_PLL_SEL_GPLL = 1, 171 ACLK_PERIHP_DIV_CON_SHIFT = 0, 172 ACLK_PERIHP_DIV_CON_MASK = 0x1f, 173 174 /* CLKSEL_CON21 */ 175 ACLK_EMMC_PLL_SEL_SHIFT = 7, 176 ACLK_EMMC_PLL_SEL_MASK = 0x1 << ACLK_EMMC_PLL_SEL_SHIFT, 177 ACLK_EMMC_PLL_SEL_GPLL = 0x1, 178 ACLK_EMMC_DIV_CON_SHIFT = 0, 179 ACLK_EMMC_DIV_CON_MASK = 0x1f, 180 181 /* CLKSEL_CON22 */ 182 CLK_EMMC_PLL_SHIFT = 8, 183 CLK_EMMC_PLL_MASK = 0x7 << CLK_EMMC_PLL_SHIFT, 184 CLK_EMMC_PLL_SEL_GPLL = 0x1, 185 CLK_EMMC_PLL_SEL_24M = 0x5, 186 CLK_EMMC_DIV_CON_SHIFT = 0, 187 CLK_EMMC_DIV_CON_MASK = 0x7f << CLK_EMMC_DIV_CON_SHIFT, 188 189 /* CLKSEL_CON23 */ 190 PCLK_PERILP0_DIV_CON_SHIFT = 12, 191 PCLK_PERILP0_DIV_CON_MASK = 0x7 << PCLK_PERILP0_DIV_CON_SHIFT, 192 HCLK_PERILP0_DIV_CON_SHIFT = 8, 193 HCLK_PERILP0_DIV_CON_MASK = 3 << HCLK_PERILP0_DIV_CON_SHIFT, 194 ACLK_PERILP0_PLL_SEL_SHIFT = 7, 195 ACLK_PERILP0_PLL_SEL_MASK = 1 << ACLK_PERILP0_PLL_SEL_SHIFT, 196 ACLK_PERILP0_PLL_SEL_CPLL = 0, 197 ACLK_PERILP0_PLL_SEL_GPLL = 1, 198 ACLK_PERILP0_DIV_CON_SHIFT = 0, 199 ACLK_PERILP0_DIV_CON_MASK = 0x1f, 200 201 /* CRU_CLK_SEL24_CON */ 202 CRYPTO0_PLL_SEL_SHIFT = 6, 203 CRYPTO0_PLL_SEL_MASK = 3 << CRYPTO0_PLL_SEL_SHIFT, 204 CRYPTO_PLL_SEL_CPLL = 0, 205 CRYPTO_PLL_SEL_GPLL, 206 CRYPTO_PLL_SEL_PPLL = 0, 207 CRYPTO0_DIV_SHIFT = 0, 208 CRYPTO0_DIV_MASK = 0x1f << CRYPTO0_DIV_SHIFT, 209 210 /* CLKSEL_CON25 */ 211 PCLK_PERILP1_DIV_CON_SHIFT = 8, 212 PCLK_PERILP1_DIV_CON_MASK = 0x7 << PCLK_PERILP1_DIV_CON_SHIFT, 213 HCLK_PERILP1_PLL_SEL_SHIFT = 7, 214 HCLK_PERILP1_PLL_SEL_MASK = 1 << HCLK_PERILP1_PLL_SEL_SHIFT, 215 HCLK_PERILP1_PLL_SEL_CPLL = 0, 216 HCLK_PERILP1_PLL_SEL_GPLL = 1, 217 HCLK_PERILP1_DIV_CON_SHIFT = 0, 218 HCLK_PERILP1_DIV_CON_MASK = 0x1f, 219 220 /* CLKSEL_CON26 */ 221 CLK_SARADC_DIV_CON_SHIFT = 8, 222 CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8), 223 CLK_SARADC_DIV_CON_WIDTH = 8, 224 CRYPTO1_PLL_SEL_SHIFT = 6, 225 CRYPTO1_PLL_SEL_MASK = 3 << CRYPTO1_PLL_SEL_SHIFT, 226 CRYPTO1_DIV_SHIFT = 0, 227 CRYPTO1_DIV_MASK = 0x1f << CRYPTO1_DIV_SHIFT, 228 229 /* CLKSEL_CON27 */ 230 CLK_TSADC_SEL_X24M = 0x0, 231 CLK_TSADC_SEL_SHIFT = 15, 232 CLK_TSADC_SEL_MASK = 1 << CLK_TSADC_SEL_SHIFT, 233 CLK_TSADC_DIV_CON_SHIFT = 0, 234 CLK_TSADC_DIV_CON_MASK = 0x3ff, 235 236 /* CLKSEL_CON47 & CLKSEL_CON48 */ 237 ACLK_VOP_PLL_SEL_SHIFT = 6, 238 ACLK_VOP_PLL_SEL_MASK = 0x3 << ACLK_VOP_PLL_SEL_SHIFT, 239 ACLK_VOP_PLL_SEL_CPLL = 0x1, 240 ACLK_VOP_PLL_SEL_GPLL = 0x2, 241 ACLK_VOP_DIV_CON_SHIFT = 0, 242 ACLK_VOP_DIV_CON_MASK = 0x1f << ACLK_VOP_DIV_CON_SHIFT, 243 244 /* CLKSEL_CON49 & CLKSEL_CON50 */ 245 DCLK_VOP_DCLK_SEL_SHIFT = 11, 246 DCLK_VOP_DCLK_SEL_MASK = 1 << DCLK_VOP_DCLK_SEL_SHIFT, 247 DCLK_VOP_DCLK_SEL_DIVOUT = 0, 248 DCLK_VOP_PLL_SEL_SHIFT = 8, 249 DCLK_VOP_PLL_SEL_MASK = 3 << DCLK_VOP_PLL_SEL_SHIFT, 250 DCLK_VOP_PLL_SEL_VPLL = 0, 251 DCLK_VOP_PLL_SEL_CPLL = 1, 252 DCLK_VOP_DIV_CON_MASK = 0xff, 253 DCLK_VOP_DIV_CON_SHIFT = 0, 254 255 /* CLKSEL_CON57 */ 256 PCLK_ALIVE_DIV_CON_SHIFT = 0, 257 PCLK_ALIVE_DIV_CON_MASK = 0x1f << PCLK_ALIVE_DIV_CON_SHIFT, 258 259 /* CLKSEL_CON58 */ 260 CLK_SPI_PLL_SEL_WIDTH = 1, 261 CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1), 262 CLK_SPI_PLL_SEL_CPLL = 0, 263 CLK_SPI_PLL_SEL_GPLL = 1, 264 CLK_SPI_PLL_DIV_CON_WIDTH = 7, 265 CLK_SPI_PLL_DIV_CON_MASK = ((1 << CLK_SPI_PLL_DIV_CON_WIDTH) - 1), 266 267 CLK_SPI5_PLL_DIV_CON_SHIFT = 8, 268 CLK_SPI5_PLL_SEL_SHIFT = 15, 269 270 /* CLKSEL_CON59 */ 271 CLK_SPI1_PLL_SEL_SHIFT = 15, 272 CLK_SPI1_PLL_DIV_CON_SHIFT = 8, 273 CLK_SPI0_PLL_SEL_SHIFT = 7, 274 CLK_SPI0_PLL_DIV_CON_SHIFT = 0, 275 276 /* CLKSEL_CON60 */ 277 CLK_SPI4_PLL_SEL_SHIFT = 15, 278 CLK_SPI4_PLL_DIV_CON_SHIFT = 8, 279 CLK_SPI2_PLL_SEL_SHIFT = 7, 280 CLK_SPI2_PLL_DIV_CON_SHIFT = 0, 281 282 /* CLKSEL_CON61 */ 283 CLK_I2C_PLL_SEL_MASK = 1, 284 CLK_I2C_PLL_SEL_CPLL = 0, 285 CLK_I2C_PLL_SEL_GPLL = 1, 286 CLK_I2C5_PLL_SEL_SHIFT = 15, 287 CLK_I2C5_DIV_CON_SHIFT = 8, 288 CLK_I2C1_PLL_SEL_SHIFT = 7, 289 CLK_I2C1_DIV_CON_SHIFT = 0, 290 291 /* CLKSEL_CON62 */ 292 CLK_I2C6_PLL_SEL_SHIFT = 15, 293 CLK_I2C6_DIV_CON_SHIFT = 8, 294 CLK_I2C2_PLL_SEL_SHIFT = 7, 295 CLK_I2C2_DIV_CON_SHIFT = 0, 296 297 /* CLKSEL_CON63 */ 298 CLK_I2C7_PLL_SEL_SHIFT = 15, 299 CLK_I2C7_DIV_CON_SHIFT = 8, 300 CLK_I2C3_PLL_SEL_SHIFT = 7, 301 CLK_I2C3_DIV_CON_SHIFT = 0, 302 303 /* CRU_SOFTRST_CON4 */ 304 RESETN_DDR0_REQ_SHIFT = 8, 305 RESETN_DDR0_REQ_MASK = 1 << RESETN_DDR0_REQ_SHIFT, 306 RESETN_DDRPHY0_REQ_SHIFT = 9, 307 RESETN_DDRPHY0_REQ_MASK = 1 << RESETN_DDRPHY0_REQ_SHIFT, 308 RESETN_DDR1_REQ_SHIFT = 12, 309 RESETN_DDR1_REQ_MASK = 1 << RESETN_DDR1_REQ_SHIFT, 310 RESETN_DDRPHY1_REQ_SHIFT = 13, 311 RESETN_DDRPHY1_REQ_MASK = 1 << RESETN_DDRPHY1_REQ_SHIFT, 312 }; 313 314 #define VCO_MAX_KHZ (3200 * (MHz / KHz)) 315 #define VCO_MIN_KHZ (800 * (MHz / KHz)) 316 #define OUTPUT_MAX_KHZ (3200 * (MHz / KHz)) 317 #define OUTPUT_MIN_KHZ (16 * (MHz / KHz)) 318 319 /* 320 * the div restructions of pll in integer mode, these are defined in 321 * * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0 322 */ 323 #define PLL_DIV_MIN 16 324 #define PLL_DIV_MAX 3200 325 326 /* 327 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63): 328 * Formulas also embedded within the Fractional PLL Verilog model: 329 * If DSMPD = 1 (DSM is disabled, "integer mode") 330 * FOUTVCO = FREF / REFDIV * FBDIV 331 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2 332 * Where: 333 * FOUTVCO = Fractional PLL non-divided output frequency 334 * FOUTPOSTDIV = Fractional PLL divided output frequency 335 * (output of second post divider) 336 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input) 337 * REFDIV = Fractional PLL input reference clock divider 338 * FBDIV = Integer value programmed into feedback divide 339 * 340 */ 341 342 static uint32_t rkclk_pll_get_rate(u32 *pll_con) 343 { 344 u32 refdiv, fbdiv, postdiv1, postdiv2; 345 u32 con; 346 347 con = readl(&pll_con[3]); 348 switch ((con & PLL_MODE_MASK) >> PLL_MODE_SHIFT) { 349 case PLL_MODE_SLOW: 350 return OSC_HZ; 351 case PLL_MODE_NORM: 352 /* normal mode */ 353 con = readl(&pll_con[0]); 354 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; 355 con = readl(&pll_con[1]); 356 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; 357 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; 358 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; 359 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; 360 case PLL_MODE_DEEP: 361 default: 362 return 32768; 363 } 364 } 365 366 static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div) 367 { 368 /* All 8 PLLs have same VCO and output frequency range restrictions. */ 369 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; 370 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2; 371 372 debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, " 373 "postdiv2=%d, vco=%u khz, output=%u khz\n", 374 pll_con, div->fbdiv, div->refdiv, div->postdiv1, 375 div->postdiv2, vco_khz, output_khz); 376 assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ && 377 output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ && 378 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); 379 380 /* 381 * When power on or changing PLL setting, 382 * we must force PLL into slow mode to ensure output stable clock. 383 */ 384 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK, 385 PLL_MODE_SLOW << PLL_MODE_SHIFT); 386 387 /* use integer mode */ 388 rk_clrsetreg(&pll_con[3], PLL_DSMPD_MASK, 389 PLL_INTEGER_MODE << PLL_DSMPD_SHIFT); 390 391 rk_clrsetreg(&pll_con[0], PLL_FBDIV_MASK, 392 div->fbdiv << PLL_FBDIV_SHIFT); 393 rk_clrsetreg(&pll_con[1], 394 PLL_POSTDIV2_MASK | PLL_POSTDIV1_MASK | 395 PLL_REFDIV_MASK | PLL_REFDIV_SHIFT, 396 (div->postdiv2 << PLL_POSTDIV2_SHIFT) | 397 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | 398 (div->refdiv << PLL_REFDIV_SHIFT)); 399 400 /* waiting for pll lock */ 401 while (!(readl(&pll_con[2]) & (1 << PLL_LOCK_STATUS_SHIFT))) 402 udelay(1); 403 404 /* pll enter normal mode */ 405 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK, 406 PLL_MODE_NORM << PLL_MODE_SHIFT); 407 } 408 409 static ulong rk3399_pll_get_rate(struct rk3399_clk_priv *priv, 410 enum rk3399_pll_id pll_id) 411 { 412 struct rk3399_cru *cru = priv->cru; 413 u32 *pll_con; 414 415 switch (pll_id) { 416 case PLL_APLLL: 417 pll_con = &cru->apll_l_con[0]; 418 break; 419 case PLL_APLLB: 420 pll_con = &cru->apll_b_con[0]; 421 break; 422 case PLL_DPLL: 423 pll_con = &cru->dpll_con[0]; 424 break; 425 case PLL_CPLL: 426 pll_con = &cru->cpll_con[0]; 427 break; 428 case PLL_GPLL: 429 pll_con = &cru->gpll_con[0]; 430 break; 431 case PLL_NPLL: 432 pll_con = &cru->npll_con[0]; 433 break; 434 case PLL_VPLL: 435 pll_con = &cru->vpll_con[0]; 436 break; 437 default: 438 pll_con = &cru->vpll_con[0]; 439 break; 440 } 441 442 return rkclk_pll_get_rate(pll_con); 443 } 444 445 static int pll_para_config(u32 freq_hz, struct pll_div *div) 446 { 447 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; 448 u32 postdiv1, postdiv2 = 1; 449 u32 fref_khz; 450 u32 diff_khz, best_diff_khz; 451 const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16; 452 const u32 max_postdiv1 = 7, max_postdiv2 = 7; 453 u32 vco_khz; 454 u32 freq_khz = freq_hz / KHz; 455 456 if (!freq_hz) { 457 printf("%s: the frequency can't be 0 Hz\n", __func__); 458 return -1; 459 } 460 461 postdiv1 = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz); 462 if (postdiv1 > max_postdiv1) { 463 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); 464 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); 465 } 466 467 vco_khz = freq_khz * postdiv1 * postdiv2; 468 469 if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || 470 postdiv2 > max_postdiv2) { 471 printf("%s: Cannot find out a supported VCO" 472 " for Frequency (%uHz).\n", __func__, freq_hz); 473 return -1; 474 } 475 476 div->postdiv1 = postdiv1; 477 div->postdiv2 = postdiv2; 478 479 best_diff_khz = vco_khz; 480 for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) { 481 fref_khz = ref_khz / refdiv; 482 483 fbdiv = vco_khz / fref_khz; 484 if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv)) 485 continue; 486 diff_khz = vco_khz - fbdiv * fref_khz; 487 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) { 488 fbdiv++; 489 diff_khz = fref_khz - diff_khz; 490 } 491 492 if (diff_khz >= best_diff_khz) 493 continue; 494 495 best_diff_khz = diff_khz; 496 div->refdiv = refdiv; 497 div->fbdiv = fbdiv; 498 } 499 500 if (best_diff_khz > 4 * (MHz/KHz)) { 501 printf("%s: Failed to match output frequency %u, " 502 "difference is %u Hz,exceed 4MHZ\n", __func__, freq_hz, 503 best_diff_khz * KHz); 504 return -1; 505 } 506 return 0; 507 } 508 509 void rk3399_configure_cpu(struct rk3399_cru *cru, 510 enum apll_frequencies freq, 511 enum cpu_cluster cluster) 512 { 513 u32 aclkm_div; 514 u32 pclk_dbg_div; 515 u32 atclk_div, apll_hz; 516 int con_base, parent; 517 u32 *pll_con; 518 519 switch (cluster) { 520 case CPU_CLUSTER_LITTLE: 521 con_base = 0; 522 parent = CLK_CORE_PLL_SEL_ALPLL; 523 pll_con = &cru->apll_l_con[0]; 524 break; 525 case CPU_CLUSTER_BIG: 526 default: 527 con_base = 2; 528 parent = CLK_CORE_PLL_SEL_ABPLL; 529 pll_con = &cru->apll_b_con[0]; 530 break; 531 } 532 533 apll_hz = apll_cfgs[freq]->freq; 534 rkclk_set_pll(pll_con, apll_cfgs[freq]); 535 536 aclkm_div = apll_hz / ACLKM_CORE_HZ - 1; 537 assert((aclkm_div + 1) * ACLKM_CORE_HZ <= apll_hz && 538 aclkm_div < 0x1f); 539 540 pclk_dbg_div = apll_hz / PCLK_DBG_HZ - 1; 541 assert((pclk_dbg_div + 1) * PCLK_DBG_HZ <= apll_hz && 542 pclk_dbg_div < 0x1f); 543 544 atclk_div = apll_hz / ATCLK_CORE_HZ - 1; 545 assert((atclk_div + 1) * ATCLK_CORE_HZ <= apll_hz && 546 atclk_div < 0x1f); 547 548 rk_clrsetreg(&cru->clksel_con[con_base], 549 ACLKM_CORE_DIV_CON_MASK | CLK_CORE_PLL_SEL_MASK | 550 CLK_CORE_DIV_MASK, 551 aclkm_div << ACLKM_CORE_DIV_CON_SHIFT | 552 parent << CLK_CORE_PLL_SEL_SHIFT | 553 0 << CLK_CORE_DIV_SHIFT); 554 555 rk_clrsetreg(&cru->clksel_con[con_base + 1], 556 PCLK_DBG_DIV_MASK | ATCLK_CORE_DIV_MASK, 557 pclk_dbg_div << PCLK_DBG_DIV_SHIFT | 558 atclk_div << ATCLK_CORE_DIV_SHIFT); 559 } 560 #define I2C_CLK_REG_MASK(bus) \ 561 (I2C_DIV_CON_MASK << \ 562 CLK_I2C ##bus## _DIV_CON_SHIFT | \ 563 CLK_I2C_PLL_SEL_MASK << \ 564 CLK_I2C ##bus## _PLL_SEL_SHIFT) 565 566 #define I2C_CLK_REG_VALUE(bus, clk_div) \ 567 ((clk_div - 1) << \ 568 CLK_I2C ##bus## _DIV_CON_SHIFT | \ 569 CLK_I2C_PLL_SEL_GPLL << \ 570 CLK_I2C ##bus## _PLL_SEL_SHIFT) 571 572 #define I2C_CLK_DIV_VALUE(con, bus) \ 573 (con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & \ 574 I2C_DIV_CON_MASK; 575 576 #define I2C_PMUCLK_REG_MASK(bus) \ 577 (I2C_DIV_CON_MASK << \ 578 CLK_I2C ##bus## _DIV_CON_SHIFT) 579 580 #define I2C_PMUCLK_REG_VALUE(bus, clk_div) \ 581 ((clk_div - 1) << \ 582 CLK_I2C ##bus## _DIV_CON_SHIFT) 583 584 static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id) 585 { 586 u32 div, con; 587 588 switch (clk_id) { 589 case SCLK_I2C1: 590 con = readl(&cru->clksel_con[61]); 591 div = I2C_CLK_DIV_VALUE(con, 1); 592 break; 593 case SCLK_I2C2: 594 con = readl(&cru->clksel_con[62]); 595 div = I2C_CLK_DIV_VALUE(con, 2); 596 break; 597 case SCLK_I2C3: 598 con = readl(&cru->clksel_con[63]); 599 div = I2C_CLK_DIV_VALUE(con, 3); 600 break; 601 case SCLK_I2C5: 602 con = readl(&cru->clksel_con[61]); 603 div = I2C_CLK_DIV_VALUE(con, 5); 604 break; 605 case SCLK_I2C6: 606 con = readl(&cru->clksel_con[62]); 607 div = I2C_CLK_DIV_VALUE(con, 6); 608 break; 609 case SCLK_I2C7: 610 con = readl(&cru->clksel_con[63]); 611 div = I2C_CLK_DIV_VALUE(con, 7); 612 break; 613 default: 614 printf("do not support this i2c bus\n"); 615 return -EINVAL; 616 } 617 618 return DIV_TO_RATE(GPLL_HZ, div); 619 } 620 621 static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) 622 { 623 int src_clk_div; 624 625 /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/ 626 src_clk_div = GPLL_HZ / hz; 627 assert(src_clk_div - 1 <= 127); 628 629 switch (clk_id) { 630 case SCLK_I2C1: 631 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(1), 632 I2C_CLK_REG_VALUE(1, src_clk_div)); 633 break; 634 case SCLK_I2C2: 635 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(2), 636 I2C_CLK_REG_VALUE(2, src_clk_div)); 637 break; 638 case SCLK_I2C3: 639 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(3), 640 I2C_CLK_REG_VALUE(3, src_clk_div)); 641 break; 642 case SCLK_I2C5: 643 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(5), 644 I2C_CLK_REG_VALUE(5, src_clk_div)); 645 break; 646 case SCLK_I2C6: 647 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(6), 648 I2C_CLK_REG_VALUE(6, src_clk_div)); 649 break; 650 case SCLK_I2C7: 651 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(7), 652 I2C_CLK_REG_VALUE(7, src_clk_div)); 653 break; 654 default: 655 printf("do not support this i2c bus\n"); 656 return -EINVAL; 657 } 658 659 return rk3399_i2c_get_clk(cru, clk_id); 660 } 661 662 /* 663 * RK3399 SPI clocks have a common divider-width (7 bits) and a single bit 664 * to select either CPLL or GPLL as the clock-parent. The location within 665 * the enclosing CLKSEL_CON (i.e. div_shift and sel_shift) are variable. 666 */ 667 668 struct spi_clkreg { 669 uint8_t reg; /* CLKSEL_CON[reg] register in CRU */ 670 uint8_t div_shift; 671 uint8_t sel_shift; 672 }; 673 674 /* 675 * The entries are numbered relative to their offset from SCLK_SPI0. 676 * 677 * Note that SCLK_SPI3 (which is configured via PMUCRU and requires different 678 * logic is not supported). 679 */ 680 static const struct spi_clkreg spi_clkregs[] = { 681 [0] = { .reg = 59, 682 .div_shift = CLK_SPI0_PLL_DIV_CON_SHIFT, 683 .sel_shift = CLK_SPI0_PLL_SEL_SHIFT, }, 684 [1] = { .reg = 59, 685 .div_shift = CLK_SPI1_PLL_DIV_CON_SHIFT, 686 .sel_shift = CLK_SPI1_PLL_SEL_SHIFT, }, 687 [2] = { .reg = 60, 688 .div_shift = CLK_SPI2_PLL_DIV_CON_SHIFT, 689 .sel_shift = CLK_SPI2_PLL_SEL_SHIFT, }, 690 [3] = { .reg = 60, 691 .div_shift = CLK_SPI4_PLL_DIV_CON_SHIFT, 692 .sel_shift = CLK_SPI4_PLL_SEL_SHIFT, }, 693 [4] = { .reg = 58, 694 .div_shift = CLK_SPI5_PLL_DIV_CON_SHIFT, 695 .sel_shift = CLK_SPI5_PLL_SEL_SHIFT, }, 696 }; 697 698 static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id) 699 { 700 const struct spi_clkreg *spiclk = NULL; 701 u32 div, val; 702 703 switch (clk_id) { 704 case SCLK_SPI0 ... SCLK_SPI5: 705 spiclk = &spi_clkregs[clk_id - SCLK_SPI0]; 706 break; 707 708 default: 709 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id); 710 return -EINVAL; 711 } 712 713 val = readl(&cru->clksel_con[spiclk->reg]); 714 div = bitfield_extract(val, spiclk->div_shift, 715 CLK_SPI_PLL_DIV_CON_WIDTH); 716 717 return DIV_TO_RATE(GPLL_HZ, div); 718 } 719 720 static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) 721 { 722 const struct spi_clkreg *spiclk = NULL; 723 int src_clk_div; 724 725 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; 726 assert(src_clk_div < 128); 727 728 switch (clk_id) { 729 case SCLK_SPI1 ... SCLK_SPI5: 730 spiclk = &spi_clkregs[clk_id - SCLK_SPI0]; 731 break; 732 733 default: 734 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id); 735 return -EINVAL; 736 } 737 738 rk_clrsetreg(&cru->clksel_con[spiclk->reg], 739 ((CLK_SPI_PLL_DIV_CON_MASK << spiclk->div_shift) | 740 (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)), 741 ((src_clk_div << spiclk->div_shift) | 742 (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift))); 743 744 return rk3399_spi_get_clk(cru, clk_id); 745 } 746 747 #define RK3399_LIMIT_PLL_ACLK_VOP (400 * 1000000) 748 749 static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz) 750 { 751 struct pll_div vpll_config = {0}, cpll_config = {0}; 752 int aclk_vop = RK3399_LIMIT_PLL_ACLK_VOP; 753 void *aclkreg_addr, *dclkreg_addr; 754 u32 div = 1; 755 756 switch (clk_id) { 757 case DCLK_VOP0: 758 aclkreg_addr = &cru->clksel_con[47]; 759 dclkreg_addr = &cru->clksel_con[49]; 760 break; 761 case DCLK_VOP1: 762 aclkreg_addr = &cru->clksel_con[48]; 763 dclkreg_addr = &cru->clksel_con[50]; 764 break; 765 default: 766 return -EINVAL; 767 } 768 /* vop aclk source clk: cpll */ 769 div = GPLL_HZ / aclk_vop; 770 assert(div - 1 <= 31); 771 772 rk_clrsetreg(aclkreg_addr, 773 ACLK_VOP_PLL_SEL_MASK | ACLK_VOP_DIV_CON_MASK, 774 ACLK_VOP_PLL_SEL_GPLL << ACLK_VOP_PLL_SEL_SHIFT | 775 (div - 1) << ACLK_VOP_DIV_CON_SHIFT); 776 777 if (readl(dclkreg_addr) & DCLK_VOP_PLL_SEL_MASK) { 778 if (pll_para_config(hz, &cpll_config)) 779 return -1; 780 rkclk_set_pll(&cru->cpll_con[0], &cpll_config); 781 } else { 782 if (pll_para_config(hz, &vpll_config)) 783 return -1; 784 rkclk_set_pll(&cru->vpll_con[0], &vpll_config); 785 } 786 787 rk_clrsetreg(dclkreg_addr, 788 DCLK_VOP_DCLK_SEL_MASK | DCLK_VOP_DIV_CON_MASK, 789 DCLK_VOP_DCLK_SEL_DIVOUT << DCLK_VOP_DCLK_SEL_SHIFT | 790 (1 - 1) << DCLK_VOP_DIV_CON_SHIFT); 791 792 return hz; 793 } 794 795 static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id) 796 { 797 u32 div, con; 798 799 switch (clk_id) { 800 case HCLK_SDMMC: 801 case SCLK_SDMMC: 802 con = readl(&cru->clksel_con[16]); 803 /* dwmmc controller have internal div 2 */ 804 div = 2; 805 break; 806 case SCLK_EMMC: 807 con = readl(&cru->clksel_con[22]); 808 div = 1; 809 break; 810 default: 811 return -EINVAL; 812 } 813 814 div *= (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT; 815 if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT 816 == CLK_EMMC_PLL_SEL_24M) 817 return DIV_TO_RATE(OSC_HZ, div); 818 else 819 return DIV_TO_RATE(GPLL_HZ, div); 820 } 821 822 static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru, 823 ulong clk_id, ulong set_rate) 824 { 825 int src_clk_div; 826 int aclk_emmc = 198*MHz; 827 828 switch (clk_id) { 829 case HCLK_SDMMC: 830 case SCLK_SDMMC: 831 /* Select clk_sdmmc source from GPLL by default */ 832 /* mmc clock defaulg div 2 internal, provide double in cru */ 833 src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate); 834 835 if (src_clk_div > 128) { 836 /* use 24MHz source for 400KHz clock */ 837 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); 838 assert(src_clk_div - 1 < 128); 839 rk_clrsetreg(&cru->clksel_con[16], 840 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, 841 CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT | 842 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); 843 } else { 844 rk_clrsetreg(&cru->clksel_con[16], 845 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, 846 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT | 847 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); 848 } 849 break; 850 case SCLK_EMMC: 851 /* Select aclk_emmc source from GPLL */ 852 src_clk_div = DIV_ROUND_UP(GPLL_HZ , aclk_emmc); 853 assert(src_clk_div - 1 < 32); 854 855 rk_clrsetreg(&cru->clksel_con[21], 856 ACLK_EMMC_PLL_SEL_MASK | ACLK_EMMC_DIV_CON_MASK, 857 ACLK_EMMC_PLL_SEL_GPLL << ACLK_EMMC_PLL_SEL_SHIFT | 858 (src_clk_div - 1) << ACLK_EMMC_DIV_CON_SHIFT); 859 860 /* Select clk_emmc source from GPLL too */ 861 src_clk_div = DIV_ROUND_UP(GPLL_HZ, set_rate); 862 if (src_clk_div > 128) { 863 /* use 24MHz source for 400KHz clock */ 864 src_clk_div = DIV_ROUND_UP(OSC_HZ, set_rate); 865 assert(src_clk_div - 1 < 128); 866 rk_clrsetreg(&cru->clksel_con[22], 867 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, 868 CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT | 869 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); 870 } else { 871 rk_clrsetreg(&cru->clksel_con[22], 872 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, 873 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT | 874 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); 875 } 876 break; 877 default: 878 return -EINVAL; 879 } 880 return rk3399_mmc_get_clk(cru, clk_id); 881 } 882 883 static ulong rk3399_gmac_set_clk(struct rk3399_cru *cru, ulong rate) 884 { 885 ulong ret; 886 887 /* 888 * The RGMII CLK can be derived either from an external "clkin" 889 * or can be generated from internally by a divider from SCLK_MAC. 890 */ 891 if (readl(&cru->clksel_con[19]) & BIT(4)) { 892 /* An external clock will always generate the right rate... */ 893 ret = rate; 894 } else { 895 /* 896 * No platform uses an internal clock to date. 897 * Implement this once it becomes necessary and print an error 898 * if someone tries to use it (while it remains unimplemented). 899 */ 900 pr_err("%s: internal clock is UNIMPLEMENTED\n", __func__); 901 ret = 0; 902 } 903 904 return ret; 905 } 906 907 #define PMUSGRF_DDR_RGN_CON16 0xff330040 908 static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru, 909 ulong set_rate) 910 { 911 struct pll_div dpll_cfg; 912 913 /* IC ECO bug, need to set this register */ 914 writel(0xc000c000, PMUSGRF_DDR_RGN_CON16); 915 916 /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */ 917 switch (set_rate) { 918 case 50 * MHz: 919 dpll_cfg = (struct pll_div) 920 {.refdiv = 1, .fbdiv = 12, .postdiv1 = 3, .postdiv2 = 2}; 921 break; 922 case 200 * MHz: 923 dpll_cfg = (struct pll_div) 924 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1}; 925 break; 926 case 300 * MHz: 927 dpll_cfg = (struct pll_div) 928 {.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1}; 929 break; 930 case 400 * MHz: 931 dpll_cfg = (struct pll_div) 932 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1}; 933 break; 934 case 666 * MHz: 935 dpll_cfg = (struct pll_div) 936 {.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1}; 937 break; 938 case 800 * MHz: 939 dpll_cfg = (struct pll_div) 940 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}; 941 break; 942 case 933 * MHz: 943 dpll_cfg = (struct pll_div) 944 {.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1}; 945 break; 946 default: 947 pr_err("Unsupported SDRAM frequency!,%ld\n", set_rate); 948 } 949 rkclk_set_pll(&cru->dpll_con[0], &dpll_cfg); 950 951 return set_rate; 952 } 953 954 static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru) 955 { 956 u32 div, val; 957 958 val = readl(&cru->clksel_con[26]); 959 div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT, 960 CLK_SARADC_DIV_CON_WIDTH); 961 962 return DIV_TO_RATE(OSC_HZ, div); 963 } 964 965 static ulong rk3399_saradc_set_clk(struct rk3399_cru *cru, uint hz) 966 { 967 int src_clk_div; 968 969 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; 970 assert(src_clk_div <= 255); 971 972 rk_clrsetreg(&cru->clksel_con[26], 973 CLK_SARADC_DIV_CON_MASK, 974 src_clk_div << CLK_SARADC_DIV_CON_SHIFT); 975 976 return rk3399_saradc_get_clk(cru); 977 } 978 979 static ulong rk3399_tsadc_get_clk(struct rk3399_cru *cru) 980 { 981 u32 div, val; 982 983 val = readl(&cru->clksel_con[27]); 984 div = bitfield_extract(val, CLK_TSADC_SEL_SHIFT, 985 10); 986 987 return DIV_TO_RATE(OSC_HZ, div); 988 } 989 990 static ulong rk3399_tsadc_set_clk(struct rk3399_cru *cru, uint hz) 991 { 992 int src_clk_div; 993 994 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; 995 assert(src_clk_div <= 255); 996 997 rk_clrsetreg(&cru->clksel_con[27], 998 CLK_TSADC_DIV_CON_MASK | CLK_TSADC_SEL_MASK, 999 (CLK_TSADC_SEL_X24M << CLK_TSADC_SEL_SHIFT) | 1000 (src_clk_div << CLK_TSADC_DIV_CON_SHIFT)); 1001 1002 return rk3399_tsadc_get_clk(cru); 1003 } 1004 1005 static ulong rk3399_crypto_get_clk(struct rk3399_clk_priv *priv, ulong clk_id) 1006 { 1007 struct rk3399_cru *cru = priv->cru; 1008 u32 div, con, parent; 1009 1010 switch (clk_id) { 1011 case SCLK_CRYPTO0: 1012 con = readl(&cru->clksel_con[24]); 1013 div = (con & CRYPTO0_DIV_MASK) >> CRYPTO0_DIV_SHIFT; 1014 parent = GPLL_HZ; 1015 break; 1016 case SCLK_CRYPTO1: 1017 con = readl(&cru->clksel_con[26]); 1018 div = (con & CRYPTO1_DIV_MASK) >> CRYPTO1_DIV_SHIFT; 1019 parent = GPLL_HZ; 1020 break; 1021 default: 1022 return -ENOENT; 1023 } 1024 1025 return DIV_TO_RATE(parent, div); 1026 } 1027 1028 static ulong rk3399_crypto_set_clk(struct rk3399_clk_priv *priv, ulong clk_id, 1029 ulong hz) 1030 { 1031 struct rk3399_cru *cru = priv->cru; 1032 int src_clk_div; 1033 1034 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz); 1035 assert(src_clk_div - 1 <= 31); 1036 1037 /* 1038 * select gpll as crypto clock source and 1039 * set up dependent divisors for crypto clocks. 1040 */ 1041 switch (clk_id) { 1042 case SCLK_CRYPTO0: 1043 rk_clrsetreg(&cru->clksel_con[24], 1044 CRYPTO0_PLL_SEL_MASK | CRYPTO0_DIV_MASK, 1045 CRYPTO_PLL_SEL_GPLL << CRYPTO0_PLL_SEL_SHIFT | 1046 (src_clk_div - 1) << CRYPTO0_DIV_SHIFT); 1047 break; 1048 case SCLK_CRYPTO1: 1049 rk_clrsetreg(&cru->clksel_con[26], 1050 CRYPTO1_PLL_SEL_MASK | CRYPTO1_DIV_MASK, 1051 CRYPTO_PLL_SEL_GPLL << CRYPTO1_PLL_SEL_SHIFT | 1052 (src_clk_div - 1) << CRYPTO1_DIV_SHIFT); 1053 break; 1054 default: 1055 printf("do not support this peri freq\n"); 1056 return -EINVAL; 1057 } 1058 1059 return rk3399_crypto_get_clk(priv, clk_id); 1060 } 1061 1062 #ifndef CONFIG_SPL_BUILD 1063 static ulong rk3399_peri_get_clk(struct rk3399_clk_priv *priv, ulong clk_id) 1064 { 1065 struct rk3399_cru *cru = priv->cru; 1066 u32 div, con, parent; 1067 1068 switch (clk_id) { 1069 case ACLK_PERIHP: 1070 con = readl(&cru->clksel_con[14]); 1071 div = (con & ACLK_PERIHP_DIV_CON_MASK) >> 1072 ACLK_PERIHP_DIV_CON_SHIFT; 1073 parent = GPLL_HZ; 1074 break; 1075 case PCLK_PERIHP: 1076 con = readl(&cru->clksel_con[14]); 1077 div = (con & PCLK_PERIHP_DIV_CON_MASK) >> 1078 PCLK_PERIHP_DIV_CON_SHIFT; 1079 parent = rk3399_peri_get_clk(priv, ACLK_PERIHP); 1080 break; 1081 case HCLK_PERIHP: 1082 con = readl(&cru->clksel_con[14]); 1083 div = (con & HCLK_PERIHP_DIV_CON_MASK) >> 1084 HCLK_PERIHP_DIV_CON_SHIFT; 1085 parent = rk3399_peri_get_clk(priv, ACLK_PERIHP); 1086 break; 1087 case ACLK_PERILP0: 1088 con = readl(&cru->clksel_con[23]); 1089 div = (con & ACLK_PERILP0_DIV_CON_MASK) >> 1090 ACLK_PERILP0_DIV_CON_SHIFT; 1091 parent = GPLL_HZ; 1092 break; 1093 case HCLK_PERILP0: 1094 con = readl(&cru->clksel_con[23]); 1095 div = (con & HCLK_PERILP0_DIV_CON_MASK) >> 1096 HCLK_PERILP0_DIV_CON_SHIFT; 1097 parent = rk3399_peri_get_clk(priv, ACLK_PERILP0); 1098 break; 1099 case PCLK_PERILP0: 1100 con = readl(&cru->clksel_con[23]); 1101 div = (con & PCLK_PERILP0_DIV_CON_MASK) >> 1102 PCLK_PERILP0_DIV_CON_SHIFT; 1103 parent = rk3399_peri_get_clk(priv, ACLK_PERILP0); 1104 break; 1105 case HCLK_PERILP1: 1106 con = readl(&cru->clksel_con[25]); 1107 div = (con & HCLK_PERILP1_DIV_CON_MASK) >> 1108 HCLK_PERILP1_DIV_CON_SHIFT; 1109 parent = GPLL_HZ; 1110 break; 1111 case PCLK_PERILP1: 1112 con = readl(&cru->clksel_con[25]); 1113 div = (con & PCLK_PERILP1_DIV_CON_MASK) >> 1114 PCLK_PERILP1_DIV_CON_SHIFT; 1115 parent = rk3399_peri_get_clk(priv, HCLK_PERILP1); 1116 break; 1117 default: 1118 return -ENOENT; 1119 } 1120 1121 return DIV_TO_RATE(parent, div); 1122 } 1123 1124 static ulong rk3399_alive_get_clk(struct rk3399_clk_priv *priv) 1125 { 1126 struct rk3399_cru *cru = priv->cru; 1127 u32 div, con, parent; 1128 1129 con = readl(&cru->clksel_con[57]); 1130 div = (con & PCLK_ALIVE_DIV_CON_MASK) >> 1131 PCLK_ALIVE_DIV_CON_SHIFT; 1132 parent = GPLL_HZ; 1133 return DIV_TO_RATE(parent, div); 1134 } 1135 #endif 1136 1137 static ulong rk3399_clk_get_rate(struct clk *clk) 1138 { 1139 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); 1140 ulong rate = 0; 1141 1142 switch (clk->id) { 1143 case PLL_APLLL: 1144 case PLL_APLLB: 1145 case PLL_DPLL: 1146 case PLL_CPLL: 1147 case PLL_GPLL: 1148 case PLL_NPLL: 1149 case PLL_VPLL: 1150 rate = rk3399_pll_get_rate(priv, clk->id); 1151 break; 1152 case HCLK_SDMMC: 1153 case SCLK_SDMMC: 1154 case SCLK_EMMC: 1155 rate = rk3399_mmc_get_clk(priv->cru, clk->id); 1156 break; 1157 case SCLK_I2C1: 1158 case SCLK_I2C2: 1159 case SCLK_I2C3: 1160 case SCLK_I2C5: 1161 case SCLK_I2C6: 1162 case SCLK_I2C7: 1163 rate = rk3399_i2c_get_clk(priv->cru, clk->id); 1164 break; 1165 case SCLK_SPI0...SCLK_SPI5: 1166 rate = rk3399_spi_get_clk(priv->cru, clk->id); 1167 break; 1168 case SCLK_UART0: 1169 case SCLK_UART1: 1170 case SCLK_UART2: 1171 case SCLK_UART3: 1172 return 24000000; 1173 break; 1174 case PCLK_HDMI_CTRL: 1175 break; 1176 case DCLK_VOP0: 1177 case DCLK_VOP1: 1178 break; 1179 case PCLK_EFUSE1024NS: 1180 break; 1181 case SCLK_SARADC: 1182 rate = rk3399_saradc_get_clk(priv->cru); 1183 break; 1184 case SCLK_TSADC: 1185 rate = rk3399_tsadc_get_clk(priv->cru); 1186 break; 1187 case SCLK_CRYPTO0: 1188 case SCLK_CRYPTO1: 1189 rate = rk3399_crypto_get_clk(priv, clk->id); 1190 break; 1191 #ifndef CONFIG_SPL_BUILD 1192 case ACLK_PERIHP: 1193 case HCLK_PERIHP: 1194 case PCLK_PERIHP: 1195 case ACLK_PERILP0: 1196 case HCLK_PERILP0: 1197 case PCLK_PERILP0: 1198 case HCLK_PERILP1: 1199 case PCLK_PERILP1: 1200 rate = rk3399_peri_get_clk(priv, clk->id); 1201 break; 1202 case PCLK_ALIVE: 1203 case PCLK_WDT: 1204 rate = rk3399_alive_get_clk(priv); 1205 break; 1206 #endif 1207 default: 1208 return -ENOENT; 1209 } 1210 1211 return rate; 1212 } 1213 1214 static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) 1215 { 1216 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); 1217 ulong ret = 0; 1218 1219 switch (clk->id) { 1220 case 0 ... 63: 1221 return 0; 1222 1223 case ACLK_PERIHP: 1224 case HCLK_PERIHP: 1225 case PCLK_PERIHP: 1226 return 0; 1227 1228 case ACLK_PERILP0: 1229 case HCLK_PERILP0: 1230 case PCLK_PERILP0: 1231 return 0; 1232 1233 case ACLK_CCI: 1234 return 0; 1235 1236 case HCLK_PERILP1: 1237 case PCLK_PERILP1: 1238 return 0; 1239 1240 case HCLK_SDMMC: 1241 case SCLK_SDMMC: 1242 case SCLK_EMMC: 1243 ret = rk3399_mmc_set_clk(priv->cru, clk->id, rate); 1244 break; 1245 case SCLK_MAC: 1246 ret = rk3399_gmac_set_clk(priv->cru, rate); 1247 break; 1248 case SCLK_I2C1: 1249 case SCLK_I2C2: 1250 case SCLK_I2C3: 1251 case SCLK_I2C5: 1252 case SCLK_I2C6: 1253 case SCLK_I2C7: 1254 ret = rk3399_i2c_set_clk(priv->cru, clk->id, rate); 1255 break; 1256 case SCLK_SPI0...SCLK_SPI5: 1257 ret = rk3399_spi_set_clk(priv->cru, clk->id, rate); 1258 break; 1259 case PCLK_HDMI_CTRL: 1260 case PCLK_VIO_GRF: 1261 /* the PCLK gates for video are enabled by default */ 1262 break; 1263 case DCLK_VOP0: 1264 case DCLK_VOP1: 1265 ret = rk3399_vop_set_clk(priv->cru, clk->id, rate); 1266 break; 1267 case SCLK_DDRCLK: 1268 ret = rk3399_ddr_set_clk(priv->cru, rate); 1269 break; 1270 case PCLK_EFUSE1024NS: 1271 break; 1272 case SCLK_SARADC: 1273 ret = rk3399_saradc_set_clk(priv->cru, rate); 1274 break; 1275 case SCLK_TSADC: 1276 ret = rk3399_tsadc_set_clk(priv->cru, rate); 1277 break; 1278 case SCLK_CRYPTO0: 1279 case SCLK_CRYPTO1: 1280 ret = rk3399_crypto_set_clk(priv, clk->id, rate); 1281 break; 1282 default: 1283 return -ENOENT; 1284 } 1285 1286 return ret; 1287 } 1288 1289 static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk, struct clk *parent) 1290 { 1291 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); 1292 const char *clock_output_name; 1293 int ret; 1294 1295 /* 1296 * If the requested parent is in the same clock-controller and 1297 * the id is SCLK_MAC ("clk_gmac"), switch to the internal clock. 1298 */ 1299 if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC)) { 1300 debug("%s: switching RGMII to SCLK_MAC\n", __func__); 1301 rk_clrreg(&priv->cru->clksel_con[19], BIT(4)); 1302 return 0; 1303 } 1304 1305 /* 1306 * Otherwise, we need to check the clock-output-names of the 1307 * requested parent to see if the requested id is "clkin_gmac". 1308 */ 1309 ret = dev_read_string_index(parent->dev, "clock-output-names", 1310 parent->id, &clock_output_name); 1311 if (ret < 0) 1312 return -ENODATA; 1313 1314 /* If this is "clkin_gmac", switch to the external clock input */ 1315 if (!strcmp(clock_output_name, "clkin_gmac")) { 1316 debug("%s: switching RGMII to CLKIN\n", __func__); 1317 rk_setreg(&priv->cru->clksel_con[19], BIT(4)); 1318 return 0; 1319 } 1320 1321 return -EINVAL; 1322 } 1323 1324 static int __maybe_unused rk3399_dclk_vop_set_parent(struct clk *clk, 1325 struct clk *parent) 1326 { 1327 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); 1328 void *dclkreg_addr; 1329 1330 switch (clk->id) { 1331 case DCLK_VOP0_DIV: 1332 dclkreg_addr = &priv->cru->clksel_con[49]; 1333 break; 1334 case DCLK_VOP1_DIV: 1335 dclkreg_addr = &priv->cru->clksel_con[50]; 1336 break; 1337 default: 1338 return -EINVAL; 1339 } 1340 if (parent->id == PLL_CPLL) { 1341 rk_clrsetreg(dclkreg_addr, DCLK_VOP_PLL_SEL_MASK, 1342 DCLK_VOP_PLL_SEL_CPLL << DCLK_VOP_PLL_SEL_SHIFT); 1343 } else { 1344 rk_clrsetreg(dclkreg_addr, DCLK_VOP_PLL_SEL_MASK, 1345 DCLK_VOP_PLL_SEL_VPLL << DCLK_VOP_PLL_SEL_SHIFT); 1346 } 1347 1348 return 0; 1349 } 1350 1351 static int __maybe_unused rk3399_clk_set_parent(struct clk *clk, struct clk *parent) 1352 { 1353 switch (clk->id) { 1354 case SCLK_RMII_SRC: 1355 return rk3399_gmac_set_parent(clk, parent); 1356 case DCLK_VOP0_DIV: 1357 case DCLK_VOP1_DIV: 1358 return rk3399_dclk_vop_set_parent(clk, parent); 1359 } 1360 1361 debug("%s: unsupported clk %ld\n", __func__, clk->id); 1362 return -ENOENT; 1363 } 1364 1365 static int rk3399_clk_enable(struct clk *clk) 1366 { 1367 switch (clk->id) { 1368 case HCLK_HOST0: 1369 case HCLK_HOST0_ARB: 1370 case SCLK_USBPHY0_480M_SRC: 1371 case HCLK_HOST1: 1372 case HCLK_HOST1_ARB: 1373 case SCLK_USBPHY1_480M_SRC: 1374 case ACLK_USB3OTG1: 1375 case ACLK_USB3_GRF: 1376 case SCLK_USB3OTG1_REF: 1377 case SCLK_USB3OTG1_SUSPEND: 1378 return 0; 1379 } 1380 1381 debug("%s: unsupported clk %ld\n", __func__, clk->id); 1382 return -ENOENT; 1383 } 1384 1385 static struct clk_ops rk3399_clk_ops = { 1386 .get_rate = rk3399_clk_get_rate, 1387 .set_rate = rk3399_clk_set_rate, 1388 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 1389 .set_parent = rk3399_clk_set_parent, 1390 #endif 1391 .enable = rk3399_clk_enable, 1392 }; 1393 1394 static void rkclk_init(struct rk3399_cru *cru) 1395 { 1396 u32 aclk_div; 1397 u32 hclk_div; 1398 u32 pclk_div; 1399 1400 rk3399_configure_cpu(cru, APLL_816_MHZ, CPU_CLUSTER_LITTLE); 1401 rk3399_configure_cpu(cru, APLL_816_MHZ, CPU_CLUSTER_BIG); 1402 1403 /* 1404 * some cru registers changed by bootrom, we'd better reset them to 1405 * reset/default values described in TRM to avoid confusion in kernel. 1406 * Please consider these three lines as a fix of bootrom bug. 1407 */ 1408 if (rkclk_pll_get_rate(&cru->npll_con[0]) != NPLL_HZ) 1409 rkclk_set_pll(&cru->npll_con[0], &npll_init_cfg); 1410 1411 if (rkclk_pll_get_rate(&cru->gpll_con[0]) == GPLL_HZ) 1412 return; 1413 1414 rk_clrsetreg(&cru->clksel_con[12], 0xffff, 0x4101); 1415 rk_clrsetreg(&cru->clksel_con[19], 0xffff, 0x033f); 1416 rk_clrsetreg(&cru->clksel_con[56], 0x0003, 0x0003); 1417 1418 /* configure perihp aclk, hclk, pclk */ 1419 aclk_div = DIV_ROUND_UP(GPLL_HZ, PERIHP_ACLK_HZ) - 1; 1420 1421 hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1; 1422 assert((hclk_div + 1) * PERIHP_HCLK_HZ <= 1423 PERIHP_ACLK_HZ && (hclk_div <= 0x3)); 1424 1425 pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1; 1426 assert((pclk_div + 1) * PERIHP_PCLK_HZ <= 1427 PERIHP_ACLK_HZ && (pclk_div <= 0x7)); 1428 1429 rk_clrsetreg(&cru->clksel_con[14], 1430 PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK | 1431 ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK, 1432 pclk_div << PCLK_PERIHP_DIV_CON_SHIFT | 1433 hclk_div << HCLK_PERIHP_DIV_CON_SHIFT | 1434 ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT | 1435 aclk_div << ACLK_PERIHP_DIV_CON_SHIFT); 1436 1437 /* configure perilp0 aclk, hclk, pclk */ 1438 aclk_div = DIV_ROUND_UP(GPLL_HZ, PERILP0_ACLK_HZ) - 1; 1439 1440 hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1; 1441 assert((hclk_div + 1) * PERILP0_HCLK_HZ <= 1442 PERILP0_ACLK_HZ && (hclk_div <= 0x3)); 1443 1444 pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1; 1445 assert((pclk_div + 1) * PERILP0_PCLK_HZ <= 1446 PERILP0_ACLK_HZ && (pclk_div <= 0x7)); 1447 1448 rk_clrsetreg(&cru->clksel_con[23], 1449 PCLK_PERILP0_DIV_CON_MASK | HCLK_PERILP0_DIV_CON_MASK | 1450 ACLK_PERILP0_PLL_SEL_MASK | ACLK_PERILP0_DIV_CON_MASK, 1451 pclk_div << PCLK_PERILP0_DIV_CON_SHIFT | 1452 hclk_div << HCLK_PERILP0_DIV_CON_SHIFT | 1453 ACLK_PERILP0_PLL_SEL_GPLL << ACLK_PERILP0_PLL_SEL_SHIFT | 1454 aclk_div << ACLK_PERILP0_DIV_CON_SHIFT); 1455 1456 /* perilp1 hclk select gpll as source */ 1457 hclk_div = DIV_ROUND_UP(GPLL_HZ, PERILP1_HCLK_HZ) - 1; 1458 assert((hclk_div + 1) * PERILP1_HCLK_HZ <= 1459 GPLL_HZ && (hclk_div <= 0x1f)); 1460 1461 pclk_div = PERILP1_HCLK_HZ / PERILP1_PCLK_HZ - 1; 1462 assert((pclk_div + 1) * PERILP1_PCLK_HZ <= 1463 PERILP1_HCLK_HZ && (pclk_div <= 0x7)); 1464 1465 rk_clrsetreg(&cru->clksel_con[25], 1466 PCLK_PERILP1_DIV_CON_MASK | HCLK_PERILP1_DIV_CON_MASK | 1467 HCLK_PERILP1_PLL_SEL_MASK, 1468 pclk_div << PCLK_PERILP1_DIV_CON_SHIFT | 1469 hclk_div << HCLK_PERILP1_DIV_CON_SHIFT | 1470 HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT); 1471 1472 rk_clrsetreg(&cru->clksel_con[21], 1473 ACLK_EMMC_PLL_SEL_MASK | ACLK_EMMC_DIV_CON_MASK, 1474 ACLK_EMMC_PLL_SEL_GPLL << ACLK_EMMC_PLL_SEL_SHIFT | 1475 (4 - 1) << ACLK_EMMC_DIV_CON_SHIFT); 1476 rk_clrsetreg(&cru->clksel_con[22], 0x3f << 0, 7 << 0); 1477 1478 /* 1479 * I2c MUx is in cpll by default, but cpll is for dclk_vop exclusive. 1480 * If dclk_vop set rate after i2c init, the CPLL changed, 1481 * but the i2c not perception, it will resulting the wrong 1482 * frequency of the i2c. 1483 * So set the i2c frequency according to the kernel configuration, 1484 * and Hang I2C on the GPLL. 1485 */ 1486 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(1), 1487 I2C_CLK_REG_VALUE(1, 4)); 1488 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(2), 1489 I2C_CLK_REG_VALUE(2, 4)); 1490 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(3), 1491 I2C_CLK_REG_VALUE(3, 4)); 1492 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(5), 1493 I2C_CLK_REG_VALUE(5, 4)); 1494 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(6), 1495 I2C_CLK_REG_VALUE(6, 4)); 1496 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(7), 1497 I2C_CLK_REG_VALUE(7, 4)); 1498 1499 rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg); 1500 } 1501 1502 static int rk3399_clk_probe(struct udevice *dev) 1503 { 1504 struct rk3399_clk_priv *priv = dev_get_priv(dev); 1505 1506 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1507 struct rk3399_clk_plat *plat = dev_get_platdata(dev); 1508 1509 priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); 1510 #endif 1511 1512 priv->sync_kernel = false; 1513 if (!priv->armlclk_enter_hz) 1514 priv->armlclk_enter_hz = 1515 rkclk_pll_get_rate(&priv->cru->apll_l_con[0]); 1516 if (!priv->armbclk_enter_hz) 1517 priv->armbclk_enter_hz = 1518 rkclk_pll_get_rate(&priv->cru->apll_b_con[0]); 1519 rkclk_init(priv->cru); 1520 if (!priv->armlclk_init_hz) 1521 priv->armlclk_init_hz = 1522 rkclk_pll_get_rate(&priv->cru->apll_l_con[0]); 1523 if (!priv->armbclk_init_hz) 1524 priv->armbclk_init_hz = 1525 rkclk_pll_get_rate(&priv->cru->apll_b_con[0]); 1526 1527 return 0; 1528 } 1529 1530 static int rk3399_clk_ofdata_to_platdata(struct udevice *dev) 1531 { 1532 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 1533 struct rk3399_clk_priv *priv = dev_get_priv(dev); 1534 1535 priv->cru = dev_read_addr_ptr(dev); 1536 #endif 1537 return 0; 1538 } 1539 1540 static int rk3399_clk_bind(struct udevice *dev) 1541 { 1542 int ret; 1543 struct udevice *sys_child, *sf_child; 1544 struct sysreset_reg *priv; 1545 struct softreset_reg *sf_priv; 1546 1547 /* The reset driver does not have a device node, so bind it here */ 1548 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", 1549 &sys_child); 1550 if (ret) { 1551 debug("Warning: No sysreset driver: ret=%d\n", ret); 1552 } else { 1553 priv = malloc(sizeof(struct sysreset_reg)); 1554 priv->glb_srst_fst_value = offsetof(struct rk3399_cru, 1555 glb_srst_fst_value); 1556 priv->glb_srst_snd_value = offsetof(struct rk3399_cru, 1557 glb_srst_snd_value); 1558 sys_child->priv = priv; 1559 } 1560 1561 ret = device_bind_driver_to_node(dev, "rockchip_reset", "reset", 1562 dev_ofnode(dev), &sf_child); 1563 if (ret) { 1564 debug("Warning: No rockchip reset driver: ret=%d\n", ret); 1565 } else { 1566 sf_priv = malloc(sizeof(struct softreset_reg)); 1567 sf_priv->sf_reset_offset = offsetof(struct rk3399_cru, 1568 softrst_con[0]); 1569 sf_priv->sf_reset_num = 21; 1570 sf_child->priv = sf_priv; 1571 } 1572 1573 return 0; 1574 } 1575 1576 static const struct udevice_id rk3399_clk_ids[] = { 1577 { .compatible = "rockchip,rk3399-cru" }, 1578 { } 1579 }; 1580 1581 U_BOOT_DRIVER(clk_rk3399) = { 1582 .name = "rockchip_rk3399_cru", 1583 .id = UCLASS_CLK, 1584 .of_match = rk3399_clk_ids, 1585 .priv_auto_alloc_size = sizeof(struct rk3399_clk_priv), 1586 .ofdata_to_platdata = rk3399_clk_ofdata_to_platdata, 1587 .ops = &rk3399_clk_ops, 1588 .bind = rk3399_clk_bind, 1589 .probe = rk3399_clk_probe, 1590 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1591 .platdata_auto_alloc_size = sizeof(struct rk3399_clk_plat), 1592 #endif 1593 }; 1594 1595 static ulong rk3399_i2c_get_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id) 1596 { 1597 u32 div, con; 1598 1599 switch (clk_id) { 1600 case SCLK_I2C0_PMU: 1601 con = readl(&pmucru->pmucru_clksel[2]); 1602 div = I2C_CLK_DIV_VALUE(con, 0); 1603 break; 1604 case SCLK_I2C4_PMU: 1605 con = readl(&pmucru->pmucru_clksel[3]); 1606 div = I2C_CLK_DIV_VALUE(con, 4); 1607 break; 1608 case SCLK_I2C8_PMU: 1609 con = readl(&pmucru->pmucru_clksel[2]); 1610 div = I2C_CLK_DIV_VALUE(con, 8); 1611 break; 1612 default: 1613 printf("do not support this i2c bus\n"); 1614 return -EINVAL; 1615 } 1616 1617 return DIV_TO_RATE(PPLL_HZ, div); 1618 } 1619 1620 static ulong rk3399_i2c_set_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id, 1621 uint hz) 1622 { 1623 int src_clk_div; 1624 1625 src_clk_div = PPLL_HZ / hz; 1626 assert(src_clk_div - 1 < 127); 1627 1628 switch (clk_id) { 1629 case SCLK_I2C0_PMU: 1630 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(0), 1631 I2C_PMUCLK_REG_VALUE(0, src_clk_div)); 1632 break; 1633 case SCLK_I2C4_PMU: 1634 rk_clrsetreg(&pmucru->pmucru_clksel[3], I2C_PMUCLK_REG_MASK(4), 1635 I2C_PMUCLK_REG_VALUE(4, src_clk_div)); 1636 break; 1637 case SCLK_I2C8_PMU: 1638 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(8), 1639 I2C_PMUCLK_REG_VALUE(8, src_clk_div)); 1640 break; 1641 default: 1642 printf("do not support this i2c bus\n"); 1643 return -EINVAL; 1644 } 1645 1646 return DIV_TO_RATE(PPLL_HZ, src_clk_div); 1647 } 1648 1649 static ulong rk3399_pwm_get_clk(struct rk3399_pmucru *pmucru) 1650 { 1651 u32 div, con; 1652 1653 /* PWM closk rate is same as pclk_pmu */ 1654 con = readl(&pmucru->pmucru_clksel[0]); 1655 div = con & PMU_PCLK_DIV_CON_MASK; 1656 1657 return DIV_TO_RATE(PPLL_HZ, div); 1658 } 1659 1660 static ulong rk3399_pmuclk_get_rate(struct clk *clk) 1661 { 1662 struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev); 1663 ulong rate = 0; 1664 1665 switch (clk->id) { 1666 case PCLK_RKPWM_PMU: 1667 case PCLK_WDT_M0_PMU: 1668 rate = rk3399_pwm_get_clk(priv->pmucru); 1669 break; 1670 case SCLK_I2C0_PMU: 1671 case SCLK_I2C4_PMU: 1672 case SCLK_I2C8_PMU: 1673 rate = rk3399_i2c_get_pmuclk(priv->pmucru, clk->id); 1674 break; 1675 case SCLK_UART4_PMU: 1676 rate = 24000000; 1677 break; 1678 default: 1679 return -ENOENT; 1680 } 1681 1682 return rate; 1683 } 1684 1685 static ulong rk3399_pmuclk_set_rate(struct clk *clk, ulong rate) 1686 { 1687 struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev); 1688 ulong ret = 0; 1689 1690 switch (clk->id) { 1691 case SCLK_I2C0_PMU: 1692 case SCLK_I2C4_PMU: 1693 case SCLK_I2C8_PMU: 1694 ret = rk3399_i2c_set_pmuclk(priv->pmucru, clk->id, rate); 1695 break; 1696 default: 1697 return -ENOENT; 1698 } 1699 1700 return ret; 1701 } 1702 1703 static struct clk_ops rk3399_pmuclk_ops = { 1704 .get_rate = rk3399_pmuclk_get_rate, 1705 .set_rate = rk3399_pmuclk_set_rate, 1706 }; 1707 1708 #ifndef CONFIG_SPL_BUILD 1709 static void pmuclk_init(struct rk3399_pmucru *pmucru) 1710 { 1711 u32 pclk_div; 1712 1713 /* configure pmu pll(ppll) */ 1714 rkclk_set_pll(&pmucru->ppll_con[0], &ppll_init_cfg); 1715 1716 /* configure pmu pclk */ 1717 pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1; 1718 rk_clrsetreg(&pmucru->pmucru_clksel[0], 1719 PMU_PCLK_DIV_CON_MASK, 1720 pclk_div << PMU_PCLK_DIV_CON_SHIFT); 1721 } 1722 #endif 1723 1724 static int rk3399_pmuclk_probe(struct udevice *dev) 1725 { 1726 #if CONFIG_IS_ENABLED(OF_PLATDATA) || !defined(CONFIG_SPL_BUILD) 1727 struct rk3399_pmuclk_priv *priv = dev_get_priv(dev); 1728 #endif 1729 1730 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1731 struct rk3399_pmuclk_plat *plat = dev_get_platdata(dev); 1732 1733 priv->pmucru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); 1734 #endif 1735 1736 #ifndef CONFIG_SPL_BUILD 1737 pmuclk_init(priv->pmucru); 1738 #endif 1739 return 0; 1740 } 1741 1742 static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev) 1743 { 1744 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 1745 struct rk3399_pmuclk_priv *priv = dev_get_priv(dev); 1746 1747 priv->pmucru = dev_read_addr_ptr(dev); 1748 #endif 1749 return 0; 1750 } 1751 1752 static int rk3399_pmuclk_bind(struct udevice *dev) 1753 { 1754 int ret = 0; 1755 struct udevice *sf_child; 1756 struct softreset_reg *sf_priv; 1757 1758 ret = device_bind_driver_to_node(dev, "rockchip_reset", 1759 "reset", dev_ofnode(dev), 1760 &sf_child); 1761 if (ret) { 1762 debug("Warning: No rockchip reset driver: ret=%d\n", ret); 1763 } else { 1764 sf_priv = malloc(sizeof(struct softreset_reg)); 1765 sf_priv->sf_reset_offset = offsetof(struct rk3399_pmucru, 1766 pmucru_softrst_con[0]); 1767 sf_priv->sf_reset_num = 2; 1768 sf_child->priv = sf_priv; 1769 } 1770 1771 return 0; 1772 } 1773 1774 static const struct udevice_id rk3399_pmuclk_ids[] = { 1775 { .compatible = "rockchip,rk3399-pmucru" }, 1776 { } 1777 }; 1778 1779 U_BOOT_DRIVER(rockchip_rk3399_pmuclk) = { 1780 .name = "rockchip_rk3399_pmucru", 1781 .id = UCLASS_CLK, 1782 .of_match = rk3399_pmuclk_ids, 1783 .priv_auto_alloc_size = sizeof(struct rk3399_pmuclk_priv), 1784 .ofdata_to_platdata = rk3399_pmuclk_ofdata_to_platdata, 1785 .ops = &rk3399_pmuclk_ops, 1786 .probe = rk3399_pmuclk_probe, 1787 .bind = rk3399_pmuclk_bind, 1788 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1789 .platdata_auto_alloc_size = sizeof(struct rk3399_pmuclk_plat), 1790 #endif 1791 }; 1792 1793 #ifndef CONFIG_SPL_BUILD 1794 /** 1795 * soc_clk_dump() - Print clock frequencies 1796 * Returns zero on success 1797 * 1798 * Implementation for the clk dump command. 1799 */ 1800 int soc_clk_dump(void) 1801 { 1802 struct udevice *cru_dev, *pmucru_dev; 1803 struct rk3399_clk_priv *priv; 1804 const struct rk3399_clk_info *clk_dump; 1805 struct clk clk; 1806 unsigned long clk_count = ARRAY_SIZE(clks_dump); 1807 unsigned long rate; 1808 int i, ret; 1809 1810 ret = uclass_get_device_by_driver(UCLASS_CLK, 1811 DM_GET_DRIVER(clk_rk3399), 1812 &cru_dev); 1813 if (ret) { 1814 printf("%s failed to get cru device\n", __func__); 1815 return ret; 1816 } 1817 1818 ret = uclass_get_device_by_driver(UCLASS_CLK, 1819 DM_GET_DRIVER(rockchip_rk3399_pmuclk), 1820 &pmucru_dev); 1821 if (ret) { 1822 printf("%s failed to get pmucru device\n", __func__); 1823 return ret; 1824 } 1825 1826 priv = dev_get_priv(cru_dev); 1827 printf("CLK: (%s. arml: enter %lu KHz, init %lu KHz, kernel %lu%s)\n", 1828 priv->sync_kernel ? "sync kernel" : "uboot", 1829 priv->armlclk_enter_hz / 1000, 1830 priv->armlclk_init_hz / 1000, 1831 priv->set_armclk_rate ? priv->armlclk_hz / 1000 : 0, 1832 priv->set_armclk_rate ? " KHz" : "N/A"); 1833 printf("CLK: (%s. armb: enter %lu KHz, init %lu KHz, kernel %lu%s)\n", 1834 priv->sync_kernel ? "sync kernel" : "uboot", 1835 priv->armbclk_enter_hz / 1000, 1836 priv->armbclk_init_hz / 1000, 1837 priv->set_armclk_rate ? priv->armbclk_hz / 1000 : 0, 1838 priv->set_armclk_rate ? " KHz" : "N/A"); 1839 for (i = 0; i < clk_count; i++) { 1840 clk_dump = &clks_dump[i]; 1841 if (clk_dump->name) { 1842 clk.id = clk_dump->id; 1843 if (clk_dump->is_cru) 1844 ret = clk_request(cru_dev, &clk); 1845 else 1846 ret = clk_request(pmucru_dev, &clk); 1847 if (ret < 0) 1848 return ret; 1849 1850 rate = clk_get_rate(&clk); 1851 clk_free(&clk); 1852 if (i == 0) { 1853 if (rate < 0) 1854 printf(" %s %s\n", clk_dump->name, 1855 "unknown"); 1856 else 1857 printf(" %s %lu KHz\n", clk_dump->name, 1858 rate / 1000); 1859 } else { 1860 if (rate < 0) 1861 printf(" %s %s\n", clk_dump->name, 1862 "unknown"); 1863 else 1864 printf(" %s %lu KHz\n", clk_dump->name, 1865 rate / 1000); 1866 } 1867 } 1868 } 1869 1870 return 0; 1871 } 1872 #endif 1873