1 /* 2 * (C) Copyright 2015 Google, Inc 3 * (C) 2017 Theobroma Systems Design und Consulting GmbH 4 * 5 * SPDX-License-Identifier: GPL-2.0 6 */ 7 8 #include <common.h> 9 #include <clk-uclass.h> 10 #include <dm.h> 11 #include <dt-structs.h> 12 #include <errno.h> 13 #include <mapmem.h> 14 #include <syscon.h> 15 #include <bitfield.h> 16 #include <asm/io.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/cru_rk3399.h> 19 #include <asm/arch/hardware.h> 20 #include <dm/lists.h> 21 #include <dt-bindings/clock/rk3399-cru.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #if CONFIG_IS_ENABLED(OF_PLATDATA) 26 struct rk3399_clk_plat { 27 struct dtd_rockchip_rk3399_cru dtd; 28 }; 29 30 struct rk3399_pmuclk_plat { 31 struct dtd_rockchip_rk3399_pmucru dtd; 32 }; 33 #endif 34 35 struct pll_div { 36 u32 refdiv; 37 u32 fbdiv; 38 u32 postdiv1; 39 u32 postdiv2; 40 u32 frac; 41 u32 freq; 42 }; 43 44 #define RATE_TO_DIV(input_rate, output_rate) \ 45 ((input_rate) / (output_rate) - 1); 46 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) 47 48 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ 49 .refdiv = _refdiv,\ 50 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\ 51 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2, .freq = hz}; 52 53 #if !defined(CONFIG_SPL_BUILD) 54 static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1); 55 #endif 56 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 3, 1); 57 static const struct pll_div npll_init_cfg = PLL_DIVISORS(NPLL_HZ, 1, 3, 1); 58 static const struct pll_div apll_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1); 59 static const struct pll_div apll_816_cfg = PLL_DIVISORS(816 * MHz, 1, 2, 1); 60 static const struct pll_div apll_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1); 61 62 static const struct pll_div *apll_cfgs[] = { 63 [APLL_1600_MHZ] = &apll_1600_cfg, 64 [APLL_816_MHZ] = &apll_816_cfg, 65 [APLL_600_MHZ] = &apll_600_cfg, 66 }; 67 68 #ifndef CONFIG_SPL_BUILD 69 #define RK3399_CLK_DUMP(_id, _name, _iscru) \ 70 { \ 71 .id = _id, \ 72 .name = _name, \ 73 .is_cru = _iscru, \ 74 } 75 76 static const struct rk3399_clk_info clks_dump[] = { 77 RK3399_CLK_DUMP(PLL_APLLL, "aplll", true), 78 RK3399_CLK_DUMP(PLL_APLLB, "apllb", true), 79 RK3399_CLK_DUMP(PLL_DPLL, "dpll", true), 80 RK3399_CLK_DUMP(PLL_CPLL, "cpll", true), 81 RK3399_CLK_DUMP(PLL_GPLL, "gpll", true), 82 RK3399_CLK_DUMP(PLL_NPLL, "npll", true), 83 RK3399_CLK_DUMP(PLL_VPLL, "vpll", true), 84 RK3399_CLK_DUMP(ACLK_PERIHP, "aclk_perihp", true), 85 RK3399_CLK_DUMP(HCLK_PERIHP, "hclk_perihp", true), 86 RK3399_CLK_DUMP(PCLK_PERIHP, "pclk_perihp", true), 87 RK3399_CLK_DUMP(ACLK_PERILP0, "aclk_perilp0", true), 88 RK3399_CLK_DUMP(HCLK_PERILP0, "hclk_perilp0", true), 89 RK3399_CLK_DUMP(PCLK_PERILP0, "pclk_perilp0", true), 90 RK3399_CLK_DUMP(HCLK_PERILP1, "hclk_perilp1", true), 91 RK3399_CLK_DUMP(PCLK_PERILP1, "pclk_perilp1", true), 92 }; 93 #endif 94 95 enum { 96 /* PLL_CON0 */ 97 PLL_FBDIV_MASK = 0xfff, 98 PLL_FBDIV_SHIFT = 0, 99 100 /* PLL_CON1 */ 101 PLL_POSTDIV2_SHIFT = 12, 102 PLL_POSTDIV2_MASK = 0x7 << PLL_POSTDIV2_SHIFT, 103 PLL_POSTDIV1_SHIFT = 8, 104 PLL_POSTDIV1_MASK = 0x7 << PLL_POSTDIV1_SHIFT, 105 PLL_REFDIV_MASK = 0x3f, 106 PLL_REFDIV_SHIFT = 0, 107 108 /* PLL_CON2 */ 109 PLL_LOCK_STATUS_SHIFT = 31, 110 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, 111 PLL_FRACDIV_MASK = 0xffffff, 112 PLL_FRACDIV_SHIFT = 0, 113 114 /* PLL_CON3 */ 115 PLL_MODE_SHIFT = 8, 116 PLL_MODE_MASK = 3 << PLL_MODE_SHIFT, 117 PLL_MODE_SLOW = 0, 118 PLL_MODE_NORM, 119 PLL_MODE_DEEP, 120 PLL_DSMPD_SHIFT = 3, 121 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, 122 PLL_INTEGER_MODE = 1, 123 124 /* PMUCRU_CLKSEL_CON0 */ 125 PMU_PCLK_DIV_CON_MASK = 0x1f, 126 PMU_PCLK_DIV_CON_SHIFT = 0, 127 128 /* PMUCRU_CLKSEL_CON1 */ 129 SPI3_PLL_SEL_SHIFT = 7, 130 SPI3_PLL_SEL_MASK = 1 << SPI3_PLL_SEL_SHIFT, 131 SPI3_PLL_SEL_24M = 0, 132 SPI3_PLL_SEL_PPLL = 1, 133 SPI3_DIV_CON_SHIFT = 0x0, 134 SPI3_DIV_CON_MASK = 0x7f, 135 136 /* PMUCRU_CLKSEL_CON2 */ 137 I2C_DIV_CON_MASK = 0x7f, 138 CLK_I2C8_DIV_CON_SHIFT = 8, 139 CLK_I2C0_DIV_CON_SHIFT = 0, 140 141 /* PMUCRU_CLKSEL_CON3 */ 142 CLK_I2C4_DIV_CON_SHIFT = 0, 143 144 /* CLKSEL_CON0 / CLKSEL_CON2 */ 145 ACLKM_CORE_DIV_CON_MASK = 0x1f, 146 ACLKM_CORE_DIV_CON_SHIFT = 8, 147 CLK_CORE_PLL_SEL_MASK = 3, 148 CLK_CORE_PLL_SEL_SHIFT = 6, 149 CLK_CORE_PLL_SEL_ALPLL = 0x0, 150 CLK_CORE_PLL_SEL_ABPLL = 0x1, 151 CLK_CORE_PLL_SEL_DPLL = 0x10, 152 CLK_CORE_PLL_SEL_GPLL = 0x11, 153 CLK_CORE_DIV_MASK = 0x1f, 154 CLK_CORE_DIV_SHIFT = 0, 155 156 /* CLKSEL_CON1 / CLKSEL_CON3 */ 157 PCLK_DBG_DIV_MASK = 0x1f, 158 PCLK_DBG_DIV_SHIFT = 0x8, 159 ATCLK_CORE_DIV_MASK = 0x1f, 160 ATCLK_CORE_DIV_SHIFT = 0, 161 162 /* CLKSEL_CON14 */ 163 PCLK_PERIHP_DIV_CON_SHIFT = 12, 164 PCLK_PERIHP_DIV_CON_MASK = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT, 165 HCLK_PERIHP_DIV_CON_SHIFT = 8, 166 HCLK_PERIHP_DIV_CON_MASK = 3 << HCLK_PERIHP_DIV_CON_SHIFT, 167 ACLK_PERIHP_PLL_SEL_SHIFT = 7, 168 ACLK_PERIHP_PLL_SEL_MASK = 1 << ACLK_PERIHP_PLL_SEL_SHIFT, 169 ACLK_PERIHP_PLL_SEL_CPLL = 0, 170 ACLK_PERIHP_PLL_SEL_GPLL = 1, 171 ACLK_PERIHP_DIV_CON_SHIFT = 0, 172 ACLK_PERIHP_DIV_CON_MASK = 0x1f, 173 174 /* CLKSEL_CON21 */ 175 ACLK_EMMC_PLL_SEL_SHIFT = 7, 176 ACLK_EMMC_PLL_SEL_MASK = 0x1 << ACLK_EMMC_PLL_SEL_SHIFT, 177 ACLK_EMMC_PLL_SEL_GPLL = 0x1, 178 ACLK_EMMC_DIV_CON_SHIFT = 0, 179 ACLK_EMMC_DIV_CON_MASK = 0x1f, 180 181 /* CLKSEL_CON22 */ 182 CLK_EMMC_PLL_SHIFT = 8, 183 CLK_EMMC_PLL_MASK = 0x7 << CLK_EMMC_PLL_SHIFT, 184 CLK_EMMC_PLL_SEL_GPLL = 0x1, 185 CLK_EMMC_PLL_SEL_24M = 0x5, 186 CLK_EMMC_DIV_CON_SHIFT = 0, 187 CLK_EMMC_DIV_CON_MASK = 0x7f << CLK_EMMC_DIV_CON_SHIFT, 188 189 /* CLKSEL_CON23 */ 190 PCLK_PERILP0_DIV_CON_SHIFT = 12, 191 PCLK_PERILP0_DIV_CON_MASK = 0x7 << PCLK_PERILP0_DIV_CON_SHIFT, 192 HCLK_PERILP0_DIV_CON_SHIFT = 8, 193 HCLK_PERILP0_DIV_CON_MASK = 3 << HCLK_PERILP0_DIV_CON_SHIFT, 194 ACLK_PERILP0_PLL_SEL_SHIFT = 7, 195 ACLK_PERILP0_PLL_SEL_MASK = 1 << ACLK_PERILP0_PLL_SEL_SHIFT, 196 ACLK_PERILP0_PLL_SEL_CPLL = 0, 197 ACLK_PERILP0_PLL_SEL_GPLL = 1, 198 ACLK_PERILP0_DIV_CON_SHIFT = 0, 199 ACLK_PERILP0_DIV_CON_MASK = 0x1f, 200 201 /* CRU_CLK_SEL24_CON */ 202 CRYPTO0_PLL_SEL_SHIFT = 6, 203 CRYPTO0_PLL_SEL_MASK = 3 << CRYPTO0_PLL_SEL_SHIFT, 204 CRYPTO_PLL_SEL_CPLL = 0, 205 CRYPTO_PLL_SEL_GPLL, 206 CRYPTO_PLL_SEL_PPLL = 0, 207 CRYPTO0_DIV_SHIFT = 0, 208 CRYPTO0_DIV_MASK = 0x1f << CRYPTO0_DIV_SHIFT, 209 210 /* CLKSEL_CON25 */ 211 PCLK_PERILP1_DIV_CON_SHIFT = 8, 212 PCLK_PERILP1_DIV_CON_MASK = 0x7 << PCLK_PERILP1_DIV_CON_SHIFT, 213 HCLK_PERILP1_PLL_SEL_SHIFT = 7, 214 HCLK_PERILP1_PLL_SEL_MASK = 1 << HCLK_PERILP1_PLL_SEL_SHIFT, 215 HCLK_PERILP1_PLL_SEL_CPLL = 0, 216 HCLK_PERILP1_PLL_SEL_GPLL = 1, 217 HCLK_PERILP1_DIV_CON_SHIFT = 0, 218 HCLK_PERILP1_DIV_CON_MASK = 0x1f, 219 220 /* CLKSEL_CON26 */ 221 CLK_SARADC_DIV_CON_SHIFT = 8, 222 CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8), 223 CLK_SARADC_DIV_CON_WIDTH = 8, 224 CRYPTO1_PLL_SEL_SHIFT = 6, 225 CRYPTO1_PLL_SEL_MASK = 3 << CRYPTO1_PLL_SEL_SHIFT, 226 CRYPTO1_DIV_SHIFT = 0, 227 CRYPTO1_DIV_MASK = 0x1f << CRYPTO1_DIV_SHIFT, 228 229 /* CLKSEL_CON27 */ 230 CLK_TSADC_SEL_X24M = 0x0, 231 CLK_TSADC_SEL_SHIFT = 15, 232 CLK_TSADC_SEL_MASK = 1 << CLK_TSADC_SEL_SHIFT, 233 CLK_TSADC_DIV_CON_SHIFT = 0, 234 CLK_TSADC_DIV_CON_MASK = 0x3ff, 235 236 /* CLKSEL_CON47 & CLKSEL_CON48 */ 237 ACLK_VOP_PLL_SEL_SHIFT = 6, 238 ACLK_VOP_PLL_SEL_MASK = 0x3 << ACLK_VOP_PLL_SEL_SHIFT, 239 ACLK_VOP_PLL_SEL_CPLL = 0x1, 240 ACLK_VOP_PLL_SEL_GPLL = 0x2, 241 ACLK_VOP_DIV_CON_SHIFT = 0, 242 ACLK_VOP_DIV_CON_MASK = 0x1f << ACLK_VOP_DIV_CON_SHIFT, 243 244 /* CLKSEL_CON49 & CLKSEL_CON50 */ 245 DCLK_VOP_DCLK_SEL_SHIFT = 11, 246 DCLK_VOP_DCLK_SEL_MASK = 1 << DCLK_VOP_DCLK_SEL_SHIFT, 247 DCLK_VOP_DCLK_SEL_DIVOUT = 0, 248 DCLK_VOP_PLL_SEL_SHIFT = 8, 249 DCLK_VOP_PLL_SEL_MASK = 3 << DCLK_VOP_PLL_SEL_SHIFT, 250 DCLK_VOP_PLL_SEL_VPLL = 0, 251 DCLK_VOP_PLL_SEL_CPLL = 1, 252 DCLK_VOP_DIV_CON_MASK = 0xff, 253 DCLK_VOP_DIV_CON_SHIFT = 0, 254 255 /* CLKSEL_CON58 */ 256 CLK_SPI_PLL_SEL_WIDTH = 1, 257 CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1), 258 CLK_SPI_PLL_SEL_CPLL = 0, 259 CLK_SPI_PLL_SEL_GPLL = 1, 260 CLK_SPI_PLL_DIV_CON_WIDTH = 7, 261 CLK_SPI_PLL_DIV_CON_MASK = ((1 << CLK_SPI_PLL_DIV_CON_WIDTH) - 1), 262 263 CLK_SPI5_PLL_DIV_CON_SHIFT = 8, 264 CLK_SPI5_PLL_SEL_SHIFT = 15, 265 266 /* CLKSEL_CON59 */ 267 CLK_SPI1_PLL_SEL_SHIFT = 15, 268 CLK_SPI1_PLL_DIV_CON_SHIFT = 8, 269 CLK_SPI0_PLL_SEL_SHIFT = 7, 270 CLK_SPI0_PLL_DIV_CON_SHIFT = 0, 271 272 /* CLKSEL_CON60 */ 273 CLK_SPI4_PLL_SEL_SHIFT = 15, 274 CLK_SPI4_PLL_DIV_CON_SHIFT = 8, 275 CLK_SPI2_PLL_SEL_SHIFT = 7, 276 CLK_SPI2_PLL_DIV_CON_SHIFT = 0, 277 278 /* CLKSEL_CON61 */ 279 CLK_I2C_PLL_SEL_MASK = 1, 280 CLK_I2C_PLL_SEL_CPLL = 0, 281 CLK_I2C_PLL_SEL_GPLL = 1, 282 CLK_I2C5_PLL_SEL_SHIFT = 15, 283 CLK_I2C5_DIV_CON_SHIFT = 8, 284 CLK_I2C1_PLL_SEL_SHIFT = 7, 285 CLK_I2C1_DIV_CON_SHIFT = 0, 286 287 /* CLKSEL_CON62 */ 288 CLK_I2C6_PLL_SEL_SHIFT = 15, 289 CLK_I2C6_DIV_CON_SHIFT = 8, 290 CLK_I2C2_PLL_SEL_SHIFT = 7, 291 CLK_I2C2_DIV_CON_SHIFT = 0, 292 293 /* CLKSEL_CON63 */ 294 CLK_I2C7_PLL_SEL_SHIFT = 15, 295 CLK_I2C7_DIV_CON_SHIFT = 8, 296 CLK_I2C3_PLL_SEL_SHIFT = 7, 297 CLK_I2C3_DIV_CON_SHIFT = 0, 298 299 /* CRU_SOFTRST_CON4 */ 300 RESETN_DDR0_REQ_SHIFT = 8, 301 RESETN_DDR0_REQ_MASK = 1 << RESETN_DDR0_REQ_SHIFT, 302 RESETN_DDRPHY0_REQ_SHIFT = 9, 303 RESETN_DDRPHY0_REQ_MASK = 1 << RESETN_DDRPHY0_REQ_SHIFT, 304 RESETN_DDR1_REQ_SHIFT = 12, 305 RESETN_DDR1_REQ_MASK = 1 << RESETN_DDR1_REQ_SHIFT, 306 RESETN_DDRPHY1_REQ_SHIFT = 13, 307 RESETN_DDRPHY1_REQ_MASK = 1 << RESETN_DDRPHY1_REQ_SHIFT, 308 }; 309 310 #define VCO_MAX_KHZ (3200 * (MHz / KHz)) 311 #define VCO_MIN_KHZ (800 * (MHz / KHz)) 312 #define OUTPUT_MAX_KHZ (3200 * (MHz / KHz)) 313 #define OUTPUT_MIN_KHZ (16 * (MHz / KHz)) 314 315 /* 316 * the div restructions of pll in integer mode, these are defined in 317 * * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0 318 */ 319 #define PLL_DIV_MIN 16 320 #define PLL_DIV_MAX 3200 321 322 /* 323 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63): 324 * Formulas also embedded within the Fractional PLL Verilog model: 325 * If DSMPD = 1 (DSM is disabled, "integer mode") 326 * FOUTVCO = FREF / REFDIV * FBDIV 327 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2 328 * Where: 329 * FOUTVCO = Fractional PLL non-divided output frequency 330 * FOUTPOSTDIV = Fractional PLL divided output frequency 331 * (output of second post divider) 332 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input) 333 * REFDIV = Fractional PLL input reference clock divider 334 * FBDIV = Integer value programmed into feedback divide 335 * 336 */ 337 338 static uint32_t rkclk_pll_get_rate(u32 *pll_con) 339 { 340 u32 refdiv, fbdiv, postdiv1, postdiv2; 341 u32 con; 342 343 con = readl(&pll_con[3]); 344 switch ((con & PLL_MODE_MASK) >> PLL_MODE_SHIFT) { 345 case PLL_MODE_SLOW: 346 return OSC_HZ; 347 case PLL_MODE_NORM: 348 /* normal mode */ 349 con = readl(&pll_con[0]); 350 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; 351 con = readl(&pll_con[1]); 352 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; 353 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; 354 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; 355 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; 356 case PLL_MODE_DEEP: 357 default: 358 return 32768; 359 } 360 } 361 362 static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div) 363 { 364 /* All 8 PLLs have same VCO and output frequency range restrictions. */ 365 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; 366 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2; 367 368 debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, " 369 "postdiv2=%d, vco=%u khz, output=%u khz\n", 370 pll_con, div->fbdiv, div->refdiv, div->postdiv1, 371 div->postdiv2, vco_khz, output_khz); 372 assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ && 373 output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ && 374 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); 375 376 /* 377 * When power on or changing PLL setting, 378 * we must force PLL into slow mode to ensure output stable clock. 379 */ 380 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK, 381 PLL_MODE_SLOW << PLL_MODE_SHIFT); 382 383 /* use integer mode */ 384 rk_clrsetreg(&pll_con[3], PLL_DSMPD_MASK, 385 PLL_INTEGER_MODE << PLL_DSMPD_SHIFT); 386 387 rk_clrsetreg(&pll_con[0], PLL_FBDIV_MASK, 388 div->fbdiv << PLL_FBDIV_SHIFT); 389 rk_clrsetreg(&pll_con[1], 390 PLL_POSTDIV2_MASK | PLL_POSTDIV1_MASK | 391 PLL_REFDIV_MASK | PLL_REFDIV_SHIFT, 392 (div->postdiv2 << PLL_POSTDIV2_SHIFT) | 393 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | 394 (div->refdiv << PLL_REFDIV_SHIFT)); 395 396 /* waiting for pll lock */ 397 while (!(readl(&pll_con[2]) & (1 << PLL_LOCK_STATUS_SHIFT))) 398 udelay(1); 399 400 /* pll enter normal mode */ 401 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK, 402 PLL_MODE_NORM << PLL_MODE_SHIFT); 403 } 404 405 static ulong rk3399_pll_get_rate(struct rk3399_clk_priv *priv, 406 enum rk3399_pll_id pll_id) 407 { 408 struct rk3399_cru *cru = priv->cru; 409 u32 *pll_con; 410 411 switch (pll_id) { 412 case PLL_APLLL: 413 pll_con = &cru->apll_l_con[0]; 414 break; 415 case PLL_APLLB: 416 pll_con = &cru->apll_b_con[0]; 417 break; 418 case PLL_DPLL: 419 pll_con = &cru->dpll_con[0]; 420 break; 421 case PLL_CPLL: 422 pll_con = &cru->cpll_con[0]; 423 break; 424 case PLL_GPLL: 425 pll_con = &cru->gpll_con[0]; 426 break; 427 case PLL_NPLL: 428 pll_con = &cru->npll_con[0]; 429 break; 430 case PLL_VPLL: 431 pll_con = &cru->vpll_con[0]; 432 break; 433 default: 434 pll_con = &cru->vpll_con[0]; 435 break; 436 } 437 438 return rkclk_pll_get_rate(pll_con); 439 } 440 441 static int pll_para_config(u32 freq_hz, struct pll_div *div) 442 { 443 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; 444 u32 postdiv1, postdiv2 = 1; 445 u32 fref_khz; 446 u32 diff_khz, best_diff_khz; 447 const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16; 448 const u32 max_postdiv1 = 7, max_postdiv2 = 7; 449 u32 vco_khz; 450 u32 freq_khz = freq_hz / KHz; 451 452 if (!freq_hz) { 453 printf("%s: the frequency can't be 0 Hz\n", __func__); 454 return -1; 455 } 456 457 postdiv1 = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz); 458 if (postdiv1 > max_postdiv1) { 459 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); 460 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); 461 } 462 463 vco_khz = freq_khz * postdiv1 * postdiv2; 464 465 if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || 466 postdiv2 > max_postdiv2) { 467 printf("%s: Cannot find out a supported VCO" 468 " for Frequency (%uHz).\n", __func__, freq_hz); 469 return -1; 470 } 471 472 div->postdiv1 = postdiv1; 473 div->postdiv2 = postdiv2; 474 475 best_diff_khz = vco_khz; 476 for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) { 477 fref_khz = ref_khz / refdiv; 478 479 fbdiv = vco_khz / fref_khz; 480 if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv)) 481 continue; 482 diff_khz = vco_khz - fbdiv * fref_khz; 483 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) { 484 fbdiv++; 485 diff_khz = fref_khz - diff_khz; 486 } 487 488 if (diff_khz >= best_diff_khz) 489 continue; 490 491 best_diff_khz = diff_khz; 492 div->refdiv = refdiv; 493 div->fbdiv = fbdiv; 494 } 495 496 if (best_diff_khz > 4 * (MHz/KHz)) { 497 printf("%s: Failed to match output frequency %u, " 498 "difference is %u Hz,exceed 4MHZ\n", __func__, freq_hz, 499 best_diff_khz * KHz); 500 return -1; 501 } 502 return 0; 503 } 504 505 void rk3399_configure_cpu(struct rk3399_cru *cru, 506 enum apll_frequencies freq, 507 enum cpu_cluster cluster) 508 { 509 u32 aclkm_div; 510 u32 pclk_dbg_div; 511 u32 atclk_div, apll_hz; 512 int con_base, parent; 513 u32 *pll_con; 514 515 switch (cluster) { 516 case CPU_CLUSTER_LITTLE: 517 con_base = 0; 518 parent = CLK_CORE_PLL_SEL_ALPLL; 519 pll_con = &cru->apll_l_con[0]; 520 break; 521 case CPU_CLUSTER_BIG: 522 default: 523 con_base = 2; 524 parent = CLK_CORE_PLL_SEL_ABPLL; 525 pll_con = &cru->apll_b_con[0]; 526 break; 527 } 528 529 apll_hz = apll_cfgs[freq]->freq; 530 rkclk_set_pll(pll_con, apll_cfgs[freq]); 531 532 aclkm_div = apll_hz / ACLKM_CORE_HZ - 1; 533 assert((aclkm_div + 1) * ACLKM_CORE_HZ == apll_hz && 534 aclkm_div < 0x1f); 535 536 pclk_dbg_div = apll_hz / PCLK_DBG_HZ - 1; 537 assert((pclk_dbg_div + 1) * PCLK_DBG_HZ == apll_hz && 538 pclk_dbg_div < 0x1f); 539 540 atclk_div = apll_hz / ATCLK_CORE_HZ - 1; 541 assert((atclk_div + 1) * ATCLK_CORE_HZ == apll_hz && 542 atclk_div < 0x1f); 543 544 rk_clrsetreg(&cru->clksel_con[con_base], 545 ACLKM_CORE_DIV_CON_MASK | CLK_CORE_PLL_SEL_MASK | 546 CLK_CORE_DIV_MASK, 547 aclkm_div << ACLKM_CORE_DIV_CON_SHIFT | 548 parent << CLK_CORE_PLL_SEL_SHIFT | 549 0 << CLK_CORE_DIV_SHIFT); 550 551 rk_clrsetreg(&cru->clksel_con[con_base + 1], 552 PCLK_DBG_DIV_MASK | ATCLK_CORE_DIV_MASK, 553 pclk_dbg_div << PCLK_DBG_DIV_SHIFT | 554 atclk_div << ATCLK_CORE_DIV_SHIFT); 555 } 556 #define I2C_CLK_REG_MASK(bus) \ 557 (I2C_DIV_CON_MASK << \ 558 CLK_I2C ##bus## _DIV_CON_SHIFT | \ 559 CLK_I2C_PLL_SEL_MASK << \ 560 CLK_I2C ##bus## _PLL_SEL_SHIFT) 561 562 #define I2C_CLK_REG_VALUE(bus, clk_div) \ 563 ((clk_div - 1) << \ 564 CLK_I2C ##bus## _DIV_CON_SHIFT | \ 565 CLK_I2C_PLL_SEL_GPLL << \ 566 CLK_I2C ##bus## _PLL_SEL_SHIFT) 567 568 #define I2C_CLK_DIV_VALUE(con, bus) \ 569 (con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & \ 570 I2C_DIV_CON_MASK; 571 572 #define I2C_PMUCLK_REG_MASK(bus) \ 573 (I2C_DIV_CON_MASK << \ 574 CLK_I2C ##bus## _DIV_CON_SHIFT) 575 576 #define I2C_PMUCLK_REG_VALUE(bus, clk_div) \ 577 ((clk_div - 1) << \ 578 CLK_I2C ##bus## _DIV_CON_SHIFT) 579 580 static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id) 581 { 582 u32 div, con; 583 584 switch (clk_id) { 585 case SCLK_I2C1: 586 con = readl(&cru->clksel_con[61]); 587 div = I2C_CLK_DIV_VALUE(con, 1); 588 break; 589 case SCLK_I2C2: 590 con = readl(&cru->clksel_con[62]); 591 div = I2C_CLK_DIV_VALUE(con, 2); 592 break; 593 case SCLK_I2C3: 594 con = readl(&cru->clksel_con[63]); 595 div = I2C_CLK_DIV_VALUE(con, 3); 596 break; 597 case SCLK_I2C5: 598 con = readl(&cru->clksel_con[61]); 599 div = I2C_CLK_DIV_VALUE(con, 5); 600 break; 601 case SCLK_I2C6: 602 con = readl(&cru->clksel_con[62]); 603 div = I2C_CLK_DIV_VALUE(con, 6); 604 break; 605 case SCLK_I2C7: 606 con = readl(&cru->clksel_con[63]); 607 div = I2C_CLK_DIV_VALUE(con, 7); 608 break; 609 default: 610 printf("do not support this i2c bus\n"); 611 return -EINVAL; 612 } 613 614 return DIV_TO_RATE(GPLL_HZ, div); 615 } 616 617 static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) 618 { 619 int src_clk_div; 620 621 /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/ 622 src_clk_div = GPLL_HZ / hz; 623 assert(src_clk_div - 1 <= 127); 624 625 switch (clk_id) { 626 case SCLK_I2C1: 627 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(1), 628 I2C_CLK_REG_VALUE(1, src_clk_div)); 629 break; 630 case SCLK_I2C2: 631 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(2), 632 I2C_CLK_REG_VALUE(2, src_clk_div)); 633 break; 634 case SCLK_I2C3: 635 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(3), 636 I2C_CLK_REG_VALUE(3, src_clk_div)); 637 break; 638 case SCLK_I2C5: 639 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(5), 640 I2C_CLK_REG_VALUE(5, src_clk_div)); 641 break; 642 case SCLK_I2C6: 643 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(6), 644 I2C_CLK_REG_VALUE(6, src_clk_div)); 645 break; 646 case SCLK_I2C7: 647 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(7), 648 I2C_CLK_REG_VALUE(7, src_clk_div)); 649 break; 650 default: 651 printf("do not support this i2c bus\n"); 652 return -EINVAL; 653 } 654 655 return rk3399_i2c_get_clk(cru, clk_id); 656 } 657 658 /* 659 * RK3399 SPI clocks have a common divider-width (7 bits) and a single bit 660 * to select either CPLL or GPLL as the clock-parent. The location within 661 * the enclosing CLKSEL_CON (i.e. div_shift and sel_shift) are variable. 662 */ 663 664 struct spi_clkreg { 665 uint8_t reg; /* CLKSEL_CON[reg] register in CRU */ 666 uint8_t div_shift; 667 uint8_t sel_shift; 668 }; 669 670 /* 671 * The entries are numbered relative to their offset from SCLK_SPI0. 672 * 673 * Note that SCLK_SPI3 (which is configured via PMUCRU and requires different 674 * logic is not supported). 675 */ 676 static const struct spi_clkreg spi_clkregs[] = { 677 [0] = { .reg = 59, 678 .div_shift = CLK_SPI0_PLL_DIV_CON_SHIFT, 679 .sel_shift = CLK_SPI0_PLL_SEL_SHIFT, }, 680 [1] = { .reg = 59, 681 .div_shift = CLK_SPI1_PLL_DIV_CON_SHIFT, 682 .sel_shift = CLK_SPI1_PLL_SEL_SHIFT, }, 683 [2] = { .reg = 60, 684 .div_shift = CLK_SPI2_PLL_DIV_CON_SHIFT, 685 .sel_shift = CLK_SPI2_PLL_SEL_SHIFT, }, 686 [3] = { .reg = 60, 687 .div_shift = CLK_SPI4_PLL_DIV_CON_SHIFT, 688 .sel_shift = CLK_SPI4_PLL_SEL_SHIFT, }, 689 [4] = { .reg = 58, 690 .div_shift = CLK_SPI5_PLL_DIV_CON_SHIFT, 691 .sel_shift = CLK_SPI5_PLL_SEL_SHIFT, }, 692 }; 693 694 static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id) 695 { 696 const struct spi_clkreg *spiclk = NULL; 697 u32 div, val; 698 699 switch (clk_id) { 700 case SCLK_SPI0 ... SCLK_SPI5: 701 spiclk = &spi_clkregs[clk_id - SCLK_SPI0]; 702 break; 703 704 default: 705 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id); 706 return -EINVAL; 707 } 708 709 val = readl(&cru->clksel_con[spiclk->reg]); 710 div = bitfield_extract(val, spiclk->div_shift, 711 CLK_SPI_PLL_DIV_CON_WIDTH); 712 713 return DIV_TO_RATE(GPLL_HZ, div); 714 } 715 716 static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) 717 { 718 const struct spi_clkreg *spiclk = NULL; 719 int src_clk_div; 720 721 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; 722 assert(src_clk_div < 128); 723 724 switch (clk_id) { 725 case SCLK_SPI1 ... SCLK_SPI5: 726 spiclk = &spi_clkregs[clk_id - SCLK_SPI0]; 727 break; 728 729 default: 730 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id); 731 return -EINVAL; 732 } 733 734 rk_clrsetreg(&cru->clksel_con[spiclk->reg], 735 ((CLK_SPI_PLL_DIV_CON_MASK << spiclk->div_shift) | 736 (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)), 737 ((src_clk_div << spiclk->div_shift) | 738 (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift))); 739 740 return rk3399_spi_get_clk(cru, clk_id); 741 } 742 743 #define RK3399_LIMIT_PLL_ACLK_VOP (400 * 1000000) 744 745 static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz) 746 { 747 struct pll_div vpll_config = {0}, cpll_config = {0}; 748 int aclk_vop = RK3399_LIMIT_PLL_ACLK_VOP; 749 void *aclkreg_addr, *dclkreg_addr; 750 u32 div = 1; 751 752 switch (clk_id) { 753 case DCLK_VOP0: 754 aclkreg_addr = &cru->clksel_con[47]; 755 dclkreg_addr = &cru->clksel_con[49]; 756 break; 757 case DCLK_VOP1: 758 aclkreg_addr = &cru->clksel_con[48]; 759 dclkreg_addr = &cru->clksel_con[50]; 760 break; 761 default: 762 return -EINVAL; 763 } 764 /* vop aclk source clk: cpll */ 765 div = GPLL_HZ / aclk_vop; 766 assert(div - 1 <= 31); 767 768 rk_clrsetreg(aclkreg_addr, 769 ACLK_VOP_PLL_SEL_MASK | ACLK_VOP_DIV_CON_MASK, 770 ACLK_VOP_PLL_SEL_GPLL << ACLK_VOP_PLL_SEL_SHIFT | 771 (div - 1) << ACLK_VOP_DIV_CON_SHIFT); 772 773 if (readl(dclkreg_addr) & DCLK_VOP_PLL_SEL_MASK) { 774 if (pll_para_config(hz, &cpll_config)) 775 return -1; 776 rkclk_set_pll(&cru->cpll_con[0], &cpll_config); 777 } else { 778 if (pll_para_config(hz, &vpll_config)) 779 return -1; 780 rkclk_set_pll(&cru->vpll_con[0], &vpll_config); 781 } 782 783 rk_clrsetreg(dclkreg_addr, 784 DCLK_VOP_DCLK_SEL_MASK | DCLK_VOP_DIV_CON_MASK, 785 DCLK_VOP_DCLK_SEL_DIVOUT << DCLK_VOP_DCLK_SEL_SHIFT | 786 (1 - 1) << DCLK_VOP_DIV_CON_SHIFT); 787 788 return hz; 789 } 790 791 static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id) 792 { 793 u32 div, con; 794 795 switch (clk_id) { 796 case HCLK_SDMMC: 797 case SCLK_SDMMC: 798 con = readl(&cru->clksel_con[16]); 799 /* dwmmc controller have internal div 2 */ 800 div = 2; 801 break; 802 case SCLK_EMMC: 803 con = readl(&cru->clksel_con[22]); 804 div = 1; 805 break; 806 default: 807 return -EINVAL; 808 } 809 810 div *= (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT; 811 if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT 812 == CLK_EMMC_PLL_SEL_24M) 813 return DIV_TO_RATE(OSC_HZ, div); 814 else 815 return DIV_TO_RATE(GPLL_HZ, div); 816 } 817 818 static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru, 819 ulong clk_id, ulong set_rate) 820 { 821 int src_clk_div; 822 int aclk_emmc = 198*MHz; 823 824 switch (clk_id) { 825 case HCLK_SDMMC: 826 case SCLK_SDMMC: 827 /* Select clk_sdmmc source from GPLL by default */ 828 /* mmc clock defaulg div 2 internal, provide double in cru */ 829 src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate); 830 831 if (src_clk_div > 128) { 832 /* use 24MHz source for 400KHz clock */ 833 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); 834 assert(src_clk_div - 1 < 128); 835 rk_clrsetreg(&cru->clksel_con[16], 836 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, 837 CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT | 838 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); 839 } else { 840 rk_clrsetreg(&cru->clksel_con[16], 841 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, 842 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT | 843 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); 844 } 845 break; 846 case SCLK_EMMC: 847 /* Select aclk_emmc source from GPLL */ 848 src_clk_div = DIV_ROUND_UP(GPLL_HZ , aclk_emmc); 849 assert(src_clk_div - 1 < 32); 850 851 rk_clrsetreg(&cru->clksel_con[21], 852 ACLK_EMMC_PLL_SEL_MASK | ACLK_EMMC_DIV_CON_MASK, 853 ACLK_EMMC_PLL_SEL_GPLL << ACLK_EMMC_PLL_SEL_SHIFT | 854 (src_clk_div - 1) << ACLK_EMMC_DIV_CON_SHIFT); 855 856 /* Select clk_emmc source from GPLL too */ 857 src_clk_div = DIV_ROUND_UP(GPLL_HZ, set_rate); 858 if (src_clk_div > 128) { 859 /* use 24MHz source for 400KHz clock */ 860 src_clk_div = DIV_ROUND_UP(OSC_HZ, set_rate); 861 assert(src_clk_div - 1 < 128); 862 rk_clrsetreg(&cru->clksel_con[22], 863 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, 864 CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT | 865 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); 866 } else { 867 rk_clrsetreg(&cru->clksel_con[22], 868 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, 869 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT | 870 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); 871 } 872 break; 873 default: 874 return -EINVAL; 875 } 876 return rk3399_mmc_get_clk(cru, clk_id); 877 } 878 879 static ulong rk3399_gmac_set_clk(struct rk3399_cru *cru, ulong rate) 880 { 881 ulong ret; 882 883 /* 884 * The RGMII CLK can be derived either from an external "clkin" 885 * or can be generated from internally by a divider from SCLK_MAC. 886 */ 887 if (readl(&cru->clksel_con[19]) & BIT(4)) { 888 /* An external clock will always generate the right rate... */ 889 ret = rate; 890 } else { 891 /* 892 * No platform uses an internal clock to date. 893 * Implement this once it becomes necessary and print an error 894 * if someone tries to use it (while it remains unimplemented). 895 */ 896 pr_err("%s: internal clock is UNIMPLEMENTED\n", __func__); 897 ret = 0; 898 } 899 900 return ret; 901 } 902 903 #define PMUSGRF_DDR_RGN_CON16 0xff330040 904 static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru, 905 ulong set_rate) 906 { 907 struct pll_div dpll_cfg; 908 909 /* IC ECO bug, need to set this register */ 910 writel(0xc000c000, PMUSGRF_DDR_RGN_CON16); 911 912 /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */ 913 switch (set_rate) { 914 case 200*MHz: 915 dpll_cfg = (struct pll_div) 916 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1}; 917 break; 918 case 300*MHz: 919 dpll_cfg = (struct pll_div) 920 {.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1}; 921 break; 922 case 666*MHz: 923 dpll_cfg = (struct pll_div) 924 {.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1}; 925 break; 926 case 800*MHz: 927 dpll_cfg = (struct pll_div) 928 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}; 929 break; 930 case 933*MHz: 931 dpll_cfg = (struct pll_div) 932 {.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1}; 933 break; 934 default: 935 pr_err("Unsupported SDRAM frequency!,%ld\n", set_rate); 936 } 937 rkclk_set_pll(&cru->dpll_con[0], &dpll_cfg); 938 939 return set_rate; 940 } 941 942 static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru) 943 { 944 u32 div, val; 945 946 val = readl(&cru->clksel_con[26]); 947 div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT, 948 CLK_SARADC_DIV_CON_WIDTH); 949 950 return DIV_TO_RATE(OSC_HZ, div); 951 } 952 953 static ulong rk3399_saradc_set_clk(struct rk3399_cru *cru, uint hz) 954 { 955 int src_clk_div; 956 957 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; 958 assert(src_clk_div <= 255); 959 960 rk_clrsetreg(&cru->clksel_con[26], 961 CLK_SARADC_DIV_CON_MASK, 962 src_clk_div << CLK_SARADC_DIV_CON_SHIFT); 963 964 return rk3399_saradc_get_clk(cru); 965 } 966 967 static ulong rk3399_tsadc_get_clk(struct rk3399_cru *cru) 968 { 969 u32 div, val; 970 971 val = readl(&cru->clksel_con[27]); 972 div = bitfield_extract(val, CLK_TSADC_SEL_SHIFT, 973 10); 974 975 return DIV_TO_RATE(OSC_HZ, div); 976 } 977 978 static ulong rk3399_tsadc_set_clk(struct rk3399_cru *cru, uint hz) 979 { 980 int src_clk_div; 981 982 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; 983 assert(src_clk_div <= 255); 984 985 rk_clrsetreg(&cru->clksel_con[27], 986 CLK_TSADC_DIV_CON_MASK | CLK_TSADC_SEL_MASK, 987 (CLK_TSADC_SEL_X24M << CLK_TSADC_SEL_SHIFT) | 988 (src_clk_div << CLK_TSADC_DIV_CON_SHIFT)); 989 990 return rk3399_tsadc_get_clk(cru); 991 } 992 993 #ifndef CONFIG_SPL_BUILD 994 static ulong rk3399_crypto_get_clk(struct rk3399_clk_priv *priv, ulong clk_id) 995 { 996 struct rk3399_cru *cru = priv->cru; 997 u32 div, con, parent; 998 999 switch (clk_id) { 1000 case SCLK_CRYPTO0: 1001 con = readl(&cru->clksel_con[24]); 1002 div = (con & CRYPTO0_DIV_MASK) >> CRYPTO0_DIV_SHIFT; 1003 parent = GPLL_HZ; 1004 break; 1005 case SCLK_CRYPTO1: 1006 con = readl(&cru->clksel_con[26]); 1007 div = (con & CRYPTO1_DIV_MASK) >> CRYPTO1_DIV_SHIFT; 1008 parent = GPLL_HZ; 1009 break; 1010 default: 1011 return -ENOENT; 1012 } 1013 1014 return DIV_TO_RATE(parent, div); 1015 } 1016 1017 static ulong rk3399_crypto_set_clk(struct rk3399_clk_priv *priv, ulong clk_id, 1018 ulong hz) 1019 { 1020 struct rk3399_cru *cru = priv->cru; 1021 int src_clk_div; 1022 1023 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz); 1024 assert(src_clk_div - 1 <= 31); 1025 1026 /* 1027 * select gpll as crypto clock source and 1028 * set up dependent divisors for crypto clocks. 1029 */ 1030 switch (clk_id) { 1031 case SCLK_CRYPTO0: 1032 rk_clrsetreg(&cru->clksel_con[24], 1033 CRYPTO0_PLL_SEL_MASK | CRYPTO0_DIV_MASK, 1034 CRYPTO_PLL_SEL_GPLL << CRYPTO0_PLL_SEL_SHIFT | 1035 (src_clk_div - 1) << CRYPTO0_DIV_SHIFT); 1036 break; 1037 case SCLK_CRYPTO1: 1038 rk_clrsetreg(&cru->clksel_con[26], 1039 CRYPTO1_PLL_SEL_MASK | CRYPTO1_DIV_MASK, 1040 CRYPTO_PLL_SEL_GPLL << CRYPTO1_PLL_SEL_SHIFT | 1041 (src_clk_div - 1) << CRYPTO1_DIV_SHIFT); 1042 break; 1043 default: 1044 printf("do not support this peri freq\n"); 1045 return -EINVAL; 1046 } 1047 1048 return rk3399_crypto_get_clk(priv, clk_id); 1049 } 1050 1051 static ulong rk3399_peri_get_clk(struct rk3399_clk_priv *priv, ulong clk_id) 1052 { 1053 struct rk3399_cru *cru = priv->cru; 1054 u32 div, con, parent; 1055 1056 switch (clk_id) { 1057 case ACLK_PERIHP: 1058 con = readl(&cru->clksel_con[14]); 1059 div = (con & ACLK_PERIHP_DIV_CON_MASK) >> 1060 ACLK_PERIHP_DIV_CON_SHIFT; 1061 parent = GPLL_HZ; 1062 break; 1063 case PCLK_PERIHP: 1064 con = readl(&cru->clksel_con[14]); 1065 div = (con & PCLK_PERIHP_DIV_CON_MASK) >> 1066 PCLK_PERIHP_DIV_CON_SHIFT; 1067 parent = rk3399_peri_get_clk(priv, ACLK_PERIHP); 1068 break; 1069 case HCLK_PERIHP: 1070 con = readl(&cru->clksel_con[14]); 1071 div = (con & HCLK_PERIHP_DIV_CON_MASK) >> 1072 HCLK_PERIHP_DIV_CON_SHIFT; 1073 parent = rk3399_peri_get_clk(priv, ACLK_PERIHP); 1074 break; 1075 case ACLK_PERILP0: 1076 con = readl(&cru->clksel_con[23]); 1077 div = (con & ACLK_PERILP0_DIV_CON_MASK) >> 1078 ACLK_PERILP0_DIV_CON_SHIFT; 1079 parent = GPLL_HZ; 1080 break; 1081 case HCLK_PERILP0: 1082 con = readl(&cru->clksel_con[23]); 1083 div = (con & HCLK_PERILP0_DIV_CON_MASK) >> 1084 HCLK_PERILP0_DIV_CON_SHIFT; 1085 parent = rk3399_peri_get_clk(priv, ACLK_PERILP0); 1086 break; 1087 case PCLK_PERILP0: 1088 con = readl(&cru->clksel_con[23]); 1089 div = (con & PCLK_PERILP0_DIV_CON_MASK) >> 1090 PCLK_PERILP0_DIV_CON_SHIFT; 1091 parent = rk3399_peri_get_clk(priv, ACLK_PERILP0); 1092 break; 1093 case HCLK_PERILP1: 1094 con = readl(&cru->clksel_con[25]); 1095 div = (con & HCLK_PERILP1_DIV_CON_MASK) >> 1096 HCLK_PERILP1_DIV_CON_SHIFT; 1097 parent = GPLL_HZ; 1098 break; 1099 case PCLK_PERILP1: 1100 con = readl(&cru->clksel_con[25]); 1101 div = (con & PCLK_PERILP1_DIV_CON_MASK) >> 1102 PCLK_PERILP1_DIV_CON_SHIFT; 1103 parent = rk3399_peri_get_clk(priv, HCLK_PERILP1); 1104 break; 1105 default: 1106 return -ENOENT; 1107 } 1108 1109 return DIV_TO_RATE(parent, div); 1110 } 1111 1112 #endif 1113 1114 static ulong rk3399_clk_get_rate(struct clk *clk) 1115 { 1116 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); 1117 ulong rate = 0; 1118 1119 switch (clk->id) { 1120 case PLL_APLLL: 1121 case PLL_APLLB: 1122 case PLL_DPLL: 1123 case PLL_CPLL: 1124 case PLL_GPLL: 1125 case PLL_NPLL: 1126 case PLL_VPLL: 1127 rate = rk3399_pll_get_rate(priv, clk->id); 1128 break; 1129 case HCLK_SDMMC: 1130 case SCLK_SDMMC: 1131 case SCLK_EMMC: 1132 rate = rk3399_mmc_get_clk(priv->cru, clk->id); 1133 break; 1134 case SCLK_I2C1: 1135 case SCLK_I2C2: 1136 case SCLK_I2C3: 1137 case SCLK_I2C5: 1138 case SCLK_I2C6: 1139 case SCLK_I2C7: 1140 rate = rk3399_i2c_get_clk(priv->cru, clk->id); 1141 break; 1142 case SCLK_SPI0...SCLK_SPI5: 1143 rate = rk3399_spi_get_clk(priv->cru, clk->id); 1144 break; 1145 case SCLK_UART0: 1146 case SCLK_UART1: 1147 case SCLK_UART2: 1148 case SCLK_UART3: 1149 return 24000000; 1150 break; 1151 case PCLK_HDMI_CTRL: 1152 break; 1153 case DCLK_VOP0: 1154 case DCLK_VOP1: 1155 break; 1156 case PCLK_EFUSE1024NS: 1157 break; 1158 case SCLK_SARADC: 1159 rate = rk3399_saradc_get_clk(priv->cru); 1160 break; 1161 case SCLK_TSADC: 1162 rate = rk3399_tsadc_get_clk(priv->cru); 1163 break; 1164 #ifndef CONFIG_SPL_BUILD 1165 case SCLK_CRYPTO0: 1166 case SCLK_CRYPTO1: 1167 rate = rk3399_crypto_get_clk(priv, clk->id); 1168 break; 1169 case ACLK_PERIHP: 1170 case HCLK_PERIHP: 1171 case PCLK_PERIHP: 1172 case ACLK_PERILP0: 1173 case HCLK_PERILP0: 1174 case PCLK_PERILP0: 1175 case HCLK_PERILP1: 1176 case PCLK_PERILP1: 1177 rate = rk3399_peri_get_clk(priv, clk->id); 1178 break; 1179 #endif 1180 default: 1181 return -ENOENT; 1182 } 1183 1184 return rate; 1185 } 1186 1187 static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) 1188 { 1189 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); 1190 ulong ret = 0; 1191 1192 switch (clk->id) { 1193 case 0 ... 63: 1194 return 0; 1195 1196 case ACLK_PERIHP: 1197 case HCLK_PERIHP: 1198 case PCLK_PERIHP: 1199 return 0; 1200 1201 case ACLK_PERILP0: 1202 case HCLK_PERILP0: 1203 case PCLK_PERILP0: 1204 return 0; 1205 1206 case ACLK_CCI: 1207 return 0; 1208 1209 case HCLK_PERILP1: 1210 case PCLK_PERILP1: 1211 return 0; 1212 1213 case HCLK_SDMMC: 1214 case SCLK_SDMMC: 1215 case SCLK_EMMC: 1216 ret = rk3399_mmc_set_clk(priv->cru, clk->id, rate); 1217 break; 1218 case SCLK_MAC: 1219 ret = rk3399_gmac_set_clk(priv->cru, rate); 1220 break; 1221 case SCLK_I2C1: 1222 case SCLK_I2C2: 1223 case SCLK_I2C3: 1224 case SCLK_I2C5: 1225 case SCLK_I2C6: 1226 case SCLK_I2C7: 1227 ret = rk3399_i2c_set_clk(priv->cru, clk->id, rate); 1228 break; 1229 case SCLK_SPI0...SCLK_SPI5: 1230 ret = rk3399_spi_set_clk(priv->cru, clk->id, rate); 1231 break; 1232 case PCLK_HDMI_CTRL: 1233 case PCLK_VIO_GRF: 1234 /* the PCLK gates for video are enabled by default */ 1235 break; 1236 case DCLK_VOP0: 1237 case DCLK_VOP1: 1238 ret = rk3399_vop_set_clk(priv->cru, clk->id, rate); 1239 break; 1240 case SCLK_DDRCLK: 1241 ret = rk3399_ddr_set_clk(priv->cru, rate); 1242 break; 1243 case PCLK_EFUSE1024NS: 1244 break; 1245 case SCLK_SARADC: 1246 ret = rk3399_saradc_set_clk(priv->cru, rate); 1247 break; 1248 case SCLK_TSADC: 1249 ret = rk3399_tsadc_set_clk(priv->cru, rate); 1250 break; 1251 #ifndef CONFIG_SPL_BUILD 1252 case SCLK_CRYPTO0: 1253 case SCLK_CRYPTO1: 1254 ret = rk3399_crypto_set_clk(priv, clk->id, rate); 1255 break; 1256 #endif 1257 default: 1258 return -ENOENT; 1259 } 1260 1261 return ret; 1262 } 1263 1264 static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk, struct clk *parent) 1265 { 1266 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); 1267 const char *clock_output_name; 1268 int ret; 1269 1270 /* 1271 * If the requested parent is in the same clock-controller and 1272 * the id is SCLK_MAC ("clk_gmac"), switch to the internal clock. 1273 */ 1274 if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC)) { 1275 debug("%s: switching RGMII to SCLK_MAC\n", __func__); 1276 rk_clrreg(&priv->cru->clksel_con[19], BIT(4)); 1277 return 0; 1278 } 1279 1280 /* 1281 * Otherwise, we need to check the clock-output-names of the 1282 * requested parent to see if the requested id is "clkin_gmac". 1283 */ 1284 ret = dev_read_string_index(parent->dev, "clock-output-names", 1285 parent->id, &clock_output_name); 1286 if (ret < 0) 1287 return -ENODATA; 1288 1289 /* If this is "clkin_gmac", switch to the external clock input */ 1290 if (!strcmp(clock_output_name, "clkin_gmac")) { 1291 debug("%s: switching RGMII to CLKIN\n", __func__); 1292 rk_setreg(&priv->cru->clksel_con[19], BIT(4)); 1293 return 0; 1294 } 1295 1296 return -EINVAL; 1297 } 1298 1299 static int __maybe_unused rk3399_dclk_vop_set_parent(struct clk *clk, 1300 struct clk *parent) 1301 { 1302 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); 1303 void *dclkreg_addr; 1304 1305 switch (clk->id) { 1306 case DCLK_VOP0_DIV: 1307 dclkreg_addr = &priv->cru->clksel_con[49]; 1308 break; 1309 case DCLK_VOP1_DIV: 1310 dclkreg_addr = &priv->cru->clksel_con[50]; 1311 break; 1312 default: 1313 return -EINVAL; 1314 } 1315 if (parent->id == PLL_CPLL) { 1316 rk_clrsetreg(dclkreg_addr, DCLK_VOP_PLL_SEL_MASK, 1317 DCLK_VOP_PLL_SEL_CPLL << DCLK_VOP_PLL_SEL_SHIFT); 1318 } else { 1319 rk_clrsetreg(dclkreg_addr, DCLK_VOP_PLL_SEL_MASK, 1320 DCLK_VOP_PLL_SEL_VPLL << DCLK_VOP_PLL_SEL_SHIFT); 1321 } 1322 1323 return 0; 1324 } 1325 1326 static int __maybe_unused rk3399_clk_set_parent(struct clk *clk, struct clk *parent) 1327 { 1328 switch (clk->id) { 1329 case SCLK_RMII_SRC: 1330 return rk3399_gmac_set_parent(clk, parent); 1331 case DCLK_VOP0_DIV: 1332 case DCLK_VOP1_DIV: 1333 return rk3399_dclk_vop_set_parent(clk, parent); 1334 } 1335 1336 debug("%s: unsupported clk %ld\n", __func__, clk->id); 1337 return -ENOENT; 1338 } 1339 1340 static int rk3399_clk_enable(struct clk *clk) 1341 { 1342 switch (clk->id) { 1343 case HCLK_HOST0: 1344 case HCLK_HOST0_ARB: 1345 case SCLK_USBPHY0_480M_SRC: 1346 case HCLK_HOST1: 1347 case HCLK_HOST1_ARB: 1348 case SCLK_USBPHY1_480M_SRC: 1349 return 0; 1350 } 1351 1352 debug("%s: unsupported clk %ld\n", __func__, clk->id); 1353 return -ENOENT; 1354 } 1355 1356 static struct clk_ops rk3399_clk_ops = { 1357 .get_rate = rk3399_clk_get_rate, 1358 .set_rate = rk3399_clk_set_rate, 1359 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 1360 .set_parent = rk3399_clk_set_parent, 1361 #endif 1362 .enable = rk3399_clk_enable, 1363 }; 1364 1365 static void rkclk_init(struct rk3399_cru *cru) 1366 { 1367 u32 aclk_div; 1368 u32 hclk_div; 1369 u32 pclk_div; 1370 1371 rk3399_configure_cpu(cru, APLL_816_MHZ, CPU_CLUSTER_LITTLE); 1372 1373 /* 1374 * some cru registers changed by bootrom, we'd better reset them to 1375 * reset/default values described in TRM to avoid confusion in kernel. 1376 * Please consider these three lines as a fix of bootrom bug. 1377 */ 1378 if (rkclk_pll_get_rate(&cru->npll_con[0]) != NPLL_HZ) 1379 rkclk_set_pll(&cru->npll_con[0], &npll_init_cfg); 1380 1381 if (rkclk_pll_get_rate(&cru->gpll_con[0]) == GPLL_HZ) 1382 return; 1383 1384 rk_clrsetreg(&cru->clksel_con[12], 0xffff, 0x4101); 1385 rk_clrsetreg(&cru->clksel_con[19], 0xffff, 0x033f); 1386 rk_clrsetreg(&cru->clksel_con[56], 0x0003, 0x0003); 1387 1388 /* configure perihp aclk, hclk, pclk */ 1389 aclk_div = DIV_ROUND_UP(GPLL_HZ, PERIHP_ACLK_HZ) - 1; 1390 1391 hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1; 1392 assert((hclk_div + 1) * PERIHP_HCLK_HZ == 1393 PERIHP_ACLK_HZ && (hclk_div <= 0x3)); 1394 1395 pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1; 1396 assert((pclk_div + 1) * PERIHP_PCLK_HZ == 1397 PERIHP_ACLK_HZ && (pclk_div <= 0x7)); 1398 1399 rk_clrsetreg(&cru->clksel_con[14], 1400 PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK | 1401 ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK, 1402 pclk_div << PCLK_PERIHP_DIV_CON_SHIFT | 1403 hclk_div << HCLK_PERIHP_DIV_CON_SHIFT | 1404 ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT | 1405 aclk_div << ACLK_PERIHP_DIV_CON_SHIFT); 1406 1407 /* configure perilp0 aclk, hclk, pclk */ 1408 aclk_div = DIV_ROUND_UP(GPLL_HZ, PERILP0_ACLK_HZ) - 1; 1409 1410 hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1; 1411 assert((hclk_div + 1) * PERILP0_HCLK_HZ == 1412 PERILP0_ACLK_HZ && (hclk_div <= 0x3)); 1413 1414 pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1; 1415 assert((pclk_div + 1) * PERILP0_PCLK_HZ == 1416 PERILP0_ACLK_HZ && (pclk_div <= 0x7)); 1417 1418 rk_clrsetreg(&cru->clksel_con[23], 1419 PCLK_PERILP0_DIV_CON_MASK | HCLK_PERILP0_DIV_CON_MASK | 1420 ACLK_PERILP0_PLL_SEL_MASK | ACLK_PERILP0_DIV_CON_MASK, 1421 pclk_div << PCLK_PERILP0_DIV_CON_SHIFT | 1422 hclk_div << HCLK_PERILP0_DIV_CON_SHIFT | 1423 ACLK_PERILP0_PLL_SEL_GPLL << ACLK_PERILP0_PLL_SEL_SHIFT | 1424 aclk_div << ACLK_PERILP0_DIV_CON_SHIFT); 1425 1426 /* perilp1 hclk select gpll as source */ 1427 hclk_div = DIV_ROUND_UP(GPLL_HZ, PERILP1_HCLK_HZ) - 1; 1428 assert((hclk_div + 1) * PERILP1_HCLK_HZ == 1429 GPLL_HZ && (hclk_div <= 0x1f)); 1430 1431 pclk_div = PERILP1_HCLK_HZ / PERILP1_PCLK_HZ - 1; 1432 assert((pclk_div + 1) * PERILP1_PCLK_HZ == 1433 PERILP1_HCLK_HZ && (pclk_div <= 0x7)); 1434 1435 rk_clrsetreg(&cru->clksel_con[25], 1436 PCLK_PERILP1_DIV_CON_MASK | HCLK_PERILP1_DIV_CON_MASK | 1437 HCLK_PERILP1_PLL_SEL_MASK, 1438 pclk_div << PCLK_PERILP1_DIV_CON_SHIFT | 1439 hclk_div << HCLK_PERILP1_DIV_CON_SHIFT | 1440 HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT); 1441 1442 rk_clrsetreg(&cru->clksel_con[21], 1443 ACLK_EMMC_PLL_SEL_MASK | ACLK_EMMC_DIV_CON_MASK, 1444 ACLK_EMMC_PLL_SEL_GPLL << ACLK_EMMC_PLL_SEL_SHIFT | 1445 (4 - 1) << ACLK_EMMC_DIV_CON_SHIFT); 1446 rk_clrsetreg(&cru->clksel_con[22], 0x3f << 0, 7 << 0); 1447 1448 rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg); 1449 } 1450 1451 static int rk3399_clk_probe(struct udevice *dev) 1452 { 1453 struct rk3399_clk_priv *priv = dev_get_priv(dev); 1454 1455 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1456 struct rk3399_clk_plat *plat = dev_get_platdata(dev); 1457 1458 priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); 1459 #endif 1460 rkclk_init(priv->cru); 1461 return 0; 1462 } 1463 1464 static int rk3399_clk_ofdata_to_platdata(struct udevice *dev) 1465 { 1466 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 1467 struct rk3399_clk_priv *priv = dev_get_priv(dev); 1468 1469 priv->cru = dev_read_addr_ptr(dev); 1470 #endif 1471 return 0; 1472 } 1473 1474 static int rk3399_clk_bind(struct udevice *dev) 1475 { 1476 int ret; 1477 struct udevice *sys_child, *sf_child; 1478 struct sysreset_reg *priv; 1479 struct softreset_reg *sf_priv; 1480 1481 /* The reset driver does not have a device node, so bind it here */ 1482 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", 1483 &sys_child); 1484 if (ret) { 1485 debug("Warning: No sysreset driver: ret=%d\n", ret); 1486 } else { 1487 priv = malloc(sizeof(struct sysreset_reg)); 1488 priv->glb_srst_fst_value = offsetof(struct rk3399_cru, 1489 glb_srst_fst_value); 1490 priv->glb_srst_snd_value = offsetof(struct rk3399_cru, 1491 glb_srst_snd_value); 1492 sys_child->priv = priv; 1493 } 1494 1495 ret = device_bind_driver_to_node(dev, "rockchip_reset", "reset", 1496 dev_ofnode(dev), &sf_child); 1497 if (ret) { 1498 debug("Warning: No rockchip reset driver: ret=%d\n", ret); 1499 } else { 1500 sf_priv = malloc(sizeof(struct softreset_reg)); 1501 sf_priv->sf_reset_offset = offsetof(struct rk3399_cru, 1502 softrst_con[0]); 1503 sf_priv->sf_reset_num = 21; 1504 sf_child->priv = sf_priv; 1505 } 1506 1507 return 0; 1508 } 1509 1510 static const struct udevice_id rk3399_clk_ids[] = { 1511 { .compatible = "rockchip,rk3399-cru" }, 1512 { } 1513 }; 1514 1515 U_BOOT_DRIVER(clk_rk3399) = { 1516 .name = "rockchip_rk3399_cru", 1517 .id = UCLASS_CLK, 1518 .of_match = rk3399_clk_ids, 1519 .priv_auto_alloc_size = sizeof(struct rk3399_clk_priv), 1520 .ofdata_to_platdata = rk3399_clk_ofdata_to_platdata, 1521 .ops = &rk3399_clk_ops, 1522 .bind = rk3399_clk_bind, 1523 .probe = rk3399_clk_probe, 1524 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1525 .platdata_auto_alloc_size = sizeof(struct rk3399_clk_plat), 1526 #endif 1527 }; 1528 1529 static ulong rk3399_i2c_get_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id) 1530 { 1531 u32 div, con; 1532 1533 switch (clk_id) { 1534 case SCLK_I2C0_PMU: 1535 con = readl(&pmucru->pmucru_clksel[2]); 1536 div = I2C_CLK_DIV_VALUE(con, 0); 1537 break; 1538 case SCLK_I2C4_PMU: 1539 con = readl(&pmucru->pmucru_clksel[3]); 1540 div = I2C_CLK_DIV_VALUE(con, 4); 1541 break; 1542 case SCLK_I2C8_PMU: 1543 con = readl(&pmucru->pmucru_clksel[2]); 1544 div = I2C_CLK_DIV_VALUE(con, 8); 1545 break; 1546 default: 1547 printf("do not support this i2c bus\n"); 1548 return -EINVAL; 1549 } 1550 1551 return DIV_TO_RATE(PPLL_HZ, div); 1552 } 1553 1554 static ulong rk3399_i2c_set_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id, 1555 uint hz) 1556 { 1557 int src_clk_div; 1558 1559 src_clk_div = PPLL_HZ / hz; 1560 assert(src_clk_div - 1 < 127); 1561 1562 switch (clk_id) { 1563 case SCLK_I2C0_PMU: 1564 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(0), 1565 I2C_PMUCLK_REG_VALUE(0, src_clk_div)); 1566 break; 1567 case SCLK_I2C4_PMU: 1568 rk_clrsetreg(&pmucru->pmucru_clksel[3], I2C_PMUCLK_REG_MASK(4), 1569 I2C_PMUCLK_REG_VALUE(4, src_clk_div)); 1570 break; 1571 case SCLK_I2C8_PMU: 1572 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(8), 1573 I2C_PMUCLK_REG_VALUE(8, src_clk_div)); 1574 break; 1575 default: 1576 printf("do not support this i2c bus\n"); 1577 return -EINVAL; 1578 } 1579 1580 return DIV_TO_RATE(PPLL_HZ, src_clk_div); 1581 } 1582 1583 static ulong rk3399_pwm_get_clk(struct rk3399_pmucru *pmucru) 1584 { 1585 u32 div, con; 1586 1587 /* PWM closk rate is same as pclk_pmu */ 1588 con = readl(&pmucru->pmucru_clksel[0]); 1589 div = con & PMU_PCLK_DIV_CON_MASK; 1590 1591 return DIV_TO_RATE(PPLL_HZ, div); 1592 } 1593 1594 static ulong rk3399_pmuclk_get_rate(struct clk *clk) 1595 { 1596 struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev); 1597 ulong rate = 0; 1598 1599 switch (clk->id) { 1600 case PCLK_RKPWM_PMU: 1601 rate = rk3399_pwm_get_clk(priv->pmucru); 1602 break; 1603 case SCLK_I2C0_PMU: 1604 case SCLK_I2C4_PMU: 1605 case SCLK_I2C8_PMU: 1606 rate = rk3399_i2c_get_pmuclk(priv->pmucru, clk->id); 1607 break; 1608 case SCLK_UART4_PMU: 1609 rate = 24000000; 1610 break; 1611 default: 1612 return -ENOENT; 1613 } 1614 1615 return rate; 1616 } 1617 1618 static ulong rk3399_pmuclk_set_rate(struct clk *clk, ulong rate) 1619 { 1620 struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev); 1621 ulong ret = 0; 1622 1623 switch (clk->id) { 1624 case SCLK_I2C0_PMU: 1625 case SCLK_I2C4_PMU: 1626 case SCLK_I2C8_PMU: 1627 ret = rk3399_i2c_set_pmuclk(priv->pmucru, clk->id, rate); 1628 break; 1629 default: 1630 return -ENOENT; 1631 } 1632 1633 return ret; 1634 } 1635 1636 static struct clk_ops rk3399_pmuclk_ops = { 1637 .get_rate = rk3399_pmuclk_get_rate, 1638 .set_rate = rk3399_pmuclk_set_rate, 1639 }; 1640 1641 #ifndef CONFIG_SPL_BUILD 1642 static void pmuclk_init(struct rk3399_pmucru *pmucru) 1643 { 1644 u32 pclk_div; 1645 1646 /* configure pmu pll(ppll) */ 1647 rkclk_set_pll(&pmucru->ppll_con[0], &ppll_init_cfg); 1648 1649 /* configure pmu pclk */ 1650 pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1; 1651 rk_clrsetreg(&pmucru->pmucru_clksel[0], 1652 PMU_PCLK_DIV_CON_MASK, 1653 pclk_div << PMU_PCLK_DIV_CON_SHIFT); 1654 } 1655 #endif 1656 1657 static int rk3399_pmuclk_probe(struct udevice *dev) 1658 { 1659 #if CONFIG_IS_ENABLED(OF_PLATDATA) || !defined(CONFIG_SPL_BUILD) 1660 struct rk3399_pmuclk_priv *priv = dev_get_priv(dev); 1661 #endif 1662 1663 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1664 struct rk3399_pmuclk_plat *plat = dev_get_platdata(dev); 1665 1666 priv->pmucru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); 1667 #endif 1668 1669 #ifndef CONFIG_SPL_BUILD 1670 pmuclk_init(priv->pmucru); 1671 #endif 1672 return 0; 1673 } 1674 1675 static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev) 1676 { 1677 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 1678 struct rk3399_pmuclk_priv *priv = dev_get_priv(dev); 1679 1680 priv->pmucru = dev_read_addr_ptr(dev); 1681 #endif 1682 return 0; 1683 } 1684 1685 static int rk3399_pmuclk_bind(struct udevice *dev) 1686 { 1687 int ret = 0; 1688 struct udevice *sf_child; 1689 struct softreset_reg *sf_priv; 1690 1691 ret = device_bind_driver_to_node(dev, "rockchip_reset", 1692 "reset", dev_ofnode(dev), 1693 &sf_child); 1694 if (ret) { 1695 debug("Warning: No rockchip reset driver: ret=%d\n", ret); 1696 } else { 1697 sf_priv = malloc(sizeof(struct softreset_reg)); 1698 sf_priv->sf_reset_offset = offsetof(struct rk3399_pmucru, 1699 pmucru_softrst_con[0]); 1700 sf_priv->sf_reset_num = 2; 1701 sf_child->priv = sf_priv; 1702 } 1703 1704 return 0; 1705 } 1706 1707 static const struct udevice_id rk3399_pmuclk_ids[] = { 1708 { .compatible = "rockchip,rk3399-pmucru" }, 1709 { } 1710 }; 1711 1712 U_BOOT_DRIVER(rockchip_rk3399_pmuclk) = { 1713 .name = "rockchip_rk3399_pmucru", 1714 .id = UCLASS_CLK, 1715 .of_match = rk3399_pmuclk_ids, 1716 .priv_auto_alloc_size = sizeof(struct rk3399_pmuclk_priv), 1717 .ofdata_to_platdata = rk3399_pmuclk_ofdata_to_platdata, 1718 .ops = &rk3399_pmuclk_ops, 1719 .probe = rk3399_pmuclk_probe, 1720 .bind = rk3399_pmuclk_bind, 1721 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1722 .platdata_auto_alloc_size = sizeof(struct rk3399_pmuclk_plat), 1723 #endif 1724 }; 1725 1726 #ifndef CONFIG_SPL_BUILD 1727 /** 1728 * soc_clk_dump() - Print clock frequencies 1729 * Returns zero on success 1730 * 1731 * Implementation for the clk dump command. 1732 */ 1733 int soc_clk_dump(void) 1734 { 1735 struct udevice *cru_dev, *pmucru_dev; 1736 const struct rk3399_clk_info *clk_dump; 1737 struct clk clk; 1738 unsigned long clk_count = ARRAY_SIZE(clks_dump); 1739 unsigned long rate; 1740 int i, ret; 1741 1742 ret = uclass_get_device_by_driver(UCLASS_CLK, 1743 DM_GET_DRIVER(clk_rk3399), 1744 &cru_dev); 1745 if (ret) { 1746 printf("%s failed to get cru device\n", __func__); 1747 return ret; 1748 } 1749 1750 ret = uclass_get_device_by_driver(UCLASS_CLK, 1751 DM_GET_DRIVER(rockchip_rk3399_pmuclk), 1752 &pmucru_dev); 1753 if (ret) { 1754 printf("%s failed to get pmucru device\n", __func__); 1755 return ret; 1756 } 1757 1758 printf("CLK:\n"); 1759 for (i = 0; i < clk_count; i++) { 1760 clk_dump = &clks_dump[i]; 1761 if (clk_dump->name) { 1762 clk.id = clk_dump->id; 1763 if (clk_dump->is_cru) 1764 ret = clk_request(cru_dev, &clk); 1765 else 1766 ret = clk_request(pmucru_dev, &clk); 1767 if (ret < 0) 1768 return ret; 1769 1770 rate = clk_get_rate(&clk); 1771 clk_free(&clk); 1772 if (i == 0) { 1773 if (rate < 0) 1774 printf("%s %s\n", clk_dump->name, 1775 "unknown"); 1776 else 1777 printf("%s %lu KHz\n", clk_dump->name, 1778 rate / 1000); 1779 } else { 1780 if (rate < 0) 1781 printf("%s %s\n", clk_dump->name, 1782 "unknown"); 1783 else 1784 printf("%s %lu KHz\n", clk_dump->name, 1785 rate / 1000); 1786 } 1787 } 1788 } 1789 1790 return 0; 1791 } 1792 #endif 1793