1 /* 2 * (C) Copyright 2015 Google, Inc 3 * (C) 2017 Theobroma Systems Design und Consulting GmbH 4 * 5 * SPDX-License-Identifier: GPL-2.0 6 */ 7 8 #include <common.h> 9 #include <clk-uclass.h> 10 #include <dm.h> 11 #include <dt-structs.h> 12 #include <errno.h> 13 #include <mapmem.h> 14 #include <syscon.h> 15 #include <bitfield.h> 16 #include <asm/io.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/cru_rk3399.h> 19 #include <asm/arch/hardware.h> 20 #include <dm/lists.h> 21 #include <dt-bindings/clock/rk3399-cru.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #if CONFIG_IS_ENABLED(OF_PLATDATA) 26 struct rk3399_clk_plat { 27 struct dtd_rockchip_rk3399_cru dtd; 28 }; 29 30 struct rk3399_pmuclk_plat { 31 struct dtd_rockchip_rk3399_pmucru dtd; 32 }; 33 #endif 34 35 struct pll_div { 36 u32 refdiv; 37 u32 fbdiv; 38 u32 postdiv1; 39 u32 postdiv2; 40 u32 frac; 41 u32 freq; 42 }; 43 44 #define RATE_TO_DIV(input_rate, output_rate) \ 45 ((input_rate) / (output_rate) - 1); 46 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) 47 48 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ 49 .refdiv = _refdiv,\ 50 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\ 51 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2, .freq = hz}; 52 53 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 3, 1); 54 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2); 55 static const struct pll_div npll_init_cfg = PLL_DIVISORS(NPLL_HZ, 1, 2, 2); 56 #if !defined(CONFIG_SPL_BUILD) 57 static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1); 58 #endif 59 static const struct pll_div apll_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1); 60 static const struct pll_div apll_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1); 61 62 static const struct pll_div *apll_cfgs[] = { 63 [APLL_1600_MHZ] = &apll_1600_cfg, 64 [APLL_600_MHZ] = &apll_600_cfg, 65 }; 66 67 enum { 68 /* PLL_CON0 */ 69 PLL_FBDIV_MASK = 0xfff, 70 PLL_FBDIV_SHIFT = 0, 71 72 /* PLL_CON1 */ 73 PLL_POSTDIV2_SHIFT = 12, 74 PLL_POSTDIV2_MASK = 0x7 << PLL_POSTDIV2_SHIFT, 75 PLL_POSTDIV1_SHIFT = 8, 76 PLL_POSTDIV1_MASK = 0x7 << PLL_POSTDIV1_SHIFT, 77 PLL_REFDIV_MASK = 0x3f, 78 PLL_REFDIV_SHIFT = 0, 79 80 /* PLL_CON2 */ 81 PLL_LOCK_STATUS_SHIFT = 31, 82 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, 83 PLL_FRACDIV_MASK = 0xffffff, 84 PLL_FRACDIV_SHIFT = 0, 85 86 /* PLL_CON3 */ 87 PLL_MODE_SHIFT = 8, 88 PLL_MODE_MASK = 3 << PLL_MODE_SHIFT, 89 PLL_MODE_SLOW = 0, 90 PLL_MODE_NORM, 91 PLL_MODE_DEEP, 92 PLL_DSMPD_SHIFT = 3, 93 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, 94 PLL_INTEGER_MODE = 1, 95 96 /* PMUCRU_CLKSEL_CON0 */ 97 PMU_PCLK_DIV_CON_MASK = 0x1f, 98 PMU_PCLK_DIV_CON_SHIFT = 0, 99 100 /* PMUCRU_CLKSEL_CON1 */ 101 SPI3_PLL_SEL_SHIFT = 7, 102 SPI3_PLL_SEL_MASK = 1 << SPI3_PLL_SEL_SHIFT, 103 SPI3_PLL_SEL_24M = 0, 104 SPI3_PLL_SEL_PPLL = 1, 105 SPI3_DIV_CON_SHIFT = 0x0, 106 SPI3_DIV_CON_MASK = 0x7f, 107 108 /* PMUCRU_CLKSEL_CON2 */ 109 I2C_DIV_CON_MASK = 0x7f, 110 CLK_I2C8_DIV_CON_SHIFT = 8, 111 CLK_I2C0_DIV_CON_SHIFT = 0, 112 113 /* PMUCRU_CLKSEL_CON3 */ 114 CLK_I2C4_DIV_CON_SHIFT = 0, 115 116 /* CLKSEL_CON0 / CLKSEL_CON2 */ 117 ACLKM_CORE_DIV_CON_MASK = 0x1f, 118 ACLKM_CORE_DIV_CON_SHIFT = 8, 119 CLK_CORE_PLL_SEL_MASK = 3, 120 CLK_CORE_PLL_SEL_SHIFT = 6, 121 CLK_CORE_PLL_SEL_ALPLL = 0x0, 122 CLK_CORE_PLL_SEL_ABPLL = 0x1, 123 CLK_CORE_PLL_SEL_DPLL = 0x10, 124 CLK_CORE_PLL_SEL_GPLL = 0x11, 125 CLK_CORE_DIV_MASK = 0x1f, 126 CLK_CORE_DIV_SHIFT = 0, 127 128 /* CLKSEL_CON1 / CLKSEL_CON3 */ 129 PCLK_DBG_DIV_MASK = 0x1f, 130 PCLK_DBG_DIV_SHIFT = 0x8, 131 ATCLK_CORE_DIV_MASK = 0x1f, 132 ATCLK_CORE_DIV_SHIFT = 0, 133 134 /* CLKSEL_CON14 */ 135 PCLK_PERIHP_DIV_CON_SHIFT = 12, 136 PCLK_PERIHP_DIV_CON_MASK = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT, 137 HCLK_PERIHP_DIV_CON_SHIFT = 8, 138 HCLK_PERIHP_DIV_CON_MASK = 3 << HCLK_PERIHP_DIV_CON_SHIFT, 139 ACLK_PERIHP_PLL_SEL_SHIFT = 7, 140 ACLK_PERIHP_PLL_SEL_MASK = 1 << ACLK_PERIHP_PLL_SEL_SHIFT, 141 ACLK_PERIHP_PLL_SEL_CPLL = 0, 142 ACLK_PERIHP_PLL_SEL_GPLL = 1, 143 ACLK_PERIHP_DIV_CON_SHIFT = 0, 144 ACLK_PERIHP_DIV_CON_MASK = 0x1f, 145 146 /* CLKSEL_CON21 */ 147 ACLK_EMMC_PLL_SEL_SHIFT = 7, 148 ACLK_EMMC_PLL_SEL_MASK = 0x1 << ACLK_EMMC_PLL_SEL_SHIFT, 149 ACLK_EMMC_PLL_SEL_GPLL = 0x1, 150 ACLK_EMMC_DIV_CON_SHIFT = 0, 151 ACLK_EMMC_DIV_CON_MASK = 0x1f, 152 153 /* CLKSEL_CON22 */ 154 CLK_EMMC_PLL_SHIFT = 8, 155 CLK_EMMC_PLL_MASK = 0x7 << CLK_EMMC_PLL_SHIFT, 156 CLK_EMMC_PLL_SEL_GPLL = 0x1, 157 CLK_EMMC_PLL_SEL_24M = 0x5, 158 CLK_EMMC_DIV_CON_SHIFT = 0, 159 CLK_EMMC_DIV_CON_MASK = 0x7f << CLK_EMMC_DIV_CON_SHIFT, 160 161 /* CLKSEL_CON23 */ 162 PCLK_PERILP0_DIV_CON_SHIFT = 12, 163 PCLK_PERILP0_DIV_CON_MASK = 0x7 << PCLK_PERILP0_DIV_CON_SHIFT, 164 HCLK_PERILP0_DIV_CON_SHIFT = 8, 165 HCLK_PERILP0_DIV_CON_MASK = 3 << HCLK_PERILP0_DIV_CON_SHIFT, 166 ACLK_PERILP0_PLL_SEL_SHIFT = 7, 167 ACLK_PERILP0_PLL_SEL_MASK = 1 << ACLK_PERILP0_PLL_SEL_SHIFT, 168 ACLK_PERILP0_PLL_SEL_CPLL = 0, 169 ACLK_PERILP0_PLL_SEL_GPLL = 1, 170 ACLK_PERILP0_DIV_CON_SHIFT = 0, 171 ACLK_PERILP0_DIV_CON_MASK = 0x1f, 172 173 /* CLKSEL_CON25 */ 174 PCLK_PERILP1_DIV_CON_SHIFT = 8, 175 PCLK_PERILP1_DIV_CON_MASK = 0x7 << PCLK_PERILP1_DIV_CON_SHIFT, 176 HCLK_PERILP1_PLL_SEL_SHIFT = 7, 177 HCLK_PERILP1_PLL_SEL_MASK = 1 << HCLK_PERILP1_PLL_SEL_SHIFT, 178 HCLK_PERILP1_PLL_SEL_CPLL = 0, 179 HCLK_PERILP1_PLL_SEL_GPLL = 1, 180 HCLK_PERILP1_DIV_CON_SHIFT = 0, 181 HCLK_PERILP1_DIV_CON_MASK = 0x1f, 182 183 /* CLKSEL_CON26 */ 184 CLK_SARADC_DIV_CON_SHIFT = 8, 185 CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8), 186 CLK_SARADC_DIV_CON_WIDTH = 8, 187 188 /* CLKSEL_CON27 */ 189 CLK_TSADC_SEL_X24M = 0x0, 190 CLK_TSADC_SEL_SHIFT = 15, 191 CLK_TSADC_SEL_MASK = 1 << CLK_TSADC_SEL_SHIFT, 192 CLK_TSADC_DIV_CON_SHIFT = 0, 193 CLK_TSADC_DIV_CON_MASK = 0x3ff, 194 195 /* CLKSEL_CON47 & CLKSEL_CON48 */ 196 ACLK_VOP_PLL_SEL_SHIFT = 6, 197 ACLK_VOP_PLL_SEL_MASK = 0x3 << ACLK_VOP_PLL_SEL_SHIFT, 198 ACLK_VOP_PLL_SEL_CPLL = 0x1, 199 ACLK_VOP_PLL_SEL_GPLL = 0x2, 200 ACLK_VOP_DIV_CON_SHIFT = 0, 201 ACLK_VOP_DIV_CON_MASK = 0x1f << ACLK_VOP_DIV_CON_SHIFT, 202 203 /* CLKSEL_CON49 & CLKSEL_CON50 */ 204 DCLK_VOP_DCLK_SEL_SHIFT = 11, 205 DCLK_VOP_DCLK_SEL_MASK = 1 << DCLK_VOP_DCLK_SEL_SHIFT, 206 DCLK_VOP_DCLK_SEL_DIVOUT = 0, 207 DCLK_VOP_PLL_SEL_SHIFT = 8, 208 DCLK_VOP_PLL_SEL_MASK = 3 << DCLK_VOP_PLL_SEL_SHIFT, 209 DCLK_VOP_PLL_SEL_VPLL = 0, 210 DCLK_VOP_PLL_SEL_CPLL = 1, 211 DCLK_VOP_DIV_CON_MASK = 0xff, 212 DCLK_VOP_DIV_CON_SHIFT = 0, 213 214 /* CLKSEL_CON58 */ 215 CLK_SPI_PLL_SEL_WIDTH = 1, 216 CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1), 217 CLK_SPI_PLL_SEL_CPLL = 0, 218 CLK_SPI_PLL_SEL_GPLL = 1, 219 CLK_SPI_PLL_DIV_CON_WIDTH = 7, 220 CLK_SPI_PLL_DIV_CON_MASK = ((1 << CLK_SPI_PLL_DIV_CON_WIDTH) - 1), 221 222 CLK_SPI5_PLL_DIV_CON_SHIFT = 8, 223 CLK_SPI5_PLL_SEL_SHIFT = 15, 224 225 /* CLKSEL_CON59 */ 226 CLK_SPI1_PLL_SEL_SHIFT = 15, 227 CLK_SPI1_PLL_DIV_CON_SHIFT = 8, 228 CLK_SPI0_PLL_SEL_SHIFT = 7, 229 CLK_SPI0_PLL_DIV_CON_SHIFT = 0, 230 231 /* CLKSEL_CON60 */ 232 CLK_SPI4_PLL_SEL_SHIFT = 15, 233 CLK_SPI4_PLL_DIV_CON_SHIFT = 8, 234 CLK_SPI2_PLL_SEL_SHIFT = 7, 235 CLK_SPI2_PLL_DIV_CON_SHIFT = 0, 236 237 /* CLKSEL_CON61 */ 238 CLK_I2C_PLL_SEL_MASK = 1, 239 CLK_I2C_PLL_SEL_CPLL = 0, 240 CLK_I2C_PLL_SEL_GPLL = 1, 241 CLK_I2C5_PLL_SEL_SHIFT = 15, 242 CLK_I2C5_DIV_CON_SHIFT = 8, 243 CLK_I2C1_PLL_SEL_SHIFT = 7, 244 CLK_I2C1_DIV_CON_SHIFT = 0, 245 246 /* CLKSEL_CON62 */ 247 CLK_I2C6_PLL_SEL_SHIFT = 15, 248 CLK_I2C6_DIV_CON_SHIFT = 8, 249 CLK_I2C2_PLL_SEL_SHIFT = 7, 250 CLK_I2C2_DIV_CON_SHIFT = 0, 251 252 /* CLKSEL_CON63 */ 253 CLK_I2C7_PLL_SEL_SHIFT = 15, 254 CLK_I2C7_DIV_CON_SHIFT = 8, 255 CLK_I2C3_PLL_SEL_SHIFT = 7, 256 CLK_I2C3_DIV_CON_SHIFT = 0, 257 258 /* CRU_SOFTRST_CON4 */ 259 RESETN_DDR0_REQ_SHIFT = 8, 260 RESETN_DDR0_REQ_MASK = 1 << RESETN_DDR0_REQ_SHIFT, 261 RESETN_DDRPHY0_REQ_SHIFT = 9, 262 RESETN_DDRPHY0_REQ_MASK = 1 << RESETN_DDRPHY0_REQ_SHIFT, 263 RESETN_DDR1_REQ_SHIFT = 12, 264 RESETN_DDR1_REQ_MASK = 1 << RESETN_DDR1_REQ_SHIFT, 265 RESETN_DDRPHY1_REQ_SHIFT = 13, 266 RESETN_DDRPHY1_REQ_MASK = 1 << RESETN_DDRPHY1_REQ_SHIFT, 267 }; 268 269 #define VCO_MAX_KHZ (3200 * (MHz / KHz)) 270 #define VCO_MIN_KHZ (800 * (MHz / KHz)) 271 #define OUTPUT_MAX_KHZ (3200 * (MHz / KHz)) 272 #define OUTPUT_MIN_KHZ (16 * (MHz / KHz)) 273 274 /* 275 * the div restructions of pll in integer mode, these are defined in 276 * * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0 277 */ 278 #define PLL_DIV_MIN 16 279 #define PLL_DIV_MAX 3200 280 281 /* 282 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63): 283 * Formulas also embedded within the Fractional PLL Verilog model: 284 * If DSMPD = 1 (DSM is disabled, "integer mode") 285 * FOUTVCO = FREF / REFDIV * FBDIV 286 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2 287 * Where: 288 * FOUTVCO = Fractional PLL non-divided output frequency 289 * FOUTPOSTDIV = Fractional PLL divided output frequency 290 * (output of second post divider) 291 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input) 292 * REFDIV = Fractional PLL input reference clock divider 293 * FBDIV = Integer value programmed into feedback divide 294 * 295 */ 296 297 static uint32_t rkclk_pll_get_rate(u32 *pll_con) 298 { 299 u32 refdiv, fbdiv, postdiv1, postdiv2; 300 u32 con; 301 302 con = readl(&pll_con[3]); 303 switch ((con & PLL_MODE_MASK) >> PLL_MODE_SHIFT) { 304 case PLL_MODE_SLOW: 305 return OSC_HZ; 306 case PLL_MODE_NORM: 307 /* normal mode */ 308 con = readl(&pll_con[0]); 309 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; 310 con = readl(&pll_con[1]); 311 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; 312 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; 313 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; 314 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; 315 case PLL_MODE_DEEP: 316 default: 317 return 32768; 318 } 319 } 320 321 static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div) 322 { 323 /* All 8 PLLs have same VCO and output frequency range restrictions. */ 324 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; 325 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2; 326 327 debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, " 328 "postdiv2=%d, vco=%u khz, output=%u khz\n", 329 pll_con, div->fbdiv, div->refdiv, div->postdiv1, 330 div->postdiv2, vco_khz, output_khz); 331 assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ && 332 output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ && 333 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); 334 335 /* 336 * When power on or changing PLL setting, 337 * we must force PLL into slow mode to ensure output stable clock. 338 */ 339 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK, 340 PLL_MODE_SLOW << PLL_MODE_SHIFT); 341 342 /* use integer mode */ 343 rk_clrsetreg(&pll_con[3], PLL_DSMPD_MASK, 344 PLL_INTEGER_MODE << PLL_DSMPD_SHIFT); 345 346 rk_clrsetreg(&pll_con[0], PLL_FBDIV_MASK, 347 div->fbdiv << PLL_FBDIV_SHIFT); 348 rk_clrsetreg(&pll_con[1], 349 PLL_POSTDIV2_MASK | PLL_POSTDIV1_MASK | 350 PLL_REFDIV_MASK | PLL_REFDIV_SHIFT, 351 (div->postdiv2 << PLL_POSTDIV2_SHIFT) | 352 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | 353 (div->refdiv << PLL_REFDIV_SHIFT)); 354 355 /* waiting for pll lock */ 356 while (!(readl(&pll_con[2]) & (1 << PLL_LOCK_STATUS_SHIFT))) 357 udelay(1); 358 359 /* pll enter normal mode */ 360 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK, 361 PLL_MODE_NORM << PLL_MODE_SHIFT); 362 } 363 364 static ulong rk3399_pll_get_rate(struct rk3399_clk_priv *priv, 365 enum rk3399_pll_id pll_id) 366 { 367 struct rk3399_cru *cru = priv->cru; 368 u32 *pll_con; 369 370 switch (pll_id) { 371 case PLL_APLLL: 372 pll_con = &cru->apll_l_con[0]; 373 break; 374 case PLL_APLLB: 375 pll_con = &cru->apll_b_con[0]; 376 break; 377 case PLL_DPLL: 378 pll_con = &cru->dpll_con[0]; 379 break; 380 case PLL_CPLL: 381 pll_con = &cru->cpll_con[0]; 382 break; 383 case PLL_GPLL: 384 pll_con = &cru->gpll_con[0]; 385 break; 386 case PLL_NPLL: 387 pll_con = &cru->npll_con[0]; 388 break; 389 case PLL_VPLL: 390 pll_con = &cru->vpll_con[0]; 391 break; 392 default: 393 pll_con = &cru->vpll_con[0]; 394 break; 395 } 396 397 return rkclk_pll_get_rate(pll_con); 398 } 399 400 static int pll_para_config(u32 freq_hz, struct pll_div *div) 401 { 402 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; 403 u32 postdiv1, postdiv2 = 1; 404 u32 fref_khz; 405 u32 diff_khz, best_diff_khz; 406 const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16; 407 const u32 max_postdiv1 = 7, max_postdiv2 = 7; 408 u32 vco_khz; 409 u32 freq_khz = freq_hz / KHz; 410 411 if (!freq_hz) { 412 printf("%s: the frequency can't be 0 Hz\n", __func__); 413 return -1; 414 } 415 416 postdiv1 = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz); 417 if (postdiv1 > max_postdiv1) { 418 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); 419 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); 420 } 421 422 vco_khz = freq_khz * postdiv1 * postdiv2; 423 424 if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || 425 postdiv2 > max_postdiv2) { 426 printf("%s: Cannot find out a supported VCO" 427 " for Frequency (%uHz).\n", __func__, freq_hz); 428 return -1; 429 } 430 431 div->postdiv1 = postdiv1; 432 div->postdiv2 = postdiv2; 433 434 best_diff_khz = vco_khz; 435 for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) { 436 fref_khz = ref_khz / refdiv; 437 438 fbdiv = vco_khz / fref_khz; 439 if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv)) 440 continue; 441 diff_khz = vco_khz - fbdiv * fref_khz; 442 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) { 443 fbdiv++; 444 diff_khz = fref_khz - diff_khz; 445 } 446 447 if (diff_khz >= best_diff_khz) 448 continue; 449 450 best_diff_khz = diff_khz; 451 div->refdiv = refdiv; 452 div->fbdiv = fbdiv; 453 } 454 455 if (best_diff_khz > 4 * (MHz/KHz)) { 456 printf("%s: Failed to match output frequency %u, " 457 "difference is %u Hz,exceed 4MHZ\n", __func__, freq_hz, 458 best_diff_khz * KHz); 459 return -1; 460 } 461 return 0; 462 } 463 464 void rk3399_configure_cpu(struct rk3399_cru *cru, 465 enum apll_frequencies freq, 466 enum cpu_cluster cluster) 467 { 468 u32 aclkm_div; 469 u32 pclk_dbg_div; 470 u32 atclk_div, apll_hz; 471 int con_base, parent; 472 u32 *pll_con; 473 474 switch (cluster) { 475 case CPU_CLUSTER_LITTLE: 476 con_base = 0; 477 parent = CLK_CORE_PLL_SEL_ALPLL; 478 pll_con = &cru->apll_l_con[0]; 479 break; 480 case CPU_CLUSTER_BIG: 481 default: 482 con_base = 2; 483 parent = CLK_CORE_PLL_SEL_ABPLL; 484 pll_con = &cru->apll_b_con[0]; 485 break; 486 } 487 488 apll_hz = apll_cfgs[freq]->freq; 489 rkclk_set_pll(pll_con, apll_cfgs[freq]); 490 491 aclkm_div = apll_hz / ACLKM_CORE_HZ - 1; 492 assert((aclkm_div + 1) * ACLKM_CORE_HZ == apll_hz && 493 aclkm_div < 0x1f); 494 495 pclk_dbg_div = apll_hz / PCLK_DBG_HZ - 1; 496 assert((pclk_dbg_div + 1) * PCLK_DBG_HZ == apll_hz && 497 pclk_dbg_div < 0x1f); 498 499 atclk_div = apll_hz / ATCLK_CORE_HZ - 1; 500 assert((atclk_div + 1) * ATCLK_CORE_HZ == apll_hz && 501 atclk_div < 0x1f); 502 503 rk_clrsetreg(&cru->clksel_con[con_base], 504 ACLKM_CORE_DIV_CON_MASK | CLK_CORE_PLL_SEL_MASK | 505 CLK_CORE_DIV_MASK, 506 aclkm_div << ACLKM_CORE_DIV_CON_SHIFT | 507 parent << CLK_CORE_PLL_SEL_SHIFT | 508 0 << CLK_CORE_DIV_SHIFT); 509 510 rk_clrsetreg(&cru->clksel_con[con_base + 1], 511 PCLK_DBG_DIV_MASK | ATCLK_CORE_DIV_MASK, 512 pclk_dbg_div << PCLK_DBG_DIV_SHIFT | 513 atclk_div << ATCLK_CORE_DIV_SHIFT); 514 } 515 #define I2C_CLK_REG_MASK(bus) \ 516 (I2C_DIV_CON_MASK << \ 517 CLK_I2C ##bus## _DIV_CON_SHIFT | \ 518 CLK_I2C_PLL_SEL_MASK << \ 519 CLK_I2C ##bus## _PLL_SEL_SHIFT) 520 521 #define I2C_CLK_REG_VALUE(bus, clk_div) \ 522 ((clk_div - 1) << \ 523 CLK_I2C ##bus## _DIV_CON_SHIFT | \ 524 CLK_I2C_PLL_SEL_GPLL << \ 525 CLK_I2C ##bus## _PLL_SEL_SHIFT) 526 527 #define I2C_CLK_DIV_VALUE(con, bus) \ 528 (con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & \ 529 I2C_DIV_CON_MASK; 530 531 #define I2C_PMUCLK_REG_MASK(bus) \ 532 (I2C_DIV_CON_MASK << \ 533 CLK_I2C ##bus## _DIV_CON_SHIFT) 534 535 #define I2C_PMUCLK_REG_VALUE(bus, clk_div) \ 536 ((clk_div - 1) << \ 537 CLK_I2C ##bus## _DIV_CON_SHIFT) 538 539 static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id) 540 { 541 u32 div, con; 542 543 switch (clk_id) { 544 case SCLK_I2C1: 545 con = readl(&cru->clksel_con[61]); 546 div = I2C_CLK_DIV_VALUE(con, 1); 547 break; 548 case SCLK_I2C2: 549 con = readl(&cru->clksel_con[62]); 550 div = I2C_CLK_DIV_VALUE(con, 2); 551 break; 552 case SCLK_I2C3: 553 con = readl(&cru->clksel_con[63]); 554 div = I2C_CLK_DIV_VALUE(con, 3); 555 break; 556 case SCLK_I2C5: 557 con = readl(&cru->clksel_con[61]); 558 div = I2C_CLK_DIV_VALUE(con, 5); 559 break; 560 case SCLK_I2C6: 561 con = readl(&cru->clksel_con[62]); 562 div = I2C_CLK_DIV_VALUE(con, 6); 563 break; 564 case SCLK_I2C7: 565 con = readl(&cru->clksel_con[63]); 566 div = I2C_CLK_DIV_VALUE(con, 7); 567 break; 568 default: 569 printf("do not support this i2c bus\n"); 570 return -EINVAL; 571 } 572 573 return DIV_TO_RATE(GPLL_HZ, div); 574 } 575 576 static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) 577 { 578 int src_clk_div; 579 580 /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/ 581 src_clk_div = GPLL_HZ / hz; 582 assert(src_clk_div - 1 <= 127); 583 584 switch (clk_id) { 585 case SCLK_I2C1: 586 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(1), 587 I2C_CLK_REG_VALUE(1, src_clk_div)); 588 break; 589 case SCLK_I2C2: 590 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(2), 591 I2C_CLK_REG_VALUE(2, src_clk_div)); 592 break; 593 case SCLK_I2C3: 594 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(3), 595 I2C_CLK_REG_VALUE(3, src_clk_div)); 596 break; 597 case SCLK_I2C5: 598 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(5), 599 I2C_CLK_REG_VALUE(5, src_clk_div)); 600 break; 601 case SCLK_I2C6: 602 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(6), 603 I2C_CLK_REG_VALUE(6, src_clk_div)); 604 break; 605 case SCLK_I2C7: 606 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(7), 607 I2C_CLK_REG_VALUE(7, src_clk_div)); 608 break; 609 default: 610 printf("do not support this i2c bus\n"); 611 return -EINVAL; 612 } 613 614 return rk3399_i2c_get_clk(cru, clk_id); 615 } 616 617 /* 618 * RK3399 SPI clocks have a common divider-width (7 bits) and a single bit 619 * to select either CPLL or GPLL as the clock-parent. The location within 620 * the enclosing CLKSEL_CON (i.e. div_shift and sel_shift) are variable. 621 */ 622 623 struct spi_clkreg { 624 uint8_t reg; /* CLKSEL_CON[reg] register in CRU */ 625 uint8_t div_shift; 626 uint8_t sel_shift; 627 }; 628 629 /* 630 * The entries are numbered relative to their offset from SCLK_SPI0. 631 * 632 * Note that SCLK_SPI3 (which is configured via PMUCRU and requires different 633 * logic is not supported). 634 */ 635 static const struct spi_clkreg spi_clkregs[] = { 636 [0] = { .reg = 59, 637 .div_shift = CLK_SPI0_PLL_DIV_CON_SHIFT, 638 .sel_shift = CLK_SPI0_PLL_SEL_SHIFT, }, 639 [1] = { .reg = 59, 640 .div_shift = CLK_SPI1_PLL_DIV_CON_SHIFT, 641 .sel_shift = CLK_SPI1_PLL_SEL_SHIFT, }, 642 [2] = { .reg = 60, 643 .div_shift = CLK_SPI2_PLL_DIV_CON_SHIFT, 644 .sel_shift = CLK_SPI2_PLL_SEL_SHIFT, }, 645 [3] = { .reg = 60, 646 .div_shift = CLK_SPI4_PLL_DIV_CON_SHIFT, 647 .sel_shift = CLK_SPI4_PLL_SEL_SHIFT, }, 648 [4] = { .reg = 58, 649 .div_shift = CLK_SPI5_PLL_DIV_CON_SHIFT, 650 .sel_shift = CLK_SPI5_PLL_SEL_SHIFT, }, 651 }; 652 653 static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id) 654 { 655 const struct spi_clkreg *spiclk = NULL; 656 u32 div, val; 657 658 switch (clk_id) { 659 case SCLK_SPI0 ... SCLK_SPI5: 660 spiclk = &spi_clkregs[clk_id - SCLK_SPI0]; 661 break; 662 663 default: 664 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id); 665 return -EINVAL; 666 } 667 668 val = readl(&cru->clksel_con[spiclk->reg]); 669 div = bitfield_extract(val, spiclk->div_shift, 670 CLK_SPI_PLL_DIV_CON_WIDTH); 671 672 return DIV_TO_RATE(GPLL_HZ, div); 673 } 674 675 static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) 676 { 677 const struct spi_clkreg *spiclk = NULL; 678 int src_clk_div; 679 680 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; 681 assert(src_clk_div < 128); 682 683 switch (clk_id) { 684 case SCLK_SPI1 ... SCLK_SPI5: 685 spiclk = &spi_clkregs[clk_id - SCLK_SPI0]; 686 break; 687 688 default: 689 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id); 690 return -EINVAL; 691 } 692 693 rk_clrsetreg(&cru->clksel_con[spiclk->reg], 694 ((CLK_SPI_PLL_DIV_CON_MASK << spiclk->div_shift) | 695 (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)), 696 ((src_clk_div << spiclk->div_shift) | 697 (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift))); 698 699 return rk3399_spi_get_clk(cru, clk_id); 700 } 701 702 #define RK3399_LIMIT_PLL_DCLK_VOP (600 * 1000000) 703 #define RK3399_LIMIT_PLL_ACLK_VOP (400 * 1000000) 704 705 static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz) 706 { 707 struct pll_div vpll_config = {0}, cpll_config = {0}; 708 int aclk_vop = RK3399_LIMIT_PLL_ACLK_VOP; 709 void *aclkreg_addr, *dclkreg_addr; 710 u32 div = 1; 711 712 switch (clk_id) { 713 case DCLK_VOP0: 714 aclkreg_addr = &cru->clksel_con[47]; 715 dclkreg_addr = &cru->clksel_con[49]; 716 break; 717 case DCLK_VOP1: 718 aclkreg_addr = &cru->clksel_con[48]; 719 dclkreg_addr = &cru->clksel_con[50]; 720 break; 721 default: 722 return -EINVAL; 723 } 724 /* vop aclk source clk: cpll */ 725 div = GPLL_HZ / aclk_vop; 726 assert(div - 1 <= 31); 727 728 rk_clrsetreg(aclkreg_addr, 729 ACLK_VOP_PLL_SEL_MASK | ACLK_VOP_DIV_CON_MASK, 730 ACLK_VOP_PLL_SEL_GPLL << ACLK_VOP_PLL_SEL_SHIFT | 731 (div - 1) << ACLK_VOP_DIV_CON_SHIFT); 732 733 div = DIV_ROUND_UP(RK3399_LIMIT_PLL_DCLK_VOP, hz); 734 735 if (readl(dclkreg_addr) & DCLK_VOP_PLL_SEL_MASK) { 736 if (pll_para_config(div * hz, &cpll_config)) 737 return -1; 738 rkclk_set_pll(&cru->cpll_con[0], &cpll_config); 739 } else { 740 if (pll_para_config(div * hz, &vpll_config)) 741 return -1; 742 rkclk_set_pll(&cru->vpll_con[0], &vpll_config); 743 } 744 745 rk_clrsetreg(dclkreg_addr, 746 DCLK_VOP_DCLK_SEL_MASK | DCLK_VOP_DIV_CON_MASK, 747 DCLK_VOP_DCLK_SEL_DIVOUT << DCLK_VOP_DCLK_SEL_SHIFT | 748 (div - 1) << DCLK_VOP_DIV_CON_SHIFT); 749 750 return hz; 751 } 752 753 static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id) 754 { 755 u32 div, con; 756 757 switch (clk_id) { 758 case HCLK_SDMMC: 759 case SCLK_SDMMC: 760 con = readl(&cru->clksel_con[16]); 761 /* dwmmc controller have internal div 2 */ 762 div = 2; 763 break; 764 case SCLK_EMMC: 765 con = readl(&cru->clksel_con[21]); 766 div = 1; 767 break; 768 default: 769 return -EINVAL; 770 } 771 772 div *= (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT; 773 if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT 774 == CLK_EMMC_PLL_SEL_24M) 775 return DIV_TO_RATE(OSC_HZ, div); 776 else 777 return DIV_TO_RATE(GPLL_HZ, div); 778 } 779 780 static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru, 781 ulong clk_id, ulong set_rate) 782 { 783 int src_clk_div; 784 int aclk_emmc = 198*MHz; 785 786 switch (clk_id) { 787 case HCLK_SDMMC: 788 case SCLK_SDMMC: 789 /* Select clk_sdmmc source from GPLL by default */ 790 /* mmc clock defaulg div 2 internal, provide double in cru */ 791 src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate); 792 793 if (src_clk_div > 128) { 794 /* use 24MHz source for 400KHz clock */ 795 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); 796 assert(src_clk_div - 1 < 128); 797 rk_clrsetreg(&cru->clksel_con[16], 798 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, 799 CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT | 800 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); 801 } else { 802 rk_clrsetreg(&cru->clksel_con[16], 803 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, 804 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT | 805 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); 806 } 807 break; 808 case SCLK_EMMC: 809 /* Select aclk_emmc source from GPLL */ 810 src_clk_div = DIV_ROUND_UP(GPLL_HZ , aclk_emmc); 811 assert(src_clk_div - 1 < 32); 812 813 rk_clrsetreg(&cru->clksel_con[21], 814 ACLK_EMMC_PLL_SEL_MASK | ACLK_EMMC_DIV_CON_MASK, 815 ACLK_EMMC_PLL_SEL_GPLL << ACLK_EMMC_PLL_SEL_SHIFT | 816 (src_clk_div - 1) << ACLK_EMMC_DIV_CON_SHIFT); 817 818 /* Select clk_emmc source from GPLL too */ 819 src_clk_div = DIV_ROUND_UP(GPLL_HZ, set_rate); 820 assert(src_clk_div - 1 < 128); 821 822 rk_clrsetreg(&cru->clksel_con[22], 823 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, 824 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT | 825 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); 826 break; 827 default: 828 return -EINVAL; 829 } 830 return rk3399_mmc_get_clk(cru, clk_id); 831 } 832 833 static ulong rk3399_gmac_set_clk(struct rk3399_cru *cru, ulong rate) 834 { 835 ulong ret; 836 837 /* 838 * The RGMII CLK can be derived either from an external "clkin" 839 * or can be generated from internally by a divider from SCLK_MAC. 840 */ 841 if (readl(&cru->clksel_con[19]) & BIT(4)) { 842 /* An external clock will always generate the right rate... */ 843 ret = rate; 844 } else { 845 /* 846 * No platform uses an internal clock to date. 847 * Implement this once it becomes necessary and print an error 848 * if someone tries to use it (while it remains unimplemented). 849 */ 850 pr_err("%s: internal clock is UNIMPLEMENTED\n", __func__); 851 ret = 0; 852 } 853 854 return ret; 855 } 856 857 #define PMUSGRF_DDR_RGN_CON16 0xff330040 858 static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru, 859 ulong set_rate) 860 { 861 struct pll_div dpll_cfg; 862 863 /* IC ECO bug, need to set this register */ 864 writel(0xc000c000, PMUSGRF_DDR_RGN_CON16); 865 866 /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */ 867 switch (set_rate) { 868 case 200*MHz: 869 dpll_cfg = (struct pll_div) 870 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1}; 871 break; 872 case 300*MHz: 873 dpll_cfg = (struct pll_div) 874 {.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1}; 875 break; 876 case 666*MHz: 877 dpll_cfg = (struct pll_div) 878 {.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1}; 879 break; 880 case 800*MHz: 881 dpll_cfg = (struct pll_div) 882 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}; 883 break; 884 case 933*MHz: 885 dpll_cfg = (struct pll_div) 886 {.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1}; 887 break; 888 default: 889 pr_err("Unsupported SDRAM frequency!,%ld\n", set_rate); 890 } 891 rkclk_set_pll(&cru->dpll_con[0], &dpll_cfg); 892 893 return set_rate; 894 } 895 896 static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru) 897 { 898 u32 div, val; 899 900 val = readl(&cru->clksel_con[26]); 901 div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT, 902 CLK_SARADC_DIV_CON_WIDTH); 903 904 return DIV_TO_RATE(OSC_HZ, div); 905 } 906 907 static ulong rk3399_saradc_set_clk(struct rk3399_cru *cru, uint hz) 908 { 909 int src_clk_div; 910 911 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; 912 assert(src_clk_div <= 255); 913 914 rk_clrsetreg(&cru->clksel_con[26], 915 CLK_SARADC_DIV_CON_MASK, 916 src_clk_div << CLK_SARADC_DIV_CON_SHIFT); 917 918 return rk3399_saradc_get_clk(cru); 919 } 920 921 static ulong rk3399_clk_get_rate(struct clk *clk) 922 { 923 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); 924 ulong rate = 0; 925 926 switch (clk->id) { 927 case PLL_APLLL: 928 case PLL_APLLB: 929 case PLL_DPLL: 930 case PLL_CPLL: 931 case PLL_GPLL: 932 case PLL_NPLL: 933 case PLL_VPLL: 934 rate = rk3399_pll_get_rate(priv, clk->id - 1); 935 break; 936 case HCLK_SDMMC: 937 case SCLK_SDMMC: 938 case SCLK_EMMC: 939 rate = rk3399_mmc_get_clk(priv->cru, clk->id); 940 break; 941 case SCLK_I2C1: 942 case SCLK_I2C2: 943 case SCLK_I2C3: 944 case SCLK_I2C5: 945 case SCLK_I2C6: 946 case SCLK_I2C7: 947 rate = rk3399_i2c_get_clk(priv->cru, clk->id); 948 break; 949 case SCLK_SPI0...SCLK_SPI5: 950 rate = rk3399_spi_get_clk(priv->cru, clk->id); 951 break; 952 case SCLK_UART0: 953 case SCLK_UART1: 954 case SCLK_UART2: 955 case SCLK_UART3: 956 return 24000000; 957 break; 958 case PCLK_HDMI_CTRL: 959 break; 960 case DCLK_VOP0: 961 case DCLK_VOP1: 962 break; 963 case PCLK_EFUSE1024NS: 964 break; 965 case SCLK_SARADC: 966 rate = rk3399_saradc_get_clk(priv->cru); 967 break; 968 default: 969 return -ENOENT; 970 } 971 972 return rate; 973 } 974 975 static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) 976 { 977 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); 978 ulong ret = 0; 979 980 switch (clk->id) { 981 case 0 ... 63: 982 return 0; 983 984 case ACLK_PERIHP: 985 case HCLK_PERIHP: 986 case PCLK_PERIHP: 987 return 0; 988 989 case ACLK_PERILP0: 990 case HCLK_PERILP0: 991 case PCLK_PERILP0: 992 return 0; 993 994 case ACLK_CCI: 995 return 0; 996 997 case HCLK_PERILP1: 998 case PCLK_PERILP1: 999 return 0; 1000 1001 case HCLK_SDMMC: 1002 case SCLK_SDMMC: 1003 case SCLK_EMMC: 1004 ret = rk3399_mmc_set_clk(priv->cru, clk->id, rate); 1005 break; 1006 case SCLK_MAC: 1007 ret = rk3399_gmac_set_clk(priv->cru, rate); 1008 break; 1009 case SCLK_I2C1: 1010 case SCLK_I2C2: 1011 case SCLK_I2C3: 1012 case SCLK_I2C5: 1013 case SCLK_I2C6: 1014 case SCLK_I2C7: 1015 ret = rk3399_i2c_set_clk(priv->cru, clk->id, rate); 1016 break; 1017 case SCLK_SPI0...SCLK_SPI5: 1018 ret = rk3399_spi_set_clk(priv->cru, clk->id, rate); 1019 break; 1020 case PCLK_HDMI_CTRL: 1021 case PCLK_VIO_GRF: 1022 /* the PCLK gates for video are enabled by default */ 1023 break; 1024 case DCLK_VOP0: 1025 case DCLK_VOP1: 1026 ret = rk3399_vop_set_clk(priv->cru, clk->id, rate); 1027 break; 1028 case SCLK_DDRCLK: 1029 ret = rk3399_ddr_set_clk(priv->cru, rate); 1030 break; 1031 case PCLK_EFUSE1024NS: 1032 break; 1033 case SCLK_SARADC: 1034 ret = rk3399_saradc_set_clk(priv->cru, rate); 1035 break; 1036 default: 1037 return -ENOENT; 1038 } 1039 1040 return ret; 1041 } 1042 1043 static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk, struct clk *parent) 1044 { 1045 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); 1046 const char *clock_output_name; 1047 int ret; 1048 1049 /* 1050 * If the requested parent is in the same clock-controller and 1051 * the id is SCLK_MAC ("clk_gmac"), switch to the internal clock. 1052 */ 1053 if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC)) { 1054 debug("%s: switching RGMII to SCLK_MAC\n", __func__); 1055 rk_clrreg(&priv->cru->clksel_con[19], BIT(4)); 1056 return 0; 1057 } 1058 1059 /* 1060 * Otherwise, we need to check the clock-output-names of the 1061 * requested parent to see if the requested id is "clkin_gmac". 1062 */ 1063 ret = dev_read_string_index(parent->dev, "clock-output-names", 1064 parent->id, &clock_output_name); 1065 if (ret < 0) 1066 return -ENODATA; 1067 1068 /* If this is "clkin_gmac", switch to the external clock input */ 1069 if (!strcmp(clock_output_name, "clkin_gmac")) { 1070 debug("%s: switching RGMII to CLKIN\n", __func__); 1071 rk_setreg(&priv->cru->clksel_con[19], BIT(4)); 1072 return 0; 1073 } 1074 1075 return -EINVAL; 1076 } 1077 1078 static int __maybe_unused rk3399_dclk_vop_set_parent(struct clk *clk, 1079 struct clk *parent) 1080 { 1081 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); 1082 void *dclkreg_addr; 1083 1084 switch (clk->id) { 1085 case DCLK_VOP0_DIV: 1086 dclkreg_addr = &priv->cru->clksel_con[49]; 1087 break; 1088 case DCLK_VOP1_DIV: 1089 dclkreg_addr = &priv->cru->clksel_con[50]; 1090 break; 1091 default: 1092 return -EINVAL; 1093 } 1094 if (parent->id == PLL_CPLL) { 1095 rk_clrsetreg(dclkreg_addr, DCLK_VOP_PLL_SEL_MASK, 1096 DCLK_VOP_PLL_SEL_CPLL << DCLK_VOP_PLL_SEL_SHIFT); 1097 } else { 1098 rk_clrsetreg(dclkreg_addr, DCLK_VOP_PLL_SEL_MASK, 1099 DCLK_VOP_PLL_SEL_VPLL << DCLK_VOP_PLL_SEL_SHIFT); 1100 } 1101 1102 return 0; 1103 } 1104 1105 static int __maybe_unused rk3399_clk_set_parent(struct clk *clk, struct clk *parent) 1106 { 1107 switch (clk->id) { 1108 case SCLK_RMII_SRC: 1109 return rk3399_gmac_set_parent(clk, parent); 1110 case DCLK_VOP0_DIV: 1111 case DCLK_VOP1_DIV: 1112 return rk3399_dclk_vop_set_parent(clk, parent); 1113 } 1114 1115 debug("%s: unsupported clk %ld\n", __func__, clk->id); 1116 return -ENOENT; 1117 } 1118 1119 static int rk3399_clk_enable(struct clk *clk) 1120 { 1121 switch (clk->id) { 1122 case HCLK_HOST0: 1123 case HCLK_HOST0_ARB: 1124 case SCLK_USBPHY0_480M_SRC: 1125 case HCLK_HOST1: 1126 case HCLK_HOST1_ARB: 1127 case SCLK_USBPHY1_480M_SRC: 1128 return 0; 1129 } 1130 1131 debug("%s: unsupported clk %ld\n", __func__, clk->id); 1132 return -ENOENT; 1133 } 1134 1135 static struct clk_ops rk3399_clk_ops = { 1136 .get_rate = rk3399_clk_get_rate, 1137 .set_rate = rk3399_clk_set_rate, 1138 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 1139 .set_parent = rk3399_clk_set_parent, 1140 #endif 1141 .enable = rk3399_clk_enable, 1142 }; 1143 1144 static void rkclk_init(struct rk3399_cru *cru) 1145 { 1146 u32 aclk_div; 1147 u32 hclk_div; 1148 u32 pclk_div; 1149 1150 rk3399_configure_cpu(cru, APLL_600_MHZ, CPU_CLUSTER_LITTLE); 1151 1152 /* 1153 * some cru registers changed by bootrom, we'd better reset them to 1154 * reset/default values described in TRM to avoid confusion in kernel. 1155 * Please consider these three lines as a fix of bootrom bug. 1156 */ 1157 rk_clrsetreg(&cru->clksel_con[12], 0xffff, 0x4101); 1158 rk_clrsetreg(&cru->clksel_con[19], 0xffff, 0x033f); 1159 rk_clrsetreg(&cru->clksel_con[56], 0x0003, 0x0003); 1160 1161 /* configure gpll cpll */ 1162 rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg); 1163 rkclk_set_pll(&cru->cpll_con[0], &cpll_init_cfg); 1164 rkclk_set_pll(&cru->npll_con[0], &npll_init_cfg); 1165 1166 /* configure perihp aclk, hclk, pclk */ 1167 aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1; 1168 assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); 1169 1170 hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1; 1171 assert((hclk_div + 1) * PERIHP_HCLK_HZ == 1172 PERIHP_ACLK_HZ && (hclk_div <= 0x3)); 1173 1174 pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1; 1175 assert((pclk_div + 1) * PERIHP_PCLK_HZ == 1176 PERIHP_ACLK_HZ && (pclk_div <= 0x7)); 1177 1178 rk_clrsetreg(&cru->clksel_con[14], 1179 PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK | 1180 ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK, 1181 pclk_div << PCLK_PERIHP_DIV_CON_SHIFT | 1182 hclk_div << HCLK_PERIHP_DIV_CON_SHIFT | 1183 ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT | 1184 aclk_div << ACLK_PERIHP_DIV_CON_SHIFT); 1185 1186 /* configure perilp0 aclk, hclk, pclk */ 1187 aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1; 1188 assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); 1189 1190 hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1; 1191 assert((hclk_div + 1) * PERILP0_HCLK_HZ == 1192 PERILP0_ACLK_HZ && (hclk_div <= 0x3)); 1193 1194 pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1; 1195 assert((pclk_div + 1) * PERILP0_PCLK_HZ == 1196 PERILP0_ACLK_HZ && (pclk_div <= 0x7)); 1197 1198 rk_clrsetreg(&cru->clksel_con[23], 1199 PCLK_PERILP0_DIV_CON_MASK | HCLK_PERILP0_DIV_CON_MASK | 1200 ACLK_PERILP0_PLL_SEL_MASK | ACLK_PERILP0_DIV_CON_MASK, 1201 pclk_div << PCLK_PERILP0_DIV_CON_SHIFT | 1202 hclk_div << HCLK_PERILP0_DIV_CON_SHIFT | 1203 ACLK_PERILP0_PLL_SEL_GPLL << ACLK_PERILP0_PLL_SEL_SHIFT | 1204 aclk_div << ACLK_PERILP0_DIV_CON_SHIFT); 1205 1206 /* perilp1 hclk select gpll as source */ 1207 hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1; 1208 assert((hclk_div + 1) * PERILP1_HCLK_HZ == 1209 GPLL_HZ && (hclk_div <= 0x1f)); 1210 1211 pclk_div = PERILP1_HCLK_HZ / PERILP1_PCLK_HZ - 1; 1212 assert((pclk_div + 1) * PERILP1_PCLK_HZ == 1213 PERILP1_HCLK_HZ && (pclk_div <= 0x7)); 1214 1215 rk_clrsetreg(&cru->clksel_con[25], 1216 PCLK_PERILP1_DIV_CON_MASK | HCLK_PERILP1_DIV_CON_MASK | 1217 HCLK_PERILP1_PLL_SEL_MASK, 1218 pclk_div << PCLK_PERILP1_DIV_CON_SHIFT | 1219 hclk_div << HCLK_PERILP1_DIV_CON_SHIFT | 1220 HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT); 1221 } 1222 1223 static int rk3399_clk_probe(struct udevice *dev) 1224 { 1225 struct rk3399_clk_priv *priv = dev_get_priv(dev); 1226 1227 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1228 struct rk3399_clk_plat *plat = dev_get_platdata(dev); 1229 1230 priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); 1231 #endif 1232 rkclk_init(priv->cru); 1233 return 0; 1234 } 1235 1236 static int rk3399_clk_ofdata_to_platdata(struct udevice *dev) 1237 { 1238 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 1239 struct rk3399_clk_priv *priv = dev_get_priv(dev); 1240 1241 priv->cru = dev_read_addr_ptr(dev); 1242 #endif 1243 return 0; 1244 } 1245 1246 static int rk3399_clk_bind(struct udevice *dev) 1247 { 1248 int ret; 1249 struct udevice *sys_child, *sf_child; 1250 struct sysreset_reg *priv; 1251 struct softreset_reg *sf_priv; 1252 1253 /* The reset driver does not have a device node, so bind it here */ 1254 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", 1255 &sys_child); 1256 if (ret) { 1257 debug("Warning: No sysreset driver: ret=%d\n", ret); 1258 } else { 1259 priv = malloc(sizeof(struct sysreset_reg)); 1260 priv->glb_srst_fst_value = offsetof(struct rk3399_cru, 1261 glb_srst_fst_value); 1262 priv->glb_srst_snd_value = offsetof(struct rk3399_cru, 1263 glb_srst_snd_value); 1264 sys_child->priv = priv; 1265 } 1266 1267 ret = device_bind_driver_to_node(dev, "rockchip_reset", "reset", 1268 dev_ofnode(dev), &sf_child); 1269 if (ret) { 1270 debug("Warning: No rockchip reset driver: ret=%d\n", ret); 1271 } else { 1272 sf_priv = malloc(sizeof(struct softreset_reg)); 1273 sf_priv->sf_reset_offset = offsetof(struct rk3399_cru, 1274 softrst_con[0]); 1275 sf_priv->sf_reset_num = 21; 1276 sf_child->priv = sf_priv; 1277 } 1278 1279 return 0; 1280 } 1281 1282 static const struct udevice_id rk3399_clk_ids[] = { 1283 { .compatible = "rockchip,rk3399-cru" }, 1284 { } 1285 }; 1286 1287 U_BOOT_DRIVER(clk_rk3399) = { 1288 .name = "rockchip_rk3399_cru", 1289 .id = UCLASS_CLK, 1290 .of_match = rk3399_clk_ids, 1291 .priv_auto_alloc_size = sizeof(struct rk3399_clk_priv), 1292 .ofdata_to_platdata = rk3399_clk_ofdata_to_platdata, 1293 .ops = &rk3399_clk_ops, 1294 .bind = rk3399_clk_bind, 1295 .probe = rk3399_clk_probe, 1296 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1297 .platdata_auto_alloc_size = sizeof(struct rk3399_clk_plat), 1298 #endif 1299 }; 1300 1301 static ulong rk3399_i2c_get_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id) 1302 { 1303 u32 div, con; 1304 1305 switch (clk_id) { 1306 case SCLK_I2C0_PMU: 1307 con = readl(&pmucru->pmucru_clksel[2]); 1308 div = I2C_CLK_DIV_VALUE(con, 0); 1309 break; 1310 case SCLK_I2C4_PMU: 1311 con = readl(&pmucru->pmucru_clksel[3]); 1312 div = I2C_CLK_DIV_VALUE(con, 4); 1313 break; 1314 case SCLK_I2C8_PMU: 1315 con = readl(&pmucru->pmucru_clksel[2]); 1316 div = I2C_CLK_DIV_VALUE(con, 8); 1317 break; 1318 default: 1319 printf("do not support this i2c bus\n"); 1320 return -EINVAL; 1321 } 1322 1323 return DIV_TO_RATE(PPLL_HZ, div); 1324 } 1325 1326 static ulong rk3399_i2c_set_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id, 1327 uint hz) 1328 { 1329 int src_clk_div; 1330 1331 src_clk_div = PPLL_HZ / hz; 1332 assert(src_clk_div - 1 < 127); 1333 1334 switch (clk_id) { 1335 case SCLK_I2C0_PMU: 1336 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(0), 1337 I2C_PMUCLK_REG_VALUE(0, src_clk_div)); 1338 break; 1339 case SCLK_I2C4_PMU: 1340 rk_clrsetreg(&pmucru->pmucru_clksel[3], I2C_PMUCLK_REG_MASK(4), 1341 I2C_PMUCLK_REG_VALUE(4, src_clk_div)); 1342 break; 1343 case SCLK_I2C8_PMU: 1344 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(8), 1345 I2C_PMUCLK_REG_VALUE(8, src_clk_div)); 1346 break; 1347 default: 1348 printf("do not support this i2c bus\n"); 1349 return -EINVAL; 1350 } 1351 1352 return DIV_TO_RATE(PPLL_HZ, src_clk_div); 1353 } 1354 1355 static ulong rk3399_pwm_get_clk(struct rk3399_pmucru *pmucru) 1356 { 1357 u32 div, con; 1358 1359 /* PWM closk rate is same as pclk_pmu */ 1360 con = readl(&pmucru->pmucru_clksel[0]); 1361 div = con & PMU_PCLK_DIV_CON_MASK; 1362 1363 return DIV_TO_RATE(PPLL_HZ, div); 1364 } 1365 1366 static ulong rk3399_pmuclk_get_rate(struct clk *clk) 1367 { 1368 struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev); 1369 ulong rate = 0; 1370 1371 switch (clk->id) { 1372 case PCLK_RKPWM_PMU: 1373 rate = rk3399_pwm_get_clk(priv->pmucru); 1374 break; 1375 case SCLK_I2C0_PMU: 1376 case SCLK_I2C4_PMU: 1377 case SCLK_I2C8_PMU: 1378 rate = rk3399_i2c_get_pmuclk(priv->pmucru, clk->id); 1379 break; 1380 case SCLK_UART4_PMU: 1381 rate = 24000000; 1382 break; 1383 default: 1384 return -ENOENT; 1385 } 1386 1387 return rate; 1388 } 1389 1390 static ulong rk3399_pmuclk_set_rate(struct clk *clk, ulong rate) 1391 { 1392 struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev); 1393 ulong ret = 0; 1394 1395 switch (clk->id) { 1396 case SCLK_I2C0_PMU: 1397 case SCLK_I2C4_PMU: 1398 case SCLK_I2C8_PMU: 1399 ret = rk3399_i2c_set_pmuclk(priv->pmucru, clk->id, rate); 1400 break; 1401 default: 1402 return -ENOENT; 1403 } 1404 1405 return ret; 1406 } 1407 1408 static struct clk_ops rk3399_pmuclk_ops = { 1409 .get_rate = rk3399_pmuclk_get_rate, 1410 .set_rate = rk3399_pmuclk_set_rate, 1411 }; 1412 1413 #ifndef CONFIG_SPL_BUILD 1414 static void pmuclk_init(struct rk3399_pmucru *pmucru) 1415 { 1416 u32 pclk_div; 1417 1418 /* configure pmu pll(ppll) */ 1419 rkclk_set_pll(&pmucru->ppll_con[0], &ppll_init_cfg); 1420 1421 /* configure pmu pclk */ 1422 pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1; 1423 assert((pclk_div + 1) * PMU_PCLK_HZ == PPLL_HZ && pclk_div <= 0x1f); 1424 rk_clrsetreg(&pmucru->pmucru_clksel[0], 1425 PMU_PCLK_DIV_CON_MASK, 1426 pclk_div << PMU_PCLK_DIV_CON_SHIFT); 1427 } 1428 #endif 1429 1430 static int rk3399_pmuclk_probe(struct udevice *dev) 1431 { 1432 #if CONFIG_IS_ENABLED(OF_PLATDATA) || !defined(CONFIG_SPL_BUILD) 1433 struct rk3399_pmuclk_priv *priv = dev_get_priv(dev); 1434 #endif 1435 1436 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1437 struct rk3399_pmuclk_plat *plat = dev_get_platdata(dev); 1438 1439 priv->pmucru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); 1440 #endif 1441 1442 #ifndef CONFIG_SPL_BUILD 1443 pmuclk_init(priv->pmucru); 1444 #endif 1445 return 0; 1446 } 1447 1448 static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev) 1449 { 1450 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 1451 struct rk3399_pmuclk_priv *priv = dev_get_priv(dev); 1452 1453 priv->pmucru = dev_read_addr_ptr(dev); 1454 #endif 1455 return 0; 1456 } 1457 1458 static int rk3399_pmuclk_bind(struct udevice *dev) 1459 { 1460 int ret = 0; 1461 struct udevice *sf_child; 1462 struct softreset_reg *sf_priv; 1463 1464 ret = device_bind_driver_to_node(dev, "rockchip_reset", 1465 "reset", dev_ofnode(dev), 1466 &sf_child); 1467 if (ret) { 1468 debug("Warning: No rockchip reset driver: ret=%d\n", ret); 1469 } else { 1470 sf_priv = malloc(sizeof(struct softreset_reg)); 1471 sf_priv->sf_reset_offset = offsetof(struct rk3399_pmucru, 1472 pmucru_softrst_con[0]); 1473 sf_priv->sf_reset_num = 2; 1474 sf_child->priv = sf_priv; 1475 } 1476 1477 return 0; 1478 } 1479 1480 static const struct udevice_id rk3399_pmuclk_ids[] = { 1481 { .compatible = "rockchip,rk3399-pmucru" }, 1482 { } 1483 }; 1484 1485 U_BOOT_DRIVER(rockchip_rk3399_pmuclk) = { 1486 .name = "rockchip_rk3399_pmucru", 1487 .id = UCLASS_CLK, 1488 .of_match = rk3399_pmuclk_ids, 1489 .priv_auto_alloc_size = sizeof(struct rk3399_pmuclk_priv), 1490 .ofdata_to_platdata = rk3399_pmuclk_ofdata_to_platdata, 1491 .ops = &rk3399_pmuclk_ops, 1492 .probe = rk3399_pmuclk_probe, 1493 .bind = rk3399_pmuclk_bind, 1494 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1495 .platdata_auto_alloc_size = sizeof(struct rk3399_pmuclk_plat), 1496 #endif 1497 }; 1498