1 /* 2 * (C) Copyright 2015 Google, Inc 3 * (C) 2017 Theobroma Systems Design und Consulting GmbH 4 * 5 * SPDX-License-Identifier: GPL-2.0 6 */ 7 8 #include <common.h> 9 #include <clk-uclass.h> 10 #include <dm.h> 11 #include <dt-structs.h> 12 #include <errno.h> 13 #include <mapmem.h> 14 #include <syscon.h> 15 #include <bitfield.h> 16 #include <asm/io.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/cru_rk3399.h> 19 #include <asm/arch/hardware.h> 20 #include <dm/lists.h> 21 #include <dt-bindings/clock/rk3399-cru.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #if CONFIG_IS_ENABLED(OF_PLATDATA) 26 struct rk3399_clk_plat { 27 struct dtd_rockchip_rk3399_cru dtd; 28 }; 29 30 struct rk3399_pmuclk_plat { 31 struct dtd_rockchip_rk3399_pmucru dtd; 32 }; 33 #endif 34 35 struct pll_div { 36 u32 refdiv; 37 u32 fbdiv; 38 u32 postdiv1; 39 u32 postdiv2; 40 u32 frac; 41 u32 freq; 42 }; 43 44 #define RATE_TO_DIV(input_rate, output_rate) \ 45 ((input_rate) / (output_rate) - 1); 46 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) 47 48 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ 49 .refdiv = _refdiv,\ 50 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\ 51 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2, .freq = hz}; 52 53 #if defined(CONFIG_SPL_BUILD) 54 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); 55 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2); 56 #else 57 static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1); 58 #endif 59 60 static const struct pll_div apll_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1); 61 static const struct pll_div apll_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1); 62 63 static const struct pll_div *apll_cfgs[] = { 64 [APLL_1600_MHZ] = &apll_1600_cfg, 65 [APLL_600_MHZ] = &apll_600_cfg, 66 }; 67 68 enum { 69 /* PLL_CON0 */ 70 PLL_FBDIV_MASK = 0xfff, 71 PLL_FBDIV_SHIFT = 0, 72 73 /* PLL_CON1 */ 74 PLL_POSTDIV2_SHIFT = 12, 75 PLL_POSTDIV2_MASK = 0x7 << PLL_POSTDIV2_SHIFT, 76 PLL_POSTDIV1_SHIFT = 8, 77 PLL_POSTDIV1_MASK = 0x7 << PLL_POSTDIV1_SHIFT, 78 PLL_REFDIV_MASK = 0x3f, 79 PLL_REFDIV_SHIFT = 0, 80 81 /* PLL_CON2 */ 82 PLL_LOCK_STATUS_SHIFT = 31, 83 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, 84 PLL_FRACDIV_MASK = 0xffffff, 85 PLL_FRACDIV_SHIFT = 0, 86 87 /* PLL_CON3 */ 88 PLL_MODE_SHIFT = 8, 89 PLL_MODE_MASK = 3 << PLL_MODE_SHIFT, 90 PLL_MODE_SLOW = 0, 91 PLL_MODE_NORM, 92 PLL_MODE_DEEP, 93 PLL_DSMPD_SHIFT = 3, 94 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, 95 PLL_INTEGER_MODE = 1, 96 97 /* PMUCRU_CLKSEL_CON0 */ 98 PMU_PCLK_DIV_CON_MASK = 0x1f, 99 PMU_PCLK_DIV_CON_SHIFT = 0, 100 101 /* PMUCRU_CLKSEL_CON1 */ 102 SPI3_PLL_SEL_SHIFT = 7, 103 SPI3_PLL_SEL_MASK = 1 << SPI3_PLL_SEL_SHIFT, 104 SPI3_PLL_SEL_24M = 0, 105 SPI3_PLL_SEL_PPLL = 1, 106 SPI3_DIV_CON_SHIFT = 0x0, 107 SPI3_DIV_CON_MASK = 0x7f, 108 109 /* PMUCRU_CLKSEL_CON2 */ 110 I2C_DIV_CON_MASK = 0x7f, 111 CLK_I2C8_DIV_CON_SHIFT = 8, 112 CLK_I2C0_DIV_CON_SHIFT = 0, 113 114 /* PMUCRU_CLKSEL_CON3 */ 115 CLK_I2C4_DIV_CON_SHIFT = 0, 116 117 /* CLKSEL_CON0 / CLKSEL_CON2 */ 118 ACLKM_CORE_DIV_CON_MASK = 0x1f, 119 ACLKM_CORE_DIV_CON_SHIFT = 8, 120 CLK_CORE_PLL_SEL_MASK = 3, 121 CLK_CORE_PLL_SEL_SHIFT = 6, 122 CLK_CORE_PLL_SEL_ALPLL = 0x0, 123 CLK_CORE_PLL_SEL_ABPLL = 0x1, 124 CLK_CORE_PLL_SEL_DPLL = 0x10, 125 CLK_CORE_PLL_SEL_GPLL = 0x11, 126 CLK_CORE_DIV_MASK = 0x1f, 127 CLK_CORE_DIV_SHIFT = 0, 128 129 /* CLKSEL_CON1 / CLKSEL_CON3 */ 130 PCLK_DBG_DIV_MASK = 0x1f, 131 PCLK_DBG_DIV_SHIFT = 0x8, 132 ATCLK_CORE_DIV_MASK = 0x1f, 133 ATCLK_CORE_DIV_SHIFT = 0, 134 135 /* CLKSEL_CON14 */ 136 PCLK_PERIHP_DIV_CON_SHIFT = 12, 137 PCLK_PERIHP_DIV_CON_MASK = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT, 138 HCLK_PERIHP_DIV_CON_SHIFT = 8, 139 HCLK_PERIHP_DIV_CON_MASK = 3 << HCLK_PERIHP_DIV_CON_SHIFT, 140 ACLK_PERIHP_PLL_SEL_SHIFT = 7, 141 ACLK_PERIHP_PLL_SEL_MASK = 1 << ACLK_PERIHP_PLL_SEL_SHIFT, 142 ACLK_PERIHP_PLL_SEL_CPLL = 0, 143 ACLK_PERIHP_PLL_SEL_GPLL = 1, 144 ACLK_PERIHP_DIV_CON_SHIFT = 0, 145 ACLK_PERIHP_DIV_CON_MASK = 0x1f, 146 147 /* CLKSEL_CON21 */ 148 ACLK_EMMC_PLL_SEL_SHIFT = 7, 149 ACLK_EMMC_PLL_SEL_MASK = 0x1 << ACLK_EMMC_PLL_SEL_SHIFT, 150 ACLK_EMMC_PLL_SEL_GPLL = 0x1, 151 ACLK_EMMC_DIV_CON_SHIFT = 0, 152 ACLK_EMMC_DIV_CON_MASK = 0x1f, 153 154 /* CLKSEL_CON22 */ 155 CLK_EMMC_PLL_SHIFT = 8, 156 CLK_EMMC_PLL_MASK = 0x7 << CLK_EMMC_PLL_SHIFT, 157 CLK_EMMC_PLL_SEL_GPLL = 0x1, 158 CLK_EMMC_PLL_SEL_24M = 0x5, 159 CLK_EMMC_DIV_CON_SHIFT = 0, 160 CLK_EMMC_DIV_CON_MASK = 0x7f << CLK_EMMC_DIV_CON_SHIFT, 161 162 /* CLKSEL_CON23 */ 163 PCLK_PERILP0_DIV_CON_SHIFT = 12, 164 PCLK_PERILP0_DIV_CON_MASK = 0x7 << PCLK_PERILP0_DIV_CON_SHIFT, 165 HCLK_PERILP0_DIV_CON_SHIFT = 8, 166 HCLK_PERILP0_DIV_CON_MASK = 3 << HCLK_PERILP0_DIV_CON_SHIFT, 167 ACLK_PERILP0_PLL_SEL_SHIFT = 7, 168 ACLK_PERILP0_PLL_SEL_MASK = 1 << ACLK_PERILP0_PLL_SEL_SHIFT, 169 ACLK_PERILP0_PLL_SEL_CPLL = 0, 170 ACLK_PERILP0_PLL_SEL_GPLL = 1, 171 ACLK_PERILP0_DIV_CON_SHIFT = 0, 172 ACLK_PERILP0_DIV_CON_MASK = 0x1f, 173 174 /* CLKSEL_CON25 */ 175 PCLK_PERILP1_DIV_CON_SHIFT = 8, 176 PCLK_PERILP1_DIV_CON_MASK = 0x7 << PCLK_PERILP1_DIV_CON_SHIFT, 177 HCLK_PERILP1_PLL_SEL_SHIFT = 7, 178 HCLK_PERILP1_PLL_SEL_MASK = 1 << HCLK_PERILP1_PLL_SEL_SHIFT, 179 HCLK_PERILP1_PLL_SEL_CPLL = 0, 180 HCLK_PERILP1_PLL_SEL_GPLL = 1, 181 HCLK_PERILP1_DIV_CON_SHIFT = 0, 182 HCLK_PERILP1_DIV_CON_MASK = 0x1f, 183 184 /* CLKSEL_CON26 */ 185 CLK_SARADC_DIV_CON_SHIFT = 8, 186 CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8), 187 CLK_SARADC_DIV_CON_WIDTH = 8, 188 189 /* CLKSEL_CON27 */ 190 CLK_TSADC_SEL_X24M = 0x0, 191 CLK_TSADC_SEL_SHIFT = 15, 192 CLK_TSADC_SEL_MASK = 1 << CLK_TSADC_SEL_SHIFT, 193 CLK_TSADC_DIV_CON_SHIFT = 0, 194 CLK_TSADC_DIV_CON_MASK = 0x3ff, 195 196 /* CLKSEL_CON47 & CLKSEL_CON48 */ 197 ACLK_VOP_PLL_SEL_SHIFT = 6, 198 ACLK_VOP_PLL_SEL_MASK = 0x3 << ACLK_VOP_PLL_SEL_SHIFT, 199 ACLK_VOP_PLL_SEL_CPLL = 0x1, 200 ACLK_VOP_DIV_CON_SHIFT = 0, 201 ACLK_VOP_DIV_CON_MASK = 0x1f << ACLK_VOP_DIV_CON_SHIFT, 202 203 /* CLKSEL_CON49 & CLKSEL_CON50 */ 204 DCLK_VOP_DCLK_SEL_SHIFT = 11, 205 DCLK_VOP_DCLK_SEL_MASK = 1 << DCLK_VOP_DCLK_SEL_SHIFT, 206 DCLK_VOP_DCLK_SEL_DIVOUT = 0, 207 DCLK_VOP_PLL_SEL_SHIFT = 8, 208 DCLK_VOP_PLL_SEL_MASK = 3 << DCLK_VOP_PLL_SEL_SHIFT, 209 DCLK_VOP_PLL_SEL_VPLL = 0, 210 DCLK_VOP_DIV_CON_MASK = 0xff, 211 DCLK_VOP_DIV_CON_SHIFT = 0, 212 213 /* CLKSEL_CON58 */ 214 CLK_SPI_PLL_SEL_WIDTH = 1, 215 CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1), 216 CLK_SPI_PLL_SEL_CPLL = 0, 217 CLK_SPI_PLL_SEL_GPLL = 1, 218 CLK_SPI_PLL_DIV_CON_WIDTH = 7, 219 CLK_SPI_PLL_DIV_CON_MASK = ((1 << CLK_SPI_PLL_DIV_CON_WIDTH) - 1), 220 221 CLK_SPI5_PLL_DIV_CON_SHIFT = 8, 222 CLK_SPI5_PLL_SEL_SHIFT = 15, 223 224 /* CLKSEL_CON59 */ 225 CLK_SPI1_PLL_SEL_SHIFT = 15, 226 CLK_SPI1_PLL_DIV_CON_SHIFT = 8, 227 CLK_SPI0_PLL_SEL_SHIFT = 7, 228 CLK_SPI0_PLL_DIV_CON_SHIFT = 0, 229 230 /* CLKSEL_CON60 */ 231 CLK_SPI4_PLL_SEL_SHIFT = 15, 232 CLK_SPI4_PLL_DIV_CON_SHIFT = 8, 233 CLK_SPI2_PLL_SEL_SHIFT = 7, 234 CLK_SPI2_PLL_DIV_CON_SHIFT = 0, 235 236 /* CLKSEL_CON61 */ 237 CLK_I2C_PLL_SEL_MASK = 1, 238 CLK_I2C_PLL_SEL_CPLL = 0, 239 CLK_I2C_PLL_SEL_GPLL = 1, 240 CLK_I2C5_PLL_SEL_SHIFT = 15, 241 CLK_I2C5_DIV_CON_SHIFT = 8, 242 CLK_I2C1_PLL_SEL_SHIFT = 7, 243 CLK_I2C1_DIV_CON_SHIFT = 0, 244 245 /* CLKSEL_CON62 */ 246 CLK_I2C6_PLL_SEL_SHIFT = 15, 247 CLK_I2C6_DIV_CON_SHIFT = 8, 248 CLK_I2C2_PLL_SEL_SHIFT = 7, 249 CLK_I2C2_DIV_CON_SHIFT = 0, 250 251 /* CLKSEL_CON63 */ 252 CLK_I2C7_PLL_SEL_SHIFT = 15, 253 CLK_I2C7_DIV_CON_SHIFT = 8, 254 CLK_I2C3_PLL_SEL_SHIFT = 7, 255 CLK_I2C3_DIV_CON_SHIFT = 0, 256 257 /* CRU_SOFTRST_CON4 */ 258 RESETN_DDR0_REQ_SHIFT = 8, 259 RESETN_DDR0_REQ_MASK = 1 << RESETN_DDR0_REQ_SHIFT, 260 RESETN_DDRPHY0_REQ_SHIFT = 9, 261 RESETN_DDRPHY0_REQ_MASK = 1 << RESETN_DDRPHY0_REQ_SHIFT, 262 RESETN_DDR1_REQ_SHIFT = 12, 263 RESETN_DDR1_REQ_MASK = 1 << RESETN_DDR1_REQ_SHIFT, 264 RESETN_DDRPHY1_REQ_SHIFT = 13, 265 RESETN_DDRPHY1_REQ_MASK = 1 << RESETN_DDRPHY1_REQ_SHIFT, 266 }; 267 268 #define VCO_MAX_KHZ (3200 * (MHz / KHz)) 269 #define VCO_MIN_KHZ (800 * (MHz / KHz)) 270 #define OUTPUT_MAX_KHZ (3200 * (MHz / KHz)) 271 #define OUTPUT_MIN_KHZ (16 * (MHz / KHz)) 272 273 /* 274 * the div restructions of pll in integer mode, these are defined in 275 * * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0 276 */ 277 #define PLL_DIV_MIN 16 278 #define PLL_DIV_MAX 3200 279 280 /* 281 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63): 282 * Formulas also embedded within the Fractional PLL Verilog model: 283 * If DSMPD = 1 (DSM is disabled, "integer mode") 284 * FOUTVCO = FREF / REFDIV * FBDIV 285 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2 286 * Where: 287 * FOUTVCO = Fractional PLL non-divided output frequency 288 * FOUTPOSTDIV = Fractional PLL divided output frequency 289 * (output of second post divider) 290 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input) 291 * REFDIV = Fractional PLL input reference clock divider 292 * FBDIV = Integer value programmed into feedback divide 293 * 294 */ 295 static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div) 296 { 297 /* All 8 PLLs have same VCO and output frequency range restrictions. */ 298 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; 299 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2; 300 301 debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, " 302 "postdiv2=%d, vco=%u khz, output=%u khz\n", 303 pll_con, div->fbdiv, div->refdiv, div->postdiv1, 304 div->postdiv2, vco_khz, output_khz); 305 assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ && 306 output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ && 307 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); 308 309 /* 310 * When power on or changing PLL setting, 311 * we must force PLL into slow mode to ensure output stable clock. 312 */ 313 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK, 314 PLL_MODE_SLOW << PLL_MODE_SHIFT); 315 316 /* use integer mode */ 317 rk_clrsetreg(&pll_con[3], PLL_DSMPD_MASK, 318 PLL_INTEGER_MODE << PLL_DSMPD_SHIFT); 319 320 rk_clrsetreg(&pll_con[0], PLL_FBDIV_MASK, 321 div->fbdiv << PLL_FBDIV_SHIFT); 322 rk_clrsetreg(&pll_con[1], 323 PLL_POSTDIV2_MASK | PLL_POSTDIV1_MASK | 324 PLL_REFDIV_MASK | PLL_REFDIV_SHIFT, 325 (div->postdiv2 << PLL_POSTDIV2_SHIFT) | 326 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | 327 (div->refdiv << PLL_REFDIV_SHIFT)); 328 329 /* waiting for pll lock */ 330 while (!(readl(&pll_con[2]) & (1 << PLL_LOCK_STATUS_SHIFT))) 331 udelay(1); 332 333 /* pll enter normal mode */ 334 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK, 335 PLL_MODE_NORM << PLL_MODE_SHIFT); 336 } 337 338 static int pll_para_config(u32 freq_hz, struct pll_div *div) 339 { 340 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; 341 u32 postdiv1, postdiv2 = 1; 342 u32 fref_khz; 343 u32 diff_khz, best_diff_khz; 344 const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16; 345 const u32 max_postdiv1 = 7, max_postdiv2 = 7; 346 u32 vco_khz; 347 u32 freq_khz = freq_hz / KHz; 348 349 if (!freq_hz) { 350 printf("%s: the frequency can't be 0 Hz\n", __func__); 351 return -1; 352 } 353 354 postdiv1 = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz); 355 if (postdiv1 > max_postdiv1) { 356 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); 357 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); 358 } 359 360 vco_khz = freq_khz * postdiv1 * postdiv2; 361 362 if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || 363 postdiv2 > max_postdiv2) { 364 printf("%s: Cannot find out a supported VCO" 365 " for Frequency (%uHz).\n", __func__, freq_hz); 366 return -1; 367 } 368 369 div->postdiv1 = postdiv1; 370 div->postdiv2 = postdiv2; 371 372 best_diff_khz = vco_khz; 373 for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) { 374 fref_khz = ref_khz / refdiv; 375 376 fbdiv = vco_khz / fref_khz; 377 if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv)) 378 continue; 379 diff_khz = vco_khz - fbdiv * fref_khz; 380 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) { 381 fbdiv++; 382 diff_khz = fref_khz - diff_khz; 383 } 384 385 if (diff_khz >= best_diff_khz) 386 continue; 387 388 best_diff_khz = diff_khz; 389 div->refdiv = refdiv; 390 div->fbdiv = fbdiv; 391 } 392 393 if (best_diff_khz > 4 * (MHz/KHz)) { 394 printf("%s: Failed to match output frequency %u, " 395 "difference is %u Hz,exceed 4MHZ\n", __func__, freq_hz, 396 best_diff_khz * KHz); 397 return -1; 398 } 399 return 0; 400 } 401 402 void rk3399_configure_cpu(struct rk3399_cru *cru, 403 enum apll_frequencies freq, 404 enum cpu_cluster cluster) 405 { 406 u32 aclkm_div; 407 u32 pclk_dbg_div; 408 u32 atclk_div, apll_hz; 409 int con_base, parent; 410 u32 *pll_con; 411 412 switch (cluster) { 413 case CPU_CLUSTER_LITTLE: 414 con_base = 0; 415 parent = CLK_CORE_PLL_SEL_ALPLL; 416 pll_con = &cru->apll_l_con[0]; 417 break; 418 case CPU_CLUSTER_BIG: 419 default: 420 con_base = 2; 421 parent = CLK_CORE_PLL_SEL_ABPLL; 422 pll_con = &cru->apll_b_con[0]; 423 break; 424 } 425 426 apll_hz = apll_cfgs[freq]->freq; 427 rkclk_set_pll(pll_con, apll_cfgs[freq]); 428 429 aclkm_div = apll_hz / ACLKM_CORE_HZ - 1; 430 assert((aclkm_div + 1) * ACLKM_CORE_HZ == apll_hz && 431 aclkm_div < 0x1f); 432 433 pclk_dbg_div = apll_hz / PCLK_DBG_HZ - 1; 434 assert((pclk_dbg_div + 1) * PCLK_DBG_HZ == apll_hz && 435 pclk_dbg_div < 0x1f); 436 437 atclk_div = apll_hz / ATCLK_CORE_HZ - 1; 438 assert((atclk_div + 1) * ATCLK_CORE_HZ == apll_hz && 439 atclk_div < 0x1f); 440 441 rk_clrsetreg(&cru->clksel_con[con_base], 442 ACLKM_CORE_DIV_CON_MASK | CLK_CORE_PLL_SEL_MASK | 443 CLK_CORE_DIV_MASK, 444 aclkm_div << ACLKM_CORE_DIV_CON_SHIFT | 445 parent << CLK_CORE_PLL_SEL_SHIFT | 446 0 << CLK_CORE_DIV_SHIFT); 447 448 rk_clrsetreg(&cru->clksel_con[con_base + 1], 449 PCLK_DBG_DIV_MASK | ATCLK_CORE_DIV_MASK, 450 pclk_dbg_div << PCLK_DBG_DIV_SHIFT | 451 atclk_div << ATCLK_CORE_DIV_SHIFT); 452 } 453 #define I2C_CLK_REG_MASK(bus) \ 454 (I2C_DIV_CON_MASK << \ 455 CLK_I2C ##bus## _DIV_CON_SHIFT | \ 456 CLK_I2C_PLL_SEL_MASK << \ 457 CLK_I2C ##bus## _PLL_SEL_SHIFT) 458 459 #define I2C_CLK_REG_VALUE(bus, clk_div) \ 460 ((clk_div - 1) << \ 461 CLK_I2C ##bus## _DIV_CON_SHIFT | \ 462 CLK_I2C_PLL_SEL_GPLL << \ 463 CLK_I2C ##bus## _PLL_SEL_SHIFT) 464 465 #define I2C_CLK_DIV_VALUE(con, bus) \ 466 (con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & \ 467 I2C_DIV_CON_MASK; 468 469 #define I2C_PMUCLK_REG_MASK(bus) \ 470 (I2C_DIV_CON_MASK << \ 471 CLK_I2C ##bus## _DIV_CON_SHIFT) 472 473 #define I2C_PMUCLK_REG_VALUE(bus, clk_div) \ 474 ((clk_div - 1) << \ 475 CLK_I2C ##bus## _DIV_CON_SHIFT) 476 477 static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id) 478 { 479 u32 div, con; 480 481 switch (clk_id) { 482 case SCLK_I2C1: 483 con = readl(&cru->clksel_con[61]); 484 div = I2C_CLK_DIV_VALUE(con, 1); 485 break; 486 case SCLK_I2C2: 487 con = readl(&cru->clksel_con[62]); 488 div = I2C_CLK_DIV_VALUE(con, 2); 489 break; 490 case SCLK_I2C3: 491 con = readl(&cru->clksel_con[63]); 492 div = I2C_CLK_DIV_VALUE(con, 3); 493 break; 494 case SCLK_I2C5: 495 con = readl(&cru->clksel_con[61]); 496 div = I2C_CLK_DIV_VALUE(con, 5); 497 break; 498 case SCLK_I2C6: 499 con = readl(&cru->clksel_con[62]); 500 div = I2C_CLK_DIV_VALUE(con, 6); 501 break; 502 case SCLK_I2C7: 503 con = readl(&cru->clksel_con[63]); 504 div = I2C_CLK_DIV_VALUE(con, 7); 505 break; 506 default: 507 printf("do not support this i2c bus\n"); 508 return -EINVAL; 509 } 510 511 return DIV_TO_RATE(GPLL_HZ, div); 512 } 513 514 static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) 515 { 516 int src_clk_div; 517 518 /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/ 519 src_clk_div = GPLL_HZ / hz; 520 assert(src_clk_div - 1 <= 127); 521 522 switch (clk_id) { 523 case SCLK_I2C1: 524 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(1), 525 I2C_CLK_REG_VALUE(1, src_clk_div)); 526 break; 527 case SCLK_I2C2: 528 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(2), 529 I2C_CLK_REG_VALUE(2, src_clk_div)); 530 break; 531 case SCLK_I2C3: 532 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(3), 533 I2C_CLK_REG_VALUE(3, src_clk_div)); 534 break; 535 case SCLK_I2C5: 536 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(5), 537 I2C_CLK_REG_VALUE(5, src_clk_div)); 538 break; 539 case SCLK_I2C6: 540 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(6), 541 I2C_CLK_REG_VALUE(6, src_clk_div)); 542 break; 543 case SCLK_I2C7: 544 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(7), 545 I2C_CLK_REG_VALUE(7, src_clk_div)); 546 break; 547 default: 548 printf("do not support this i2c bus\n"); 549 return -EINVAL; 550 } 551 552 return rk3399_i2c_get_clk(cru, clk_id); 553 } 554 555 /* 556 * RK3399 SPI clocks have a common divider-width (7 bits) and a single bit 557 * to select either CPLL or GPLL as the clock-parent. The location within 558 * the enclosing CLKSEL_CON (i.e. div_shift and sel_shift) are variable. 559 */ 560 561 struct spi_clkreg { 562 uint8_t reg; /* CLKSEL_CON[reg] register in CRU */ 563 uint8_t div_shift; 564 uint8_t sel_shift; 565 }; 566 567 /* 568 * The entries are numbered relative to their offset from SCLK_SPI0. 569 * 570 * Note that SCLK_SPI3 (which is configured via PMUCRU and requires different 571 * logic is not supported). 572 */ 573 static const struct spi_clkreg spi_clkregs[] = { 574 [0] = { .reg = 59, 575 .div_shift = CLK_SPI0_PLL_DIV_CON_SHIFT, 576 .sel_shift = CLK_SPI0_PLL_SEL_SHIFT, }, 577 [1] = { .reg = 59, 578 .div_shift = CLK_SPI1_PLL_DIV_CON_SHIFT, 579 .sel_shift = CLK_SPI1_PLL_SEL_SHIFT, }, 580 [2] = { .reg = 60, 581 .div_shift = CLK_SPI2_PLL_DIV_CON_SHIFT, 582 .sel_shift = CLK_SPI2_PLL_SEL_SHIFT, }, 583 [3] = { .reg = 60, 584 .div_shift = CLK_SPI4_PLL_DIV_CON_SHIFT, 585 .sel_shift = CLK_SPI4_PLL_SEL_SHIFT, }, 586 [4] = { .reg = 58, 587 .div_shift = CLK_SPI5_PLL_DIV_CON_SHIFT, 588 .sel_shift = CLK_SPI5_PLL_SEL_SHIFT, }, 589 }; 590 591 static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id) 592 { 593 const struct spi_clkreg *spiclk = NULL; 594 u32 div, val; 595 596 switch (clk_id) { 597 case SCLK_SPI0 ... SCLK_SPI5: 598 spiclk = &spi_clkregs[clk_id - SCLK_SPI0]; 599 break; 600 601 default: 602 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id); 603 return -EINVAL; 604 } 605 606 val = readl(&cru->clksel_con[spiclk->reg]); 607 div = bitfield_extract(val, spiclk->div_shift, 608 CLK_SPI_PLL_DIV_CON_WIDTH); 609 610 return DIV_TO_RATE(GPLL_HZ, div); 611 } 612 613 static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) 614 { 615 const struct spi_clkreg *spiclk = NULL; 616 int src_clk_div; 617 618 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1; 619 assert(src_clk_div < 128); 620 621 switch (clk_id) { 622 case SCLK_SPI1 ... SCLK_SPI5: 623 spiclk = &spi_clkregs[clk_id - SCLK_SPI0]; 624 break; 625 626 default: 627 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id); 628 return -EINVAL; 629 } 630 631 rk_clrsetreg(&cru->clksel_con[spiclk->reg], 632 ((CLK_SPI_PLL_DIV_CON_MASK << spiclk->div_shift) | 633 (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)), 634 ((src_clk_div << spiclk->div_shift) | 635 (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift))); 636 637 return rk3399_spi_get_clk(cru, clk_id); 638 } 639 640 static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz) 641 { 642 struct pll_div vpll_config = {0}; 643 int aclk_vop = 198*MHz; 644 void *aclkreg_addr, *dclkreg_addr; 645 u32 div; 646 647 switch (clk_id) { 648 case DCLK_VOP0: 649 aclkreg_addr = &cru->clksel_con[47]; 650 dclkreg_addr = &cru->clksel_con[49]; 651 break; 652 case DCLK_VOP1: 653 aclkreg_addr = &cru->clksel_con[48]; 654 dclkreg_addr = &cru->clksel_con[50]; 655 break; 656 default: 657 return -EINVAL; 658 } 659 /* vop aclk source clk: cpll */ 660 div = CPLL_HZ / aclk_vop; 661 assert(div - 1 <= 31); 662 663 rk_clrsetreg(aclkreg_addr, 664 ACLK_VOP_PLL_SEL_MASK | ACLK_VOP_DIV_CON_MASK, 665 ACLK_VOP_PLL_SEL_CPLL << ACLK_VOP_PLL_SEL_SHIFT | 666 (div - 1) << ACLK_VOP_DIV_CON_SHIFT); 667 668 /* vop dclk source from vpll, and equals to vpll(means div == 1) */ 669 if (pll_para_config(hz, &vpll_config)) 670 return -1; 671 672 rkclk_set_pll(&cru->vpll_con[0], &vpll_config); 673 674 rk_clrsetreg(dclkreg_addr, 675 DCLK_VOP_DCLK_SEL_MASK | DCLK_VOP_PLL_SEL_MASK| 676 DCLK_VOP_DIV_CON_MASK, 677 DCLK_VOP_DCLK_SEL_DIVOUT << DCLK_VOP_DCLK_SEL_SHIFT | 678 DCLK_VOP_PLL_SEL_VPLL << DCLK_VOP_PLL_SEL_SHIFT | 679 (1 - 1) << DCLK_VOP_DIV_CON_SHIFT); 680 681 return hz; 682 } 683 684 static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id) 685 { 686 u32 div, con; 687 688 switch (clk_id) { 689 case HCLK_SDMMC: 690 case SCLK_SDMMC: 691 con = readl(&cru->clksel_con[16]); 692 /* dwmmc controller have internal div 2 */ 693 div = 2; 694 break; 695 case SCLK_EMMC: 696 con = readl(&cru->clksel_con[21]); 697 div = 1; 698 break; 699 default: 700 return -EINVAL; 701 } 702 703 div *= (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT; 704 if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT 705 == CLK_EMMC_PLL_SEL_24M) 706 return DIV_TO_RATE(OSC_HZ, div); 707 else 708 return DIV_TO_RATE(GPLL_HZ, div); 709 } 710 711 static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru, 712 ulong clk_id, ulong set_rate) 713 { 714 int src_clk_div; 715 int aclk_emmc = 198*MHz; 716 717 switch (clk_id) { 718 case HCLK_SDMMC: 719 case SCLK_SDMMC: 720 /* Select clk_sdmmc source from GPLL by default */ 721 /* mmc clock defaulg div 2 internal, provide double in cru */ 722 src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate); 723 724 if (src_clk_div > 128) { 725 /* use 24MHz source for 400KHz clock */ 726 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); 727 assert(src_clk_div - 1 < 128); 728 rk_clrsetreg(&cru->clksel_con[16], 729 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, 730 CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT | 731 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); 732 } else { 733 rk_clrsetreg(&cru->clksel_con[16], 734 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, 735 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT | 736 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); 737 } 738 break; 739 case SCLK_EMMC: 740 /* Select aclk_emmc source from GPLL */ 741 src_clk_div = DIV_ROUND_UP(GPLL_HZ , aclk_emmc); 742 assert(src_clk_div - 1 < 32); 743 744 rk_clrsetreg(&cru->clksel_con[21], 745 ACLK_EMMC_PLL_SEL_MASK | ACLK_EMMC_DIV_CON_MASK, 746 ACLK_EMMC_PLL_SEL_GPLL << ACLK_EMMC_PLL_SEL_SHIFT | 747 (src_clk_div - 1) << ACLK_EMMC_DIV_CON_SHIFT); 748 749 /* Select clk_emmc source from GPLL too */ 750 src_clk_div = DIV_ROUND_UP(GPLL_HZ, set_rate); 751 assert(src_clk_div - 1 < 128); 752 753 rk_clrsetreg(&cru->clksel_con[22], 754 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, 755 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT | 756 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); 757 break; 758 default: 759 return -EINVAL; 760 } 761 return rk3399_mmc_get_clk(cru, clk_id); 762 } 763 764 static ulong rk3399_gmac_set_clk(struct rk3399_cru *cru, ulong rate) 765 { 766 ulong ret; 767 768 /* 769 * The RGMII CLK can be derived either from an external "clkin" 770 * or can be generated from internally by a divider from SCLK_MAC. 771 */ 772 if (readl(&cru->clksel_con[19]) & BIT(4)) { 773 /* An external clock will always generate the right rate... */ 774 ret = rate; 775 } else { 776 /* 777 * No platform uses an internal clock to date. 778 * Implement this once it becomes necessary and print an error 779 * if someone tries to use it (while it remains unimplemented). 780 */ 781 pr_err("%s: internal clock is UNIMPLEMENTED\n", __func__); 782 ret = 0; 783 } 784 785 return ret; 786 } 787 788 #define PMUSGRF_DDR_RGN_CON16 0xff330040 789 static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru, 790 ulong set_rate) 791 { 792 struct pll_div dpll_cfg; 793 794 /* IC ECO bug, need to set this register */ 795 writel(0xc000c000, PMUSGRF_DDR_RGN_CON16); 796 797 /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */ 798 switch (set_rate) { 799 case 200*MHz: 800 dpll_cfg = (struct pll_div) 801 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1}; 802 break; 803 case 300*MHz: 804 dpll_cfg = (struct pll_div) 805 {.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1}; 806 break; 807 case 666*MHz: 808 dpll_cfg = (struct pll_div) 809 {.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1}; 810 break; 811 case 800*MHz: 812 dpll_cfg = (struct pll_div) 813 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}; 814 break; 815 case 933*MHz: 816 dpll_cfg = (struct pll_div) 817 {.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1}; 818 break; 819 default: 820 pr_err("Unsupported SDRAM frequency!,%ld\n", set_rate); 821 } 822 rkclk_set_pll(&cru->dpll_con[0], &dpll_cfg); 823 824 return set_rate; 825 } 826 827 static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru) 828 { 829 u32 div, val; 830 831 val = readl(&cru->clksel_con[26]); 832 div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT, 833 CLK_SARADC_DIV_CON_WIDTH); 834 835 return DIV_TO_RATE(OSC_HZ, div); 836 } 837 838 static ulong rk3399_saradc_set_clk(struct rk3399_cru *cru, uint hz) 839 { 840 int src_clk_div; 841 842 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; 843 assert(src_clk_div <= 255); 844 845 rk_clrsetreg(&cru->clksel_con[26], 846 CLK_SARADC_DIV_CON_MASK, 847 src_clk_div << CLK_SARADC_DIV_CON_SHIFT); 848 849 return rk3399_saradc_get_clk(cru); 850 } 851 852 static ulong rk3399_clk_get_rate(struct clk *clk) 853 { 854 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); 855 ulong rate = 0; 856 857 switch (clk->id) { 858 case 0 ... 63: 859 return 0; 860 case HCLK_SDMMC: 861 case SCLK_SDMMC: 862 case SCLK_EMMC: 863 rate = rk3399_mmc_get_clk(priv->cru, clk->id); 864 break; 865 case SCLK_I2C1: 866 case SCLK_I2C2: 867 case SCLK_I2C3: 868 case SCLK_I2C5: 869 case SCLK_I2C6: 870 case SCLK_I2C7: 871 rate = rk3399_i2c_get_clk(priv->cru, clk->id); 872 break; 873 case SCLK_SPI0...SCLK_SPI5: 874 rate = rk3399_spi_get_clk(priv->cru, clk->id); 875 break; 876 case SCLK_UART0: 877 case SCLK_UART1: 878 case SCLK_UART2: 879 case SCLK_UART3: 880 return 24000000; 881 break; 882 case PCLK_HDMI_CTRL: 883 break; 884 case DCLK_VOP0: 885 case DCLK_VOP1: 886 break; 887 case PCLK_EFUSE1024NS: 888 break; 889 case SCLK_SARADC: 890 rate = rk3399_saradc_get_clk(priv->cru); 891 break; 892 default: 893 return -ENOENT; 894 } 895 896 return rate; 897 } 898 899 static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) 900 { 901 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); 902 ulong ret = 0; 903 904 switch (clk->id) { 905 case 0 ... 63: 906 return 0; 907 908 case ACLK_PERIHP: 909 case HCLK_PERIHP: 910 case PCLK_PERIHP: 911 return 0; 912 913 case ACLK_PERILP0: 914 case HCLK_PERILP0: 915 case PCLK_PERILP0: 916 return 0; 917 918 case ACLK_CCI: 919 return 0; 920 921 case HCLK_PERILP1: 922 case PCLK_PERILP1: 923 return 0; 924 925 case HCLK_SDMMC: 926 case SCLK_SDMMC: 927 case SCLK_EMMC: 928 ret = rk3399_mmc_set_clk(priv->cru, clk->id, rate); 929 break; 930 case SCLK_MAC: 931 ret = rk3399_gmac_set_clk(priv->cru, rate); 932 break; 933 case SCLK_I2C1: 934 case SCLK_I2C2: 935 case SCLK_I2C3: 936 case SCLK_I2C5: 937 case SCLK_I2C6: 938 case SCLK_I2C7: 939 ret = rk3399_i2c_set_clk(priv->cru, clk->id, rate); 940 break; 941 case SCLK_SPI0...SCLK_SPI5: 942 ret = rk3399_spi_set_clk(priv->cru, clk->id, rate); 943 break; 944 case PCLK_HDMI_CTRL: 945 case PCLK_VIO_GRF: 946 /* the PCLK gates for video are enabled by default */ 947 break; 948 case DCLK_VOP0: 949 case DCLK_VOP1: 950 ret = rk3399_vop_set_clk(priv->cru, clk->id, rate); 951 break; 952 case SCLK_DDRCLK: 953 ret = rk3399_ddr_set_clk(priv->cru, rate); 954 break; 955 case PCLK_EFUSE1024NS: 956 break; 957 case SCLK_SARADC: 958 ret = rk3399_saradc_set_clk(priv->cru, rate); 959 break; 960 default: 961 return -ENOENT; 962 } 963 964 return ret; 965 } 966 967 static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk, struct clk *parent) 968 { 969 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); 970 const char *clock_output_name; 971 int ret; 972 973 /* 974 * If the requested parent is in the same clock-controller and 975 * the id is SCLK_MAC ("clk_gmac"), switch to the internal clock. 976 */ 977 if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC)) { 978 debug("%s: switching RGMII to SCLK_MAC\n", __func__); 979 rk_clrreg(&priv->cru->clksel_con[19], BIT(4)); 980 return 0; 981 } 982 983 /* 984 * Otherwise, we need to check the clock-output-names of the 985 * requested parent to see if the requested id is "clkin_gmac". 986 */ 987 ret = dev_read_string_index(parent->dev, "clock-output-names", 988 parent->id, &clock_output_name); 989 if (ret < 0) 990 return -ENODATA; 991 992 /* If this is "clkin_gmac", switch to the external clock input */ 993 if (!strcmp(clock_output_name, "clkin_gmac")) { 994 debug("%s: switching RGMII to CLKIN\n", __func__); 995 rk_setreg(&priv->cru->clksel_con[19], BIT(4)); 996 return 0; 997 } 998 999 return -EINVAL; 1000 } 1001 1002 static int __maybe_unused rk3399_clk_set_parent(struct clk *clk, struct clk *parent) 1003 { 1004 switch (clk->id) { 1005 case SCLK_RMII_SRC: 1006 return rk3399_gmac_set_parent(clk, parent); 1007 } 1008 1009 debug("%s: unsupported clk %ld\n", __func__, clk->id); 1010 return -ENOENT; 1011 } 1012 1013 static int rk3399_clk_enable(struct clk *clk) 1014 { 1015 switch (clk->id) { 1016 case HCLK_HOST0: 1017 case HCLK_HOST0_ARB: 1018 case HCLK_HOST1: 1019 case HCLK_HOST1_ARB: 1020 return 0; 1021 } 1022 1023 debug("%s: unsupported clk %ld\n", __func__, clk->id); 1024 return -ENOENT; 1025 } 1026 1027 static struct clk_ops rk3399_clk_ops = { 1028 .get_rate = rk3399_clk_get_rate, 1029 .set_rate = rk3399_clk_set_rate, 1030 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 1031 .set_parent = rk3399_clk_set_parent, 1032 #endif 1033 .enable = rk3399_clk_enable, 1034 }; 1035 1036 #ifdef CONFIG_SPL_BUILD 1037 static void rkclk_init(struct rk3399_cru *cru) 1038 { 1039 u32 aclk_div; 1040 u32 hclk_div; 1041 u32 pclk_div; 1042 1043 rk3399_configure_cpu(cru, APLL_600_MHZ, CPU_CLUSTER_LITTLE); 1044 1045 /* 1046 * some cru registers changed by bootrom, we'd better reset them to 1047 * reset/default values described in TRM to avoid confusion in kernel. 1048 * Please consider these three lines as a fix of bootrom bug. 1049 */ 1050 rk_clrsetreg(&cru->clksel_con[12], 0xffff, 0x4101); 1051 rk_clrsetreg(&cru->clksel_con[19], 0xffff, 0x033f); 1052 rk_clrsetreg(&cru->clksel_con[56], 0x0003, 0x0003); 1053 1054 /* configure gpll cpll */ 1055 rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg); 1056 rkclk_set_pll(&cru->cpll_con[0], &cpll_init_cfg); 1057 1058 /* configure perihp aclk, hclk, pclk */ 1059 aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1; 1060 assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); 1061 1062 hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1; 1063 assert((hclk_div + 1) * PERIHP_HCLK_HZ == 1064 PERIHP_ACLK_HZ && (hclk_div <= 0x3)); 1065 1066 pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1; 1067 assert((pclk_div + 1) * PERIHP_PCLK_HZ == 1068 PERIHP_ACLK_HZ && (pclk_div <= 0x7)); 1069 1070 rk_clrsetreg(&cru->clksel_con[14], 1071 PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK | 1072 ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK, 1073 pclk_div << PCLK_PERIHP_DIV_CON_SHIFT | 1074 hclk_div << HCLK_PERIHP_DIV_CON_SHIFT | 1075 ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT | 1076 aclk_div << ACLK_PERIHP_DIV_CON_SHIFT); 1077 1078 /* configure perilp0 aclk, hclk, pclk */ 1079 aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1; 1080 assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); 1081 1082 hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1; 1083 assert((hclk_div + 1) * PERILP0_HCLK_HZ == 1084 PERILP0_ACLK_HZ && (hclk_div <= 0x3)); 1085 1086 pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1; 1087 assert((pclk_div + 1) * PERILP0_PCLK_HZ == 1088 PERILP0_ACLK_HZ && (pclk_div <= 0x7)); 1089 1090 rk_clrsetreg(&cru->clksel_con[23], 1091 PCLK_PERILP0_DIV_CON_MASK | HCLK_PERILP0_DIV_CON_MASK | 1092 ACLK_PERILP0_PLL_SEL_MASK | ACLK_PERILP0_DIV_CON_MASK, 1093 pclk_div << PCLK_PERILP0_DIV_CON_SHIFT | 1094 hclk_div << HCLK_PERILP0_DIV_CON_SHIFT | 1095 ACLK_PERILP0_PLL_SEL_GPLL << ACLK_PERILP0_PLL_SEL_SHIFT | 1096 aclk_div << ACLK_PERILP0_DIV_CON_SHIFT); 1097 1098 /* perilp1 hclk select gpll as source */ 1099 hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1; 1100 assert((hclk_div + 1) * PERILP1_HCLK_HZ == 1101 GPLL_HZ && (hclk_div <= 0x1f)); 1102 1103 pclk_div = PERILP1_HCLK_HZ / PERILP1_PCLK_HZ - 1; 1104 assert((pclk_div + 1) * PERILP1_PCLK_HZ == 1105 PERILP1_HCLK_HZ && (pclk_div <= 0x7)); 1106 1107 rk_clrsetreg(&cru->clksel_con[25], 1108 PCLK_PERILP1_DIV_CON_MASK | HCLK_PERILP1_DIV_CON_MASK | 1109 HCLK_PERILP1_PLL_SEL_MASK, 1110 pclk_div << PCLK_PERILP1_DIV_CON_SHIFT | 1111 hclk_div << HCLK_PERILP1_DIV_CON_SHIFT | 1112 HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT); 1113 } 1114 #endif 1115 1116 static int rk3399_clk_probe(struct udevice *dev) 1117 { 1118 #ifdef CONFIG_SPL_BUILD 1119 struct rk3399_clk_priv *priv = dev_get_priv(dev); 1120 1121 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1122 struct rk3399_clk_plat *plat = dev_get_platdata(dev); 1123 1124 priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); 1125 #endif 1126 rkclk_init(priv->cru); 1127 #endif 1128 return 0; 1129 } 1130 1131 static int rk3399_clk_ofdata_to_platdata(struct udevice *dev) 1132 { 1133 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 1134 struct rk3399_clk_priv *priv = dev_get_priv(dev); 1135 1136 priv->cru = dev_read_addr_ptr(dev); 1137 #endif 1138 return 0; 1139 } 1140 1141 static int rk3399_clk_bind(struct udevice *dev) 1142 { 1143 int ret; 1144 struct udevice *sys_child, *sf_child; 1145 struct sysreset_reg *priv; 1146 struct softreset_reg *sf_priv; 1147 1148 /* The reset driver does not have a device node, so bind it here */ 1149 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", 1150 &sys_child); 1151 if (ret) { 1152 debug("Warning: No sysreset driver: ret=%d\n", ret); 1153 } else { 1154 priv = malloc(sizeof(struct sysreset_reg)); 1155 priv->glb_srst_fst_value = offsetof(struct rk3399_cru, 1156 glb_srst_fst_value); 1157 priv->glb_srst_snd_value = offsetof(struct rk3399_cru, 1158 glb_srst_snd_value); 1159 sys_child->priv = priv; 1160 } 1161 1162 ret = device_bind_driver_to_node(dev, "rockchip_reset", "reset", 1163 dev_ofnode(dev), &sf_child); 1164 if (ret) { 1165 debug("Warning: No rockchip reset driver: ret=%d\n", ret); 1166 } else { 1167 sf_priv = malloc(sizeof(struct softreset_reg)); 1168 sf_priv->sf_reset_offset = offsetof(struct rk3399_cru, 1169 softrst_con[0]); 1170 sf_priv->sf_reset_num = 21; 1171 sf_child->priv = sf_priv; 1172 } 1173 1174 return 0; 1175 } 1176 1177 static const struct udevice_id rk3399_clk_ids[] = { 1178 { .compatible = "rockchip,rk3399-cru" }, 1179 { } 1180 }; 1181 1182 U_BOOT_DRIVER(clk_rk3399) = { 1183 .name = "rockchip_rk3399_cru", 1184 .id = UCLASS_CLK, 1185 .of_match = rk3399_clk_ids, 1186 .priv_auto_alloc_size = sizeof(struct rk3399_clk_priv), 1187 .ofdata_to_platdata = rk3399_clk_ofdata_to_platdata, 1188 .ops = &rk3399_clk_ops, 1189 .bind = rk3399_clk_bind, 1190 .probe = rk3399_clk_probe, 1191 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1192 .platdata_auto_alloc_size = sizeof(struct rk3399_clk_plat), 1193 #endif 1194 }; 1195 1196 static ulong rk3399_i2c_get_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id) 1197 { 1198 u32 div, con; 1199 1200 switch (clk_id) { 1201 case SCLK_I2C0_PMU: 1202 con = readl(&pmucru->pmucru_clksel[2]); 1203 div = I2C_CLK_DIV_VALUE(con, 0); 1204 break; 1205 case SCLK_I2C4_PMU: 1206 con = readl(&pmucru->pmucru_clksel[3]); 1207 div = I2C_CLK_DIV_VALUE(con, 4); 1208 break; 1209 case SCLK_I2C8_PMU: 1210 con = readl(&pmucru->pmucru_clksel[2]); 1211 div = I2C_CLK_DIV_VALUE(con, 8); 1212 break; 1213 default: 1214 printf("do not support this i2c bus\n"); 1215 return -EINVAL; 1216 } 1217 1218 return DIV_TO_RATE(PPLL_HZ, div); 1219 } 1220 1221 static ulong rk3399_i2c_set_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id, 1222 uint hz) 1223 { 1224 int src_clk_div; 1225 1226 src_clk_div = PPLL_HZ / hz; 1227 assert(src_clk_div - 1 < 127); 1228 1229 switch (clk_id) { 1230 case SCLK_I2C0_PMU: 1231 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(0), 1232 I2C_PMUCLK_REG_VALUE(0, src_clk_div)); 1233 break; 1234 case SCLK_I2C4_PMU: 1235 rk_clrsetreg(&pmucru->pmucru_clksel[3], I2C_PMUCLK_REG_MASK(4), 1236 I2C_PMUCLK_REG_VALUE(4, src_clk_div)); 1237 break; 1238 case SCLK_I2C8_PMU: 1239 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(8), 1240 I2C_PMUCLK_REG_VALUE(8, src_clk_div)); 1241 break; 1242 default: 1243 printf("do not support this i2c bus\n"); 1244 return -EINVAL; 1245 } 1246 1247 return DIV_TO_RATE(PPLL_HZ, src_clk_div); 1248 } 1249 1250 static ulong rk3399_pwm_get_clk(struct rk3399_pmucru *pmucru) 1251 { 1252 u32 div, con; 1253 1254 /* PWM closk rate is same as pclk_pmu */ 1255 con = readl(&pmucru->pmucru_clksel[0]); 1256 div = con & PMU_PCLK_DIV_CON_MASK; 1257 1258 return DIV_TO_RATE(PPLL_HZ, div); 1259 } 1260 1261 static ulong rk3399_pmuclk_get_rate(struct clk *clk) 1262 { 1263 struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev); 1264 ulong rate = 0; 1265 1266 switch (clk->id) { 1267 case PCLK_RKPWM_PMU: 1268 rate = rk3399_pwm_get_clk(priv->pmucru); 1269 break; 1270 case SCLK_I2C0_PMU: 1271 case SCLK_I2C4_PMU: 1272 case SCLK_I2C8_PMU: 1273 rate = rk3399_i2c_get_pmuclk(priv->pmucru, clk->id); 1274 break; 1275 case SCLK_UART4_PMU: 1276 rate = 24000000; 1277 break; 1278 default: 1279 return -ENOENT; 1280 } 1281 1282 return rate; 1283 } 1284 1285 static ulong rk3399_pmuclk_set_rate(struct clk *clk, ulong rate) 1286 { 1287 struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev); 1288 ulong ret = 0; 1289 1290 switch (clk->id) { 1291 case SCLK_I2C0_PMU: 1292 case SCLK_I2C4_PMU: 1293 case SCLK_I2C8_PMU: 1294 ret = rk3399_i2c_set_pmuclk(priv->pmucru, clk->id, rate); 1295 break; 1296 default: 1297 return -ENOENT; 1298 } 1299 1300 return ret; 1301 } 1302 1303 static struct clk_ops rk3399_pmuclk_ops = { 1304 .get_rate = rk3399_pmuclk_get_rate, 1305 .set_rate = rk3399_pmuclk_set_rate, 1306 }; 1307 1308 #ifndef CONFIG_SPL_BUILD 1309 static void pmuclk_init(struct rk3399_pmucru *pmucru) 1310 { 1311 u32 pclk_div; 1312 1313 /* configure pmu pll(ppll) */ 1314 rkclk_set_pll(&pmucru->ppll_con[0], &ppll_init_cfg); 1315 1316 /* configure pmu pclk */ 1317 pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1; 1318 assert((pclk_div + 1) * PMU_PCLK_HZ == PPLL_HZ && pclk_div <= 0x1f); 1319 rk_clrsetreg(&pmucru->pmucru_clksel[0], 1320 PMU_PCLK_DIV_CON_MASK, 1321 pclk_div << PMU_PCLK_DIV_CON_SHIFT); 1322 } 1323 #endif 1324 1325 static int rk3399_pmuclk_probe(struct udevice *dev) 1326 { 1327 #if CONFIG_IS_ENABLED(OF_PLATDATA) || !defined(CONFIG_SPL_BUILD) 1328 struct rk3399_pmuclk_priv *priv = dev_get_priv(dev); 1329 #endif 1330 1331 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1332 struct rk3399_pmuclk_plat *plat = dev_get_platdata(dev); 1333 1334 priv->pmucru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); 1335 #endif 1336 1337 #ifndef CONFIG_SPL_BUILD 1338 pmuclk_init(priv->pmucru); 1339 #endif 1340 return 0; 1341 } 1342 1343 static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev) 1344 { 1345 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 1346 struct rk3399_pmuclk_priv *priv = dev_get_priv(dev); 1347 1348 priv->pmucru = dev_read_addr_ptr(dev); 1349 #endif 1350 return 0; 1351 } 1352 1353 static int rk3399_pmuclk_bind(struct udevice *dev) 1354 { 1355 int ret = 0; 1356 struct udevice *sf_child; 1357 struct softreset_reg *sf_priv; 1358 1359 ret = device_bind_driver_to_node(dev, "rockchip_reset", 1360 "reset", dev_ofnode(dev), 1361 &sf_child); 1362 if (ret) { 1363 debug("Warning: No rockchip reset driver: ret=%d\n", ret); 1364 } else { 1365 sf_priv = malloc(sizeof(struct softreset_reg)); 1366 sf_priv->sf_reset_offset = offsetof(struct rk3399_pmucru, 1367 pmucru_softrst_con[0]); 1368 sf_priv->sf_reset_num = 2; 1369 sf_child->priv = sf_priv; 1370 } 1371 1372 return 0; 1373 } 1374 1375 static const struct udevice_id rk3399_pmuclk_ids[] = { 1376 { .compatible = "rockchip,rk3399-pmucru" }, 1377 { } 1378 }; 1379 1380 U_BOOT_DRIVER(rockchip_rk3399_pmuclk) = { 1381 .name = "rockchip_rk3399_pmucru", 1382 .id = UCLASS_CLK, 1383 .of_match = rk3399_pmuclk_ids, 1384 .priv_auto_alloc_size = sizeof(struct rk3399_pmuclk_priv), 1385 .ofdata_to_platdata = rk3399_pmuclk_ofdata_to_platdata, 1386 .ops = &rk3399_pmuclk_ops, 1387 .probe = rk3399_pmuclk_probe, 1388 .bind = rk3399_pmuclk_bind, 1389 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1390 .platdata_auto_alloc_size = sizeof(struct rk3399_pmuclk_plat), 1391 #endif 1392 }; 1393